[llvm] [X86] Added sincos vector lib codegen test coverage (PR #183702)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 3 02:10:07 PST 2026
https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/183702
>From 0c9e285e689931fec06aaba2622c72fea4dccdc2 Mon Sep 17 00:00:00 2001
From: Aadarsh-Keshri <keshri.aadarsh123 at gmail.com>
Date: Fri, 27 Feb 2026 11:54:41 +0530
Subject: [PATCH 1/4] Inital commit
---
llvm/test/CodeGen/X86/veclib-llvm.sincos.ll | 39 +++++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/veclib-llvm.sincos.ll
diff --git a/llvm/test/CodeGen/X86/veclib-llvm.sincos.ll b/llvm/test/CodeGen/X86/veclib-llvm.sincos.ll
new file mode 100644
index 0000000000000..e8c9cb239d584
--- /dev/null
+++ b/llvm/test/CodeGen/X86/veclib-llvm.sincos.ll
@@ -0,0 +1,39 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter "(bl|ptrue)" --version 5
+; RUN: llc -mtriple=aarch64-gnu-linux -mattr=+neon,+sve -vector-library=sleefgnuabi < %s | FileCheck %s -check-prefix=SLEEF
+; RUN: llc -mtriple=aarch64-gnu-linux -mattr=+neon,+sve -vector-library=ArmPL < %s | FileCheck %s -check-prefix=ARMPL
+
+define void @test_sincos_v4f32(<4 x float> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
+ %result = call { <4 x float>, <4 x float> } @llvm.sincos.v4f32(<4 x float> %x)
+ %result.0 = extractvalue { <4 x float>, <4 x float> } %result, 0
+ %result.1 = extractvalue { <4 x float>, <4 x float> } %result, 1
+ store <4 x float> %result.0, ptr %out_sin, align 4
+ store <4 x float> %result.1, ptr %out_cos, align 4
+ ret void
+}
+
+define void @test_sincos_v2f64(<2 x double> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
+ %result = call { <2 x double>, <2 x double> } @llvm.sincos.v2f64(<2 x double> %x)
+ %result.0 = extractvalue { <2 x double>, <2 x double> } %result, 0
+ %result.1 = extractvalue { <2 x double>, <2 x double> } %result, 1
+ store <2 x double> %result.0, ptr %out_sin, align 8
+ store <2 x double> %result.1, ptr %out_cos, align 8
+ ret void
+}
+
+define void @test_sincos_nxv4f32(<vscale x 4 x float> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
+ %result = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.sincos.nxv4f32(<vscale x 4 x float> %x)
+ %result.0 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %result, 0
+ %result.1 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %result, 1
+ store <vscale x 4 x float> %result.0, ptr %out_sin, align 4
+ store <vscale x 4 x float> %result.1, ptr %out_cos, align 4
+ ret void
+}
+
+define void @test_sincos_nxv2f64(<vscale x 2 x double> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
+ %result = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.sincos.nxv2f64(<vscale x 2 x double> %x)
+ %result.0 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %result, 0
+ %result.1 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %result, 1
+ store <vscale x 2 x double> %result.0, ptr %out_sin, align 8
+ store <vscale x 2 x double> %result.1, ptr %out_cos, align 8
+ ret void
+}
>From 4eb8f9a89f9d1e38b433e4a388480e3a8ab3368e Mon Sep 17 00:00:00 2001
From: Aadarsh-Keshri <keshri.aadarsh123 at gmail.com>
Date: Fri, 27 Feb 2026 14:30:36 +0530
Subject: [PATCH 2/4] Added veclib-llvm.sincos.ll test
---
llvm/test/CodeGen/X86/veclib-llvm.sincos.ll | 268 ++++++++++++++++++--
1 file changed, 249 insertions(+), 19 deletions(-)
diff --git a/llvm/test/CodeGen/X86/veclib-llvm.sincos.ll b/llvm/test/CodeGen/X86/veclib-llvm.sincos.ll
index e8c9cb239d584..bcd2384366097 100644
--- a/llvm/test/CodeGen/X86/veclib-llvm.sincos.ll
+++ b/llvm/test/CodeGen/X86/veclib-llvm.sincos.ll
@@ -1,39 +1,269 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter "(bl|ptrue)" --version 5
-; RUN: llc -mtriple=aarch64-gnu-linux -mattr=+neon,+sve -vector-library=sleefgnuabi < %s | FileCheck %s -check-prefix=SLEEF
-; RUN: llc -mtriple=aarch64-gnu-linux -mattr=+neon,+sve -vector-library=ArmPL < %s | FileCheck %s -check-prefix=ARMPL
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter "(callq|ptrue)" --version 5
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefix=SSE
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v2 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefix=AVX
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v3 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefix=AVX2
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v4 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefix=AVX512
define void @test_sincos_v4f32(<4 x float> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
+; SSE-LABEL: test_sincos_v4f32:
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+;
+; AVX-LABEL: test_sincos_v4f32:
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+;
+; AVX2-LABEL: test_sincos_v4f32:
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+;
+; AVX512-LABEL: test_sincos_v4f32:
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
%result = call { <4 x float>, <4 x float> } @llvm.sincos.v4f32(<4 x float> %x)
%result.0 = extractvalue { <4 x float>, <4 x float> } %result, 0
%result.1 = extractvalue { <4 x float>, <4 x float> } %result, 1
- store <4 x float> %result.0, ptr %out_sin, align 4
- store <4 x float> %result.1, ptr %out_cos, align 4
+ store <4 x float> %result.0, ptr %out_sin, align 16
+ store <4 x float> %result.1, ptr %out_cos, align 16
+ ret void
+}
+
+define void @test_sincos_v8f32(<8 x float> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
+; SSE-LABEL: test_sincos_v8f32:
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+;
+; AVX-LABEL: test_sincos_v8f32:
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+;
+; AVX2-LABEL: test_sincos_v8f32:
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+;
+; AVX512-LABEL: test_sincos_v8f32:
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+ %result = call { <8 x float>, <8 x float> } @llvm.sincos.v8f32(<8 x float> %x)
+ %result.0 = extractvalue { <8 x float>, <8 x float> } %result, 0
+ %result.1 = extractvalue { <8 x float>, <8 x float> } %result, 1
+ store <8 x float> %result.0, ptr %out_sin, align 32
+ store <8 x float> %result.1, ptr %out_cos, align 32
+ ret void
+}
+
+define void @test_sincos_v16f32(<16 x float> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
+; SSE-LABEL: test_sincos_v16f32:
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+; SSE: callq sincosf at PLT
+;
+; AVX-LABEL: test_sincos_v16f32:
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+; AVX: callq sincosf at PLT
+;
+; AVX2-LABEL: test_sincos_v16f32:
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+; AVX2: callq sincosf at PLT
+;
+; AVX512-LABEL: test_sincos_v16f32:
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+; AVX512: callq sincosf at PLT
+ %result = call { <16 x float>, <16 x float> } @llvm.sincos.v16f32(<16 x float> %x)
+ %result.0 = extractvalue { <16 x float>, <16 x float> } %result, 0
+ %result.1 = extractvalue { <16 x float>, <16 x float> } %result, 1
+ store <16 x float> %result.0, ptr %out_sin, align 64
+ store <16 x float> %result.1, ptr %out_cos, align 64
ret void
}
define void @test_sincos_v2f64(<2 x double> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
+; SSE-LABEL: test_sincos_v2f64:
+; SSE: callq sincos at PLT
+; SSE: callq sincos at PLT
+;
+; AVX-LABEL: test_sincos_v2f64:
+; AVX: callq sincos at PLT
+; AVX: callq sincos at PLT
+;
+; AVX2-LABEL: test_sincos_v2f64:
+; AVX2: callq sincos at PLT
+; AVX2: callq sincos at PLT
+;
+; AVX512-LABEL: test_sincos_v2f64:
+; AVX512: callq sincos at PLT
+; AVX512: callq sincos at PLT
%result = call { <2 x double>, <2 x double> } @llvm.sincos.v2f64(<2 x double> %x)
%result.0 = extractvalue { <2 x double>, <2 x double> } %result, 0
%result.1 = extractvalue { <2 x double>, <2 x double> } %result, 1
- store <2 x double> %result.0, ptr %out_sin, align 8
- store <2 x double> %result.1, ptr %out_cos, align 8
+ store <2 x double> %result.0, ptr %out_sin, align 16
+ store <2 x double> %result.1, ptr %out_cos, align 16
ret void
}
-define void @test_sincos_nxv4f32(<vscale x 4 x float> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
- %result = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.sincos.nxv4f32(<vscale x 4 x float> %x)
- %result.0 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %result, 0
- %result.1 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } %result, 1
- store <vscale x 4 x float> %result.0, ptr %out_sin, align 4
- store <vscale x 4 x float> %result.1, ptr %out_cos, align 4
+define void @test_sincos_v4f64(<4 x double> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
+; SSE-LABEL: test_sincos_v4f64:
+; SSE: callq sincos at PLT
+; SSE: callq sincos at PLT
+; SSE: callq sincos at PLT
+; SSE: callq sincos at PLT
+;
+; AVX-LABEL: test_sincos_v4f64:
+; AVX: callq sincos at PLT
+; AVX: callq sincos at PLT
+; AVX: callq sincos at PLT
+; AVX: callq sincos at PLT
+;
+; AVX2-LABEL: test_sincos_v4f64:
+; AVX2: callq sincos at PLT
+; AVX2: callq sincos at PLT
+; AVX2: callq sincos at PLT
+; AVX2: callq sincos at PLT
+;
+; AVX512-LABEL: test_sincos_v4f64:
+; AVX512: callq sincos at PLT
+; AVX512: callq sincos at PLT
+; AVX512: callq sincos at PLT
+; AVX512: callq sincos at PLT
+ %result = call { <4 x double>, <4 x double> } @llvm.sincos.v4f64(<4 x double> %x)
+ %result.0 = extractvalue { <4 x double>, <4 x double> } %result, 0
+ %result.1 = extractvalue { <4 x double>, <4 x double> } %result, 1
+ store <4 x double> %result.0, ptr %out_sin, align 32
+ store <4 x double> %result.1, ptr %out_cos, align 32
ret void
}
-define void @test_sincos_nxv2f64(<vscale x 2 x double> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
- %result = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.sincos.nxv2f64(<vscale x 2 x double> %x)
- %result.0 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %result, 0
- %result.1 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %result, 1
- store <vscale x 2 x double> %result.0, ptr %out_sin, align 8
- store <vscale x 2 x double> %result.1, ptr %out_cos, align 8
+define void @test_sincos_v8f64(<8 x double> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
+; SSE-LABEL: test_sincos_v8f64:
+; SSE: callq sincos at PLT
+; SSE: callq sincos at PLT
+; SSE: callq sincos at PLT
+; SSE: callq sincos at PLT
+; SSE: callq sincos at PLT
+; SSE: callq sincos at PLT
+; SSE: callq sincos at PLT
+; SSE: callq sincos at PLT
+;
+; AVX-LABEL: test_sincos_v8f64:
+; AVX: callq sincos at PLT
+; AVX: callq sincos at PLT
+; AVX: callq sincos at PLT
+; AVX: callq sincos at PLT
+; AVX: callq sincos at PLT
+; AVX: callq sincos at PLT
+; AVX: callq sincos at PLT
+; AVX: callq sincos at PLT
+;
+; AVX2-LABEL: test_sincos_v8f64:
+; AVX2: callq sincos at PLT
+; AVX2: callq sincos at PLT
+; AVX2: callq sincos at PLT
+; AVX2: callq sincos at PLT
+; AVX2: callq sincos at PLT
+; AVX2: callq sincos at PLT
+; AVX2: callq sincos at PLT
+; AVX2: callq sincos at PLT
+;
+; AVX512-LABEL: test_sincos_v8f64:
+; AVX512: callq sincos at PLT
+; AVX512: callq sincos at PLT
+; AVX512: callq sincos at PLT
+; AVX512: callq sincos at PLT
+; AVX512: callq sincos at PLT
+; AVX512: callq sincos at PLT
+; AVX512: callq sincos at PLT
+; AVX512: callq sincos at PLT
+ %result = call { <8 x double>, <8 x double> } @llvm.sincos.v8f64(<8 x double> %x)
+ %result.0 = extractvalue { <8 x double>, <8 x double> } %result, 0
+ %result.1 = extractvalue { <8 x double>, <8 x double> } %result, 1
+ store <8 x double> %result.0, ptr %out_sin, align 64
+ store <8 x double> %result.1, ptr %out_cos, align 64
ret void
}
>From 1385366113d894d433fc0bc6b8dd4509f57f8f4c Mon Sep 17 00:00:00 2001
From: Aadarsh-Keshri <keshri.aadarsh123 at gmail.com>
Date: Tue, 3 Mar 2026 11:40:30 +0530
Subject: [PATCH 3/4] Eliminated redundancy while generating assertions
---
llvm/test/CodeGen/X86/veclib-llvm.sincos.ll | 271 ++++----------------
1 file changed, 57 insertions(+), 214 deletions(-)
diff --git a/llvm/test/CodeGen/X86/veclib-llvm.sincos.ll b/llvm/test/CodeGen/X86/veclib-llvm.sincos.ll
index bcd2384366097..7e9a9c28ea92e 100644
--- a/llvm/test/CodeGen/X86/veclib-llvm.sincos.ll
+++ b/llvm/test/CodeGen/X86/veclib-llvm.sincos.ll
@@ -1,33 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter "(callq|ptrue)" --version 5
-; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefix=SSE
-; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v2 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefix=AVX
-; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v3 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefix=AVX2
-; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v4 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefix=AVX512
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v2 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v3 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefixes=CHECK,AVX2
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v4 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefixes=CHECK,AVX512
define void @test_sincos_v4f32(<4 x float> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
-; SSE-LABEL: test_sincos_v4f32:
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-;
-; AVX-LABEL: test_sincos_v4f32:
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-;
-; AVX2-LABEL: test_sincos_v4f32:
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-;
-; AVX512-LABEL: test_sincos_v4f32:
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
+; CHECK-LABEL: test_sincos_v4f32:
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
%result = call { <4 x float>, <4 x float> } @llvm.sincos.v4f32(<4 x float> %x)
%result.0 = extractvalue { <4 x float>, <4 x float> } %result, 0
%result.1 = extractvalue { <4 x float>, <4 x float> } %result, 1
@@ -37,45 +19,15 @@ define void @test_sincos_v4f32(<4 x float> %x, ptr noalias %out_sin, ptr noalias
}
define void @test_sincos_v8f32(<8 x float> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
-; SSE-LABEL: test_sincos_v8f32:
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-;
-; AVX-LABEL: test_sincos_v8f32:
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-;
-; AVX2-LABEL: test_sincos_v8f32:
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-;
-; AVX512-LABEL: test_sincos_v8f32:
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
+; CHECK-LABEL: test_sincos_v8f32:
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
%result = call { <8 x float>, <8 x float> } @llvm.sincos.v8f32(<8 x float> %x)
%result.0 = extractvalue { <8 x float>, <8 x float> } %result, 0
%result.1 = extractvalue { <8 x float>, <8 x float> } %result, 1
@@ -85,77 +37,23 @@ define void @test_sincos_v8f32(<8 x float> %x, ptr noalias %out_sin, ptr noalias
}
define void @test_sincos_v16f32(<16 x float> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
-; SSE-LABEL: test_sincos_v16f32:
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-; SSE: callq sincosf at PLT
-;
-; AVX-LABEL: test_sincos_v16f32:
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-; AVX: callq sincosf at PLT
-;
-; AVX2-LABEL: test_sincos_v16f32:
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-; AVX2: callq sincosf at PLT
-;
-; AVX512-LABEL: test_sincos_v16f32:
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
-; AVX512: callq sincosf at PLT
+; CHECK-LABEL: test_sincos_v16f32:
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
+; CHECK: callq sincosf at PLT
%result = call { <16 x float>, <16 x float> } @llvm.sincos.v16f32(<16 x float> %x)
%result.0 = extractvalue { <16 x float>, <16 x float> } %result, 0
%result.1 = extractvalue { <16 x float>, <16 x float> } %result, 1
@@ -165,21 +63,9 @@ define void @test_sincos_v16f32(<16 x float> %x, ptr noalias %out_sin, ptr noali
}
define void @test_sincos_v2f64(<2 x double> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
-; SSE-LABEL: test_sincos_v2f64:
-; SSE: callq sincos at PLT
-; SSE: callq sincos at PLT
-;
-; AVX-LABEL: test_sincos_v2f64:
-; AVX: callq sincos at PLT
-; AVX: callq sincos at PLT
-;
-; AVX2-LABEL: test_sincos_v2f64:
-; AVX2: callq sincos at PLT
-; AVX2: callq sincos at PLT
-;
-; AVX512-LABEL: test_sincos_v2f64:
-; AVX512: callq sincos at PLT
-; AVX512: callq sincos at PLT
+; CHECK-LABEL: test_sincos_v2f64:
+; CHECK: callq sincos at PLT
+; CHECK: callq sincos at PLT
%result = call { <2 x double>, <2 x double> } @llvm.sincos.v2f64(<2 x double> %x)
%result.0 = extractvalue { <2 x double>, <2 x double> } %result, 0
%result.1 = extractvalue { <2 x double>, <2 x double> } %result, 1
@@ -189,29 +75,11 @@ define void @test_sincos_v2f64(<2 x double> %x, ptr noalias %out_sin, ptr noalia
}
define void @test_sincos_v4f64(<4 x double> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
-; SSE-LABEL: test_sincos_v4f64:
-; SSE: callq sincos at PLT
-; SSE: callq sincos at PLT
-; SSE: callq sincos at PLT
-; SSE: callq sincos at PLT
-;
-; AVX-LABEL: test_sincos_v4f64:
-; AVX: callq sincos at PLT
-; AVX: callq sincos at PLT
-; AVX: callq sincos at PLT
-; AVX: callq sincos at PLT
-;
-; AVX2-LABEL: test_sincos_v4f64:
-; AVX2: callq sincos at PLT
-; AVX2: callq sincos at PLT
-; AVX2: callq sincos at PLT
-; AVX2: callq sincos at PLT
-;
-; AVX512-LABEL: test_sincos_v4f64:
-; AVX512: callq sincos at PLT
-; AVX512: callq sincos at PLT
-; AVX512: callq sincos at PLT
-; AVX512: callq sincos at PLT
+; CHECK-LABEL: test_sincos_v4f64:
+; CHECK: callq sincos at PLT
+; CHECK: callq sincos at PLT
+; CHECK: callq sincos at PLT
+; CHECK: callq sincos at PLT
%result = call { <4 x double>, <4 x double> } @llvm.sincos.v4f64(<4 x double> %x)
%result.0 = extractvalue { <4 x double>, <4 x double> } %result, 0
%result.1 = extractvalue { <4 x double>, <4 x double> } %result, 1
@@ -221,45 +89,15 @@ define void @test_sincos_v4f64(<4 x double> %x, ptr noalias %out_sin, ptr noalia
}
define void @test_sincos_v8f64(<8 x double> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
-; SSE-LABEL: test_sincos_v8f64:
-; SSE: callq sincos at PLT
-; SSE: callq sincos at PLT
-; SSE: callq sincos at PLT
-; SSE: callq sincos at PLT
-; SSE: callq sincos at PLT
-; SSE: callq sincos at PLT
-; SSE: callq sincos at PLT
-; SSE: callq sincos at PLT
-;
-; AVX-LABEL: test_sincos_v8f64:
-; AVX: callq sincos at PLT
-; AVX: callq sincos at PLT
-; AVX: callq sincos at PLT
-; AVX: callq sincos at PLT
-; AVX: callq sincos at PLT
-; AVX: callq sincos at PLT
-; AVX: callq sincos at PLT
-; AVX: callq sincos at PLT
-;
-; AVX2-LABEL: test_sincos_v8f64:
-; AVX2: callq sincos at PLT
-; AVX2: callq sincos at PLT
-; AVX2: callq sincos at PLT
-; AVX2: callq sincos at PLT
-; AVX2: callq sincos at PLT
-; AVX2: callq sincos at PLT
-; AVX2: callq sincos at PLT
-; AVX2: callq sincos at PLT
-;
-; AVX512-LABEL: test_sincos_v8f64:
-; AVX512: callq sincos at PLT
-; AVX512: callq sincos at PLT
-; AVX512: callq sincos at PLT
-; AVX512: callq sincos at PLT
-; AVX512: callq sincos at PLT
-; AVX512: callq sincos at PLT
-; AVX512: callq sincos at PLT
-; AVX512: callq sincos at PLT
+; CHECK-LABEL: test_sincos_v8f64:
+; CHECK: callq sincos at PLT
+; CHECK: callq sincos at PLT
+; CHECK: callq sincos at PLT
+; CHECK: callq sincos at PLT
+; CHECK: callq sincos at PLT
+; CHECK: callq sincos at PLT
+; CHECK: callq sincos at PLT
+; CHECK: callq sincos at PLT
%result = call { <8 x double>, <8 x double> } @llvm.sincos.v8f64(<8 x double> %x)
%result.0 = extractvalue { <8 x double>, <8 x double> } %result, 0
%result.1 = extractvalue { <8 x double>, <8 x double> } %result, 1
@@ -267,3 +105,8 @@ define void @test_sincos_v8f64(<8 x double> %x, ptr noalias %out_sin, ptr noalia
store <8 x double> %result.1, ptr %out_cos, align 64
ret void
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX: {{.*}}
+; AVX2: {{.*}}
+; AVX512: {{.*}}
+; SSE: {{.*}}
>From 66bd3e8132d945ebb14cad66b4751dffdf23207f Mon Sep 17 00:00:00 2001
From: Aadarsh-Keshri <keshri.aadarsh123 at gmail.com>
Date: Tue, 3 Mar 2026 12:24:38 +0530
Subject: [PATCH 4/4] Added libmvec coverage
---
llvm/test/CodeGen/X86/veclib-llvm.sincos.ll | 26 ++++++++++++++-------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/llvm/test/CodeGen/X86/veclib-llvm.sincos.ll b/llvm/test/CodeGen/X86/veclib-llvm.sincos.ll
index 7e9a9c28ea92e..11bc122cb80c8 100644
--- a/llvm/test/CodeGen/X86/veclib-llvm.sincos.ll
+++ b/llvm/test/CodeGen/X86/veclib-llvm.sincos.ll
@@ -1,8 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter "(callq|ptrue)" --version 5
-; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v2 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefixes=CHECK,AVX
-; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v3 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefixes=CHECK,AVX2
-; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v4 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefixes=CHECK,AVX512
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefixes=CHECK,AMD,AMD-SSE
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v2 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefixes=CHECK,AMD,AMD-AVX
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v3 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefixes=CHECK,AMD,AMD-AVX2
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v4 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefixes=CHECK,AMD,AMD-AVX512
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64 -vector-library=LIBMVEC < %s | FileCheck %s --check-prefixes=CHECK,GLIBC,GLIBC-SSE
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v2 -vector-library=LIBMVEC < %s | FileCheck %s --check-prefixes=CHECK,GLIBC,GLIBC-AVX
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v3 -vector-library=LIBMVEC < %s | FileCheck %s --check-prefixes=CHECK,GLIBC,GLIBC-AVX2
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v4 -vector-library=LIBMVEC < %s | FileCheck %s --check-prefixes=CHECK,GLIBC,GLIBC-AVX512
define void @test_sincos_v4f32(<4 x float> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
; CHECK-LABEL: test_sincos_v4f32:
@@ -106,7 +110,13 @@ define void @test_sincos_v8f64(<8 x double> %x, ptr noalias %out_sin, ptr noalia
ret void
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; AVX: {{.*}}
-; AVX2: {{.*}}
-; AVX512: {{.*}}
-; SSE: {{.*}}
+; AMD: {{.*}}
+; AMD-AVX: {{.*}}
+; AMD-AVX2: {{.*}}
+; AMD-AVX512: {{.*}}
+; AMD-SSE: {{.*}}
+; GLIBC: {{.*}}
+; GLIBC-AVX: {{.*}}
+; GLIBC-AVX2: {{.*}}
+; GLIBC-AVX512: {{.*}}
+; GLIBC-SSE: {{.*}}
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