[llvm] [DAG] isKnownNeverZero - add ISD::UADDSAT/UMAX/UMIN DemandedElts handling and tests (PR #183992)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 3 01:51:51 PST 2026
https://github.com/levi42x updated https://github.com/llvm/llvm-project/pull/183992
>From 470de00a5fca83100669f426b097c715004da247 Mon Sep 17 00:00:00 2001
From: shekhar suman <shekharsuman0397 at gmail.com>
Date: Sun, 1 Mar 2026 15:03:55 +0530
Subject: [PATCH 1/6] add ISD::UADDSAT/UMAX/UMIN
---
.../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 8 ++--
.../AArch64/AArch64SelectionDAGTest.cpp | 42 +++++++++++++++++++
2 files changed, 46 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 4a2bd811b5214..fe1e41239e489 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6223,8 +6223,8 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, const APInt &DemandedElts,
}
case ISD::UADDSAT:
case ISD::UMAX:
- return isKnownNeverZero(Op.getOperand(1), Depth + 1) ||
- isKnownNeverZero(Op.getOperand(0), Depth + 1);
+ return isKnownNeverZero(Op.getOperand(1), DemandedElts, Depth + 1) ||
+ isKnownNeverZero(Op.getOperand(0), DemandedElts, Depth + 1);
// For smin/smax: If either operand is known negative/positive
// respectively we don't need the other to be known at all.
@@ -6259,8 +6259,8 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, const APInt &DemandedElts,
isKnownNeverZero(Op.getOperand(0), Depth + 1);
}
case ISD::UMIN:
- return isKnownNeverZero(Op.getOperand(1), Depth + 1) &&
- isKnownNeverZero(Op.getOperand(0), Depth + 1);
+ return isKnownNeverZero(Op.getOperand(1), DemandedElts, Depth + 1) &&
+ isKnownNeverZero(Op.getOperand(0), DemandedElts, Depth + 1);
case ISD::ROTL:
case ISD::ROTR:
diff --git a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
index b0c48e8c97995..8d2c882c285d7 100644
--- a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
+++ b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
@@ -1574,4 +1574,46 @@ TEST_F(AArch64SelectionDAGTest, KnownNeverZero_Select) {
EXPECT_FALSE(DAG->isKnownNeverZero(VSelect444Big, DemandAll));
EXPECT_TRUE(DAG->isKnownNeverZero(VSelect4444, DemandAll));
}
+
+TEST_F(AArch64SelectionDAGTest, isKnownNeverZero_UMAX_UADDSAT_DemandedElts) {
+ SDLoc Loc;
+ EVT VT = EVT::getVectorVT(Context, MVT::i32, 4);
+
+ SDValue Zero = DAG->getConstant(0, Loc, MVT::i32);
+ SDValue One = DAG->getConstant(1, Loc, MVT::i32);
+ SDValue VecConst = DAG->getBuildVector(VT, Loc, {Zero, One, Zero, Zero});
+
+ SDValue VecUnknown = DAG->getExternalSymbol("unknown_vec", VT);
+
+ APInt DemandedLane1(4, 2);
+ APInt DemandedLane0(4, 1);
+
+ SDValue OpUMAX = DAG->getNode(ISD::UMAX, Loc, VT, VecConst, VecUnknown);
+ EXPECT_TRUE(DAG->isKnownNeverZero(OpUMAX, DemandedLane1));
+ EXPECT_FALSE(DAG->isKnownNeverZero(OpUMAX, DemandedLane0));
+
+ SDValue OpUADDSAT = DAG->getNode(ISD::UADDSAT, Loc, VT, VecConst, VecUnknown);
+ EXPECT_TRUE(DAG->isKnownNeverZero(OpUADDSAT, DemandedLane1));
+ EXPECT_FALSE(DAG->isKnownNeverZero(OpUADDSAT, DemandedLane0));
+}
+
+TEST_F(AArch64SelectionDAGTest, isKnownNeverZero_UMIN_DemandedElts) {
+ SDLoc Loc;
+ EVT VT = EVT::getVectorVT(Context, MVT::i32, 4);
+
+ SDValue Zero = DAG->getConstant(0, Loc, MVT::i32);
+ SDValue One = DAG->getConstant(1, Loc, MVT::i32);
+ SDValue VecConst = DAG->getBuildVector(VT, Loc, {Zero, One, Zero, Zero});
+
+ SDValue OpaqueOne = DAG->getConstant(1, Loc, MVT::i32, /*isTarget=*/false, /*isOpaque=*/true);
+ SDValue OpaqueVec = DAG->getBuildVector(VT, Loc, {Zero, OpaqueOne, Zero, Zero});
+
+ SDValue OpUMIN = DAG->getNode(ISD::UMIN, Loc, VT, VecConst, OpaqueVec);
+
+ APInt DemandedLane1(4, 2);
+ EXPECT_TRUE(DAG->isKnownNeverZero(OpUMIN, DemandedLane1));
+
+ APInt DemandedLane0(4, 1);
+ EXPECT_FALSE(DAG->isKnownNeverZero(OpUMIN, DemandedLane0));
+}
} // end namespace llvm
>From e086d087b38328f97438b6e3efb4f7f92e3014d0 Mon Sep 17 00:00:00 2001
From: shekhar suman <shekharsuman0397 at gmail.com>
Date: Mon, 2 Mar 2026 22:10:56 +0530
Subject: [PATCH 2/6] Address review: migrate to X86 IR tests and fix
formatting
---
.../X86/is-known-never-zero-extract.ll | 69 +++++++++++++++++++
.../AArch64/AArch64SelectionDAGTest.cpp | 42 -----------
2 files changed, 69 insertions(+), 42 deletions(-)
create mode 100644 llvm/test/CodeGen/X86/is-known-never-zero-extract.ll
diff --git a/llvm/test/CodeGen/X86/is-known-never-zero-extract.ll b/llvm/test/CodeGen/X86/is-known-never-zero-extract.ll
new file mode 100644
index 0000000000000..841de79e67589
--- /dev/null
+++ b/llvm/test/CodeGen/X86/is-known-never-zero-extract.ll
@@ -0,0 +1,69 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse2 < %s | FileCheck %s
+
+declare <16 x i8> @llvm.umax.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.uaddsat.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.umin.v16i8(<16 x i8>, <16 x i8>)
+
+define i1 @test_umax_extract_never_zero(<16 x i8> %x) {
+; CHECK-LABEL: test_umax_extract_never_zero:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [u,1,u,u,u,u,u,u,u,u,u,u,u,u,u,u]
+; CHECK-NEXT: por %xmm0, %xmm1
+; CHECK-NEXT: pmaxub %xmm0, %xmm1
+; CHECK-NEXT: movd %xmm1, %eax
+; CHECK-NEXT: shrl $8, %eax
+; CHECK-NEXT: testb %al, %al
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %1 = insertelement <16 x i8> poison, i8 1, i32 1
+ %2 = or <16 x i8> %x, %1
+ %3 = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %2, <16 x i8> %x)
+ %ext = extractelement <16 x i8> %3, i32 1
+ %cmp = icmp eq i8 %ext, 0
+ ret i1 %cmp
+}
+
+define i1 @test_uaddsat_extract_never_zero(<16 x i8> %x) {
+; CHECK-LABEL: test_uaddsat_extract_never_zero:
+; CHECK: # %bb.0:
+; CHECK-NEXT: subq $24, %rsp
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: movaps %xmm0, %xmm1
+; CHECK-NEXT: movaps {{.*#+}} xmm0 = [u,1,u,u,u,u,u,u,u,u,u,u,u,u,u,u]
+; CHECK-NEXT: orps %xmm1, %xmm0
+; CHECK-NEXT: callq llvm.uaddsat.v16i8 at PLT
+; CHECK-NEXT: movaps %xmm0, (%rsp)
+; CHECK-NEXT: cmpb $0, {{[0-9]+}}(%rsp)
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: addq $24, %rsp
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: retq
+ %1 = insertelement <16 x i8> poison, i8 1, i32 1
+ %2 = or <16 x i8> %x, %1
+ %3 = call <16 x i8> @llvm.uaddsat.v16i8(<16 x i8> %2, <16 x i8> %x)
+ %ext = extractelement <16 x i8> %3, i32 1
+ %cmp = icmp eq i8 %ext, 0
+ ret i1 %cmp
+}
+
+define i1 @test_umin_extract_never_zero(<16 x i8> %x, <16 x i8> %y) {
+; CHECK-LABEL: test_umin_extract_never_zero:
+; CHECK: # %bb.0:
+; CHECK-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; CHECK-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; CHECK-NEXT: pminub %xmm0, %xmm1
+; CHECK-NEXT: movd %xmm1, %eax
+; CHECK-NEXT: shrl $8, %eax
+; CHECK-NEXT: testb %al, %al
+; CHECK-NEXT: sete %al
+; CHECK-NEXT: retq
+ %1 = insertelement <16 x i8> poison, i8 1, i32 1
+ %2 = insertelement <16 x i8> poison, i8 2, i32 1
+ %or.x = or <16 x i8> %x, %1
+ %or.y = or <16 x i8> %y, %2
+ %3 = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %or.x, <16 x i8> %or.y)
+ %ext = extractelement <16 x i8> %3, i32 1
+ %cmp = icmp eq i8 %ext, 0
+ ret i1 %cmp
+}
diff --git a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
index 8d2c882c285d7..b0c48e8c97995 100644
--- a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
+++ b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
@@ -1574,46 +1574,4 @@ TEST_F(AArch64SelectionDAGTest, KnownNeverZero_Select) {
EXPECT_FALSE(DAG->isKnownNeverZero(VSelect444Big, DemandAll));
EXPECT_TRUE(DAG->isKnownNeverZero(VSelect4444, DemandAll));
}
-
-TEST_F(AArch64SelectionDAGTest, isKnownNeverZero_UMAX_UADDSAT_DemandedElts) {
- SDLoc Loc;
- EVT VT = EVT::getVectorVT(Context, MVT::i32, 4);
-
- SDValue Zero = DAG->getConstant(0, Loc, MVT::i32);
- SDValue One = DAG->getConstant(1, Loc, MVT::i32);
- SDValue VecConst = DAG->getBuildVector(VT, Loc, {Zero, One, Zero, Zero});
-
- SDValue VecUnknown = DAG->getExternalSymbol("unknown_vec", VT);
-
- APInt DemandedLane1(4, 2);
- APInt DemandedLane0(4, 1);
-
- SDValue OpUMAX = DAG->getNode(ISD::UMAX, Loc, VT, VecConst, VecUnknown);
- EXPECT_TRUE(DAG->isKnownNeverZero(OpUMAX, DemandedLane1));
- EXPECT_FALSE(DAG->isKnownNeverZero(OpUMAX, DemandedLane0));
-
- SDValue OpUADDSAT = DAG->getNode(ISD::UADDSAT, Loc, VT, VecConst, VecUnknown);
- EXPECT_TRUE(DAG->isKnownNeverZero(OpUADDSAT, DemandedLane1));
- EXPECT_FALSE(DAG->isKnownNeverZero(OpUADDSAT, DemandedLane0));
-}
-
-TEST_F(AArch64SelectionDAGTest, isKnownNeverZero_UMIN_DemandedElts) {
- SDLoc Loc;
- EVT VT = EVT::getVectorVT(Context, MVT::i32, 4);
-
- SDValue Zero = DAG->getConstant(0, Loc, MVT::i32);
- SDValue One = DAG->getConstant(1, Loc, MVT::i32);
- SDValue VecConst = DAG->getBuildVector(VT, Loc, {Zero, One, Zero, Zero});
-
- SDValue OpaqueOne = DAG->getConstant(1, Loc, MVT::i32, /*isTarget=*/false, /*isOpaque=*/true);
- SDValue OpaqueVec = DAG->getBuildVector(VT, Loc, {Zero, OpaqueOne, Zero, Zero});
-
- SDValue OpUMIN = DAG->getNode(ISD::UMIN, Loc, VT, VecConst, OpaqueVec);
-
- APInt DemandedLane1(4, 2);
- EXPECT_TRUE(DAG->isKnownNeverZero(OpUMIN, DemandedLane1));
-
- APInt DemandedLane0(4, 1);
- EXPECT_FALSE(DAG->isKnownNeverZero(OpUMIN, DemandedLane0));
-}
} // end namespace llvm
>From 2050eb1c7a38301c5461a7a483530f4854800445 Mon Sep 17 00:00:00 2001
From: shekhar suman <shekharsuman0397 at gmail.com>
Date: Mon, 2 Mar 2026 23:34:41 +0530
Subject: [PATCH 3/6] Address review: drop custom test and regenerate
known-never-zero.ll
---
.../X86/is-known-never-zero-extract.ll | 69 -------------------
llvm/test/CodeGen/X86/known-never-zero.ll | 9 +--
2 files changed, 3 insertions(+), 75 deletions(-)
delete mode 100644 llvm/test/CodeGen/X86/is-known-never-zero-extract.ll
diff --git a/llvm/test/CodeGen/X86/is-known-never-zero-extract.ll b/llvm/test/CodeGen/X86/is-known-never-zero-extract.ll
deleted file mode 100644
index 841de79e67589..0000000000000
--- a/llvm/test/CodeGen/X86/is-known-never-zero-extract.ll
+++ /dev/null
@@ -1,69 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mattr=+sse2 < %s | FileCheck %s
-
-declare <16 x i8> @llvm.umax.v16i8(<16 x i8>, <16 x i8>)
-declare <16 x i8> @llvm.uaddsat.v16i8(<16 x i8>, <16 x i8>)
-declare <16 x i8> @llvm.umin.v16i8(<16 x i8>, <16 x i8>)
-
-define i1 @test_umax_extract_never_zero(<16 x i8> %x) {
-; CHECK-LABEL: test_umax_extract_never_zero:
-; CHECK: # %bb.0:
-; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [u,1,u,u,u,u,u,u,u,u,u,u,u,u,u,u]
-; CHECK-NEXT: por %xmm0, %xmm1
-; CHECK-NEXT: pmaxub %xmm0, %xmm1
-; CHECK-NEXT: movd %xmm1, %eax
-; CHECK-NEXT: shrl $8, %eax
-; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: retq
- %1 = insertelement <16 x i8> poison, i8 1, i32 1
- %2 = or <16 x i8> %x, %1
- %3 = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %2, <16 x i8> %x)
- %ext = extractelement <16 x i8> %3, i32 1
- %cmp = icmp eq i8 %ext, 0
- ret i1 %cmp
-}
-
-define i1 @test_uaddsat_extract_never_zero(<16 x i8> %x) {
-; CHECK-LABEL: test_uaddsat_extract_never_zero:
-; CHECK: # %bb.0:
-; CHECK-NEXT: subq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 32
-; CHECK-NEXT: movaps %xmm0, %xmm1
-; CHECK-NEXT: movaps {{.*#+}} xmm0 = [u,1,u,u,u,u,u,u,u,u,u,u,u,u,u,u]
-; CHECK-NEXT: orps %xmm1, %xmm0
-; CHECK-NEXT: callq llvm.uaddsat.v16i8 at PLT
-; CHECK-NEXT: movaps %xmm0, (%rsp)
-; CHECK-NEXT: cmpb $0, {{[0-9]+}}(%rsp)
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: addq $24, %rsp
-; CHECK-NEXT: .cfi_def_cfa_offset 8
-; CHECK-NEXT: retq
- %1 = insertelement <16 x i8> poison, i8 1, i32 1
- %2 = or <16 x i8> %x, %1
- %3 = call <16 x i8> @llvm.uaddsat.v16i8(<16 x i8> %2, <16 x i8> %x)
- %ext = extractelement <16 x i8> %3, i32 1
- %cmp = icmp eq i8 %ext, 0
- ret i1 %cmp
-}
-
-define i1 @test_umin_extract_never_zero(<16 x i8> %x, <16 x i8> %y) {
-; CHECK-LABEL: test_umin_extract_never_zero:
-; CHECK: # %bb.0:
-; CHECK-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; CHECK-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
-; CHECK-NEXT: pminub %xmm0, %xmm1
-; CHECK-NEXT: movd %xmm1, %eax
-; CHECK-NEXT: shrl $8, %eax
-; CHECK-NEXT: testb %al, %al
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: retq
- %1 = insertelement <16 x i8> poison, i8 1, i32 1
- %2 = insertelement <16 x i8> poison, i8 2, i32 1
- %or.x = or <16 x i8> %x, %1
- %or.y = or <16 x i8> %y, %2
- %3 = call <16 x i8> @llvm.umin.v16i8(<16 x i8> %or.x, <16 x i8> %or.y)
- %ext = extractelement <16 x i8> %3, i32 1
- %cmp = icmp eq i8 %ext, 0
- ret i1 %cmp
-}
diff --git a/llvm/test/CodeGen/X86/known-never-zero.ll b/llvm/test/CodeGen/X86/known-never-zero.ll
index cee4f87ba31a7..c1caf68b7cc20 100644
--- a/llvm/test/CodeGen/X86/known-never-zero.ll
+++ b/llvm/test/CodeGen/X86/known-never-zero.ll
@@ -434,18 +434,15 @@ define i32 @uaddsat_known_nonzero_vec(<16 x i8> %x, ptr %p) {
; X86-NEXT: paddusb {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: movdqa %xmm0, (%eax)
; X86-NEXT: movzbl (%eax), %eax
-; X86-NEXT: bsfl %eax, %ecx
-; X86-NEXT: movl $32, %eax
-; X86-NEXT: cmovnel %ecx, %eax
+; X86-NEXT: rep bsfl %eax, %eax
; X86-NEXT: retl
;
; X64-LABEL: uaddsat_known_nonzero_vec:
; X64: # %bb.0:
; X64-NEXT: vpaddusb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
; X64-NEXT: vmovdqa %xmm0, (%rdi)
-; X64-NEXT: vpextrb $0, %xmm0, %ecx
-; X64-NEXT: movl $32, %eax
-; X64-NEXT: rep bsfl %ecx, %eax
+; X64-NEXT: vpextrb $0, %xmm0, %eax
+; X64-NEXT: rep bsfl %eax, %eax
; X64-NEXT: retq
%z = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> <i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>)
store <16 x i8> %z, ptr %p
>From bd48d5ff727f7e5260419d0abf88fa351052b6b4 Mon Sep 17 00:00:00 2001
From: shekhar suman <shekharsuman0397 at gmail.com>
Date: Tue, 3 Mar 2026 00:07:45 +0530
Subject: [PATCH 4/6] combine ISD::UMIN with ISD::UADDSAT/UMAX
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index f03a221261d72..0f5b47980e5c2 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6264,10 +6264,17 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, const APInt &DemandedElts,
return true;
break;
}
+
case ISD::UADDSAT:
case ISD::UMAX:
- return isKnownNeverZero(Op.getOperand(1), DemandedElts, Depth + 1) ||
+ case ISD::UMIN: {
+ bool KnownOp1 = isKnownNeverZero(Op.getOperand(1), DemandedElts, Depth + 1);
+ if (Op.getOpcode() == ISD::UMIN)
+ return KnownOp1 &&
+ isKnownNeverZero(Op.getOperand(0), DemandedElts, Depth + 1);
+ return KnownOp1 ||
isKnownNeverZero(Op.getOperand(0), DemandedElts, Depth + 1);
+ }
// For smin/smax: If either operand is known negative/positive
// respectively we don't need the other to be known at all.
@@ -6301,9 +6308,6 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, const APInt &DemandedElts,
return isKnownNeverZero(Op.getOperand(1), DemandedElts, Depth + 1) &&
isKnownNeverZero(Op.getOperand(0), DemandedElts, Depth + 1);
}
- case ISD::UMIN:
- return isKnownNeverZero(Op.getOperand(1), DemandedElts, Depth + 1) &&
- isKnownNeverZero(Op.getOperand(0), DemandedElts, Depth + 1);
case ISD::ROTL:
case ISD::ROTR:
>From 994c8e2ea3decee871b862d7f2704562d217286a Mon Sep 17 00:00:00 2001
From: shekhar suman <shekharsuman0397 at gmail.com>
Date: Tue, 3 Mar 2026 03:55:32 +0530
Subject: [PATCH 5/6] separate ISD:: UMAX/UMIN
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 0f5b47980e5c2..503c5ae2b64b7 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6266,15 +6266,13 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, const APInt &DemandedElts,
}
case ISD::UADDSAT:
- case ISD::UMAX:
- case ISD::UMIN: {
- bool KnownOp1 = isKnownNeverZero(Op.getOperand(1), DemandedElts, Depth + 1);
- if (Op.getOpcode() == ISD::UMIN)
- return KnownOp1 &&
- isKnownNeverZero(Op.getOperand(0), DemandedElts, Depth + 1);
- return KnownOp1 ||
- isKnownNeverZero(Op.getOperand(0), DemandedElts, Depth + 1);
- }
+ case ISD::UMAX:
+ return isKnownNeverZero(Op.getOperand(1), DemandedElts, Depth + 1) ||
+ isKnownNeverZero(Op.getOperand(0), DemandedElts, Depth + 1);
+
+ case ISD::UMIN:
+ return isKnownNeverZero(Op.getOperand(1), DemandedElts, Depth + 1) &&
+ isKnownNeverZero(Op.getOperand(0), DemandedElts, Depth + 1);
// For smin/smax: If either operand is known negative/positive
// respectively we don't need the other to be known at all.
>From 2620c66a8baa81931e1544d78e42843d67d5ce55 Mon Sep 17 00:00:00 2001
From: shekhar suman <shekharsuman0397 at gmail.com>
Date: Tue, 3 Mar 2026 15:18:41 +0530
Subject: [PATCH 6/6] fix format
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 503c5ae2b64b7..5d63c9340f46c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6266,13 +6266,13 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, const APInt &DemandedElts,
}
case ISD::UADDSAT:
- case ISD::UMAX:
- return isKnownNeverZero(Op.getOperand(1), DemandedElts, Depth + 1) ||
- isKnownNeverZero(Op.getOperand(0), DemandedElts, Depth + 1);
+ case ISD::UMAX:
+ return isKnownNeverZero(Op.getOperand(1), DemandedElts, Depth + 1) ||
+ isKnownNeverZero(Op.getOperand(0), DemandedElts, Depth + 1);
- case ISD::UMIN:
- return isKnownNeverZero(Op.getOperand(1), DemandedElts, Depth + 1) &&
- isKnownNeverZero(Op.getOperand(0), DemandedElts, Depth + 1);
+ case ISD::UMIN:
+ return isKnownNeverZero(Op.getOperand(1), DemandedElts, Depth + 1) &&
+ isKnownNeverZero(Op.getOperand(0), DemandedElts, Depth + 1);
// For smin/smax: If either operand is known negative/positive
// respectively we don't need the other to be known at all.
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