[llvm] [RISCV] Fix type inference ambiguity in SwapSysReg pattern (PR #184305)

[via llvm-commits]

https://github.com/lihengda861-source created https://github.com/llvm/llvm-project/pull/184305

Issue:
Building RISCVInstrInfo.td fails with the following TableGen error during the generation of RISCVGenInstrInfo.inc:
     ` error: In test: Could not infer all types in pattern!`

Root Cause:
The riscv_swap_csr node has a polymorphic result type (i32 or i64 depending on the target architecture). When used inside the SwapSysReg class pattern, TableGen's type inference engine cannot automatically deduce the exact return type solely from the GPR:$rd output, leading to the ambiguity error.

Fix:
This patch resolves the type ambiguity by explicitly wrapping the riscv_swap_csr node with XLenVT, allowing TableGen to infer the types correctly.

>From 1d01610a23f8e071930ae4c0ca7e36f5eaa85211 Mon Sep 17 00:00:00 2001
From: lihengda861-source <lihengda861 at gmail.com>
Date: Tue, 3 Mar 2026 09:18:24 +0000
Subject: [PATCH] [RISCV] Fix type inference ambiguity in SwapSysReg pattern

---
 llvm/lib/Target/RISCV/RISCVInstrInfo.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index a5c0e016aaa83..eb276ef17da75 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2057,7 +2057,7 @@ class WriteSysRegImm<SysReg SR, list<Register> Regs>
 
 class SwapSysReg<SysReg SR, list<Register> Regs>
   : Pseudo<(outs GPR:$rd), (ins GPR:$val),
-           [(set GPR:$rd, (riscv_swap_csr (XLenVT SR.Encoding), (XLenVT GPR:$val)))]>,
+           [(set GPR:$rd, (XLenVT (riscv_swap_csr (XLenVT SR.Encoding), (XLenVT GPR:$val))))]>,
     PseudoInstExpansion<(CSRRW GPR:$rd, SR.Encoding, GPR:$val)> {
   let hasSideEffects = 0;
   let Uses = Regs;