[llvm] c4e2f79 - [AArch64][GlobalISel] Limit srem by const of small sizes. (#184066)

[via llvm-commits]

Author: David Green
Date: 2026-03-03T09:31:32Z
New Revision: c4e2f79c22d2e22564cba60a7f4c1b126d6dfad9

URL: https://github.com/llvm/llvm-project/commit/c4e2f79c22d2e22564cba60a7f4c1b126d6dfad9
DIFF: https://github.com/llvm/llvm-project/commit/c4e2f79c22d2e22564cba60a7f4c1b126d6dfad9.diff

LOG: [AArch64][GlobalISel] Limit srem by const of small sizes. (#184066)

The code in SignedDivisionByConstantInfo::get can only handle bitwidths
>= 3. This adds a check for bitwidth==1 for urem too, although it will
already have been simplified.

Added: 
    

Modified: 
    llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    llvm/test/CodeGen/AArch64/srem-vec-crash.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 2a5c6ef467483..f88b3f487e6cf 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -5679,7 +5679,8 @@ bool CombinerHelper::matchUDivOrURemByConst(MachineInstr &MI) const {
   AttributeList Attr = MF.getFunction().getAttributes();
   const auto &TLI = getTargetLowering();
   LLVMContext &Ctx = MF.getFunction().getContext();
-  if (TLI.isIntDivCheap(getApproximateEVTForLLT(DstTy, Ctx), Attr))
+  if (DstTy.getScalarSizeInBits() == 1 ||
+      TLI.isIntDivCheap(getApproximateEVTForLLT(DstTy, Ctx), Attr))
     return false;
 
   // Don't do this for minsize because the instruction sequence is usually
@@ -5735,7 +5736,8 @@ bool CombinerHelper::matchSDivOrSRemByConst(MachineInstr &MI) const {
   AttributeList Attr = MF.getFunction().getAttributes();
   const auto &TLI = getTargetLowering();
   LLVMContext &Ctx = MF.getFunction().getContext();
-  if (TLI.isIntDivCheap(getApproximateEVTForLLT(DstTy, Ctx), Attr))
+  if (DstTy.getScalarSizeInBits() < 3 ||
+      TLI.isIntDivCheap(getApproximateEVTForLLT(DstTy, Ctx), Attr))
     return false;
 
   // Don't do this for minsize because the instruction sequence is usually

diff  --git a/llvm/test/CodeGen/AArch64/srem-vec-crash.ll b/llvm/test/CodeGen/AArch64/srem-vec-crash.ll
index 0fce8de30d4d4..0b1e430e21105 100644
--- a/llvm/test/CodeGen/AArch64/srem-vec-crash.ll
+++ b/llvm/test/CodeGen/AArch64/srem-vec-crash.ll
@@ -1,13 +1,38 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc -mtriple=aarch64-unknown-unknown < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-unknown-unknown < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64-unknown-unknown -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 define i32 @pr84830(i1 %arg) {
-; CHECK-LABEL: pr84830:
+; CHECK-SD-LABEL: pr84830:
+; CHECK-SD:       // %bb.0: // %bb
+; CHECK-SD-NEXT:    mov w0, #1 // =0x1
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: pr84830:
+; CHECK-GI:       // %bb.0: // %bb
+; CHECK-GI-NEXT:    mov w8, #1 // =0x1
+; CHECK-GI-NEXT:    sbfx w9, w0, #0, #1
+; CHECK-GI-NEXT:    sbfx w8, w8, #0, #1
+; CHECK-GI-NEXT:    sdiv w10, w9, w8
+; CHECK-GI-NEXT:    msub w8, w10, w8, w9
+; CHECK-GI-NEXT:    eor w8, w8, #0x1
+; CHECK-GI-NEXT:    and w0, w8, #0x1
+; CHECK-GI-NEXT:    ret
+bb:
+  %new0 = srem i1 %arg, true
+  %last = zext i1 %new0 to i32
+  %i = icmp ne i32 %last, 0
+  %i1 = select i1 %i, i32 0, i32 1
+  ret i32 %i1
+}
+
+define i32 @pr84830_u(i1 %arg) {
+; CHECK-LABEL: pr84830_u:
 ; CHECK:       // %bb.0: // %bb
 ; CHECK-NEXT:    mov w0, #1 // =0x1
 ; CHECK-NEXT:    ret
 bb:
-  %new0 = srem i1 %arg, true
+  %new0 = urem i1 %arg, true
   %last = zext i1 %new0 to i32
   %i = icmp ne i32 %last, 0
   %i1 = select i1 %i, i32 0, i32 1