[llvm] [AMDGPU] Detect VALU-after-MFMA hazard in post-RA scheduler's getHazardType (PR #184084)

[Matt Arsenault via llvm-commits]

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@@ -234,6 +234,10 @@ GCNHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
       checkMAIVALUHazards(MI) > 0)
     return HazardType;
 
+  if (SIInstrInfo::isVALU(*MI) && !SIInstrInfo::isMFMA(*MI) &&
+      checkVALUImmediatelyAfterMFMAHazard(MI) > 0)
+    return HazardType;
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arsenm wrote:

I don't really follow the HazardType handling in this function. First it's confusing because "HazardType" shadows the enum type. Second, this is supposed to be distinguishing the hard-hazard that requires nops from cases where the hardware handles the hazard, with a delay penalty. 

Which hazard is this? Is this actually one that requires hazards? The closest one I've found in the manual is DL writes VGPR followed by packed FP32, but this isn't that specific 

https://github.com/llvm/llvm-project/pull/184084