[llvm] [RISCV] Remove RISCVVectorPeephole::tryToReduceVL (PR #184297)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 2 23:54:44 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Luke Lau (lukel97)
<details>
<summary>Changes</summary>
Stacked on #<!-- -->184155
Now that RISCVVLOptimizer has been extended to handle the remaining cases tryToReduceVL handles, we can remove tryToReduceVL to keep all the reduction logic in one place.
Intended to be NFC but it looks like in test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll we were previously reducing the vl of a volatile load in insert_subvector_dag_loop, which this RISCVVLOptimizer knows to avoid.
On llvm-test-suite and SPEC CPU 2017 -march=rva23u64 -O3 there are no changes with this patch.
---
Patch is 231.89 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/184297.diff
42 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+27)
- (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.h (+5)
- (modified) llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp (+19-5)
- (modified) llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp (+3-133)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/rvv/vadd.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/rvv/vfadd.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll (+2-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll (+12-11)
- (modified) llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll (+1-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll (+1-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/fmaximum-vp.ll (+13-13)
- (modified) llvm/test/CodeGen/RISCV/rvv/fminimum-vp.ll (+13-13)
- (modified) llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll (+28-24)
- (modified) llvm/test/CodeGen/RISCV/rvv/memory-args.ll (+4-3)
- (modified) llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll (+730-700)
- (removed) llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.ll (-19)
- (removed) llvm/test/CodeGen/RISCV/rvv/reduce-vl-peephole.mir (-15)
- (modified) llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-to-vmv.mir (+2-2)
- (modified) llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll (+2-1)
- (modified) llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll (+13-11)
- (modified) llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll (+41-39)
- (modified) llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll (+10-10)
- (modified) llvm/test/CodeGen/RISCV/rvv/vector-splice.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll (+62-86)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfmuladd-vp.ll (+58-78)
- (modified) llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll (+6-3)
- (modified) llvm/test/CodeGen/RISCV/rvv/vl-opt.mir (+176-1)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmax-vp.ll (+10-10)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmaxu-vp.ll (+10-10)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmin-vp.ll (+10-10)
- (modified) llvm/test/CodeGen/RISCV/rvv/vminu-vp.ll (+10-10)
- (modified) llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir (+3-3)
- (modified) llvm/test/CodeGen/RISCV/rvv/vp-vector-interleaved-access.ll (+5-5)
- (modified) llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll (+14-12)
- (modified) llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll (+30-27)
- (modified) llvm/test/CodeGen/RISCV/rvv/vsadd-vp.ll (+10-10)
- (modified) llvm/test/CodeGen/RISCV/rvv/vsaddu-vp.ll (+10-10)
- (modified) llvm/test/CodeGen/RISCV/rvv/vselect-vp.ll (+46-39)
- (modified) llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll (+3-3)
- (modified) llvm/test/CodeGen/RISCV/rvv/vssub-vp.ll (+13-13)
- (modified) llvm/test/CodeGen/RISCV/rvv/vssubu-vp.ll (+13-13)
- (modified) llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll (+6-3)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 9c71a761c3bd1..0e3fb07332cba 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -5445,3 +5445,30 @@ bool RISCVInstrInfo::requiresNTLHint(const MachineInstr &MI) const {
return true;
}
+
+bool RISCVInstrInfo::isSafeToMove(const MachineInstr &From,
+ const MachineInstr &To) {
+ assert(From.getParent() == To.getParent());
+ SmallVector<Register> PhysUses, PhysDefs;
+ for (const MachineOperand &MO : From.all_uses())
+ if (MO.getReg().isPhysical())
+ PhysUses.push_back(MO.getReg());
+ for (const MachineOperand &MO : From.all_defs())
+ if (MO.getReg().isPhysical())
+ PhysDefs.push_back(MO.getReg());
+ bool SawStore = false;
+ for (auto II = std::next(From.getIterator()); II != To.getIterator(); II++) {
+ for (Register PhysReg : PhysUses)
+ if (II->definesRegister(PhysReg, nullptr))
+ return false;
+ for (Register PhysReg : PhysDefs)
+ if (II->definesRegister(PhysReg, nullptr) ||
+ II->readsRegister(PhysReg, nullptr))
+ return false;
+ if (II->mayStore()) {
+ SawStore = true;
+ break;
+ }
+ }
+ return From.isSafeToMove(SawStore);
+}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 57a944d2977de..5c36ff7525200 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -334,6 +334,11 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
/// Return true if the instruction requires an NTL hint to be emitted.
bool requiresNTLHint(const MachineInstr &MI) const;
+ /// Return true if moving \p From down to \p To won't cause any physical
+ /// register reads or writes to be clobbered and no visible side effects are
+ /// affected. From and To must be in the same block.
+ static bool isSafeToMove(const MachineInstr &From, const MachineInstr &To);
+
/// Return true if pairing the given load or store may be paired with another.
static bool isPairableLdStInstOpc(unsigned Opc);
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index fce023cadd99c..1a81a6115c214 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -92,7 +92,7 @@ class RISCVVLOptimizer : public MachineFunctionPass {
/// For a given instruction, records what elements of it are demanded by
/// downstream users.
- DenseMap<const MachineInstr *, DemandedVL> DemandedVLs;
+ MapVector<const MachineInstr *, DemandedVL> DemandedVLs;
SetVector<const MachineInstr *> Worklist;
/// \returns all vector virtual registers that \p MI uses.
@@ -1271,10 +1271,24 @@ bool RISCVVLOptimizer::tryReduceVL(MachineInstr &MI,
VLOp.ChangeToImmediate(CommonVL.getImm());
return true;
}
- const MachineInstr *VLMI = MRI->getVRegDef(CommonVL.getReg());
- if (!MDT->dominates(VLMI, &MI)) {
- LLVM_DEBUG(dbgs() << " Abort due to VL not dominating.\n");
- return false;
+ MachineInstr *VLMI = MRI->getVRegDef(CommonVL.getReg());
+ auto VLDominates = [this, &VLMI](MachineInstr &MI) {
+ return MDT->dominates(VLMI, &MI);
+ };
+ if (!VLDominates(MI)) {
+ assert(MI.getNumExplicitDefs() == 1);
+ auto Uses = MRI->use_instructions(MI.getOperand(0).getReg());
+ auto UsesSameBB = make_filter_range(Uses, [&MI](MachineInstr &Use) {
+ return Use.getParent() == MI.getParent();
+ });
+ if (VLMI->getParent() == MI.getParent() &&
+ all_of(UsesSameBB, VLDominates) &&
+ RISCVInstrInfo::isSafeToMove(MI, *VLMI->getNextNode())) {
+ MI.moveBefore(VLMI->getNextNode());
+ } else {
+ LLVM_DEBUG(dbgs() << " Abort due to VL not dominating.\n");
+ return false;
+ }
}
LLVM_DEBUG(dbgs() << " Reduce VL from " << VLOp << " to "
<< printReg(CommonVL.getReg(), MRI->getTargetRegisterInfo())
diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index c7c8eeed02aeb..6fc2274b026e8 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -59,7 +59,6 @@ class RISCVVectorPeephole : public MachineFunctionPass {
}
private:
- bool tryToReduceVL(MachineInstr &MI) const;
bool convertToVLMAX(MachineInstr &MI) const;
bool convertToWholeRegister(MachineInstr &MI) const;
bool convertToUnmasked(MachineInstr &MI) const;
@@ -98,106 +97,6 @@ bool RISCVVectorPeephole::hasSameEEW(const MachineInstr &User,
return SrcLog2EEW == UserLog2SEW;
}
-// Attempt to reduce the VL of an instruction whose sole use is feeding a
-// instruction with a narrower VL. This currently works backwards from the
-// user instruction (which might have a smaller VL).
-bool RISCVVectorPeephole::tryToReduceVL(MachineInstr &MI) const {
- // Note that the goal here is a bit multifaceted.
- // 1) For store's reducing the VL of the value being stored may help to
- // reduce VL toggles. This is somewhat of an artifact of the fact we
- // promote arithmetic instructions but VL predicate stores.
- // 2) For vmv.v.v reducing VL eagerly on the source instruction allows us
- // to share code with the foldVMV_V_V transform below.
- //
- // Note that to the best of our knowledge, reducing VL is generally not
- // a significant win on real hardware unless we can also reduce LMUL which
- // this code doesn't try to do.
- //
- // TODO: We can handle a bunch more instructions here, and probably
- // recurse backwards through operands too.
- SmallVector<unsigned, 2> SrcIndices = {0};
- switch (RISCV::getRVVMCOpcode(MI.getOpcode())) {
- default:
- return false;
- case RISCV::VSE8_V:
- case RISCV::VSE16_V:
- case RISCV::VSE32_V:
- case RISCV::VSE64_V:
- break;
- case RISCV::VMV_V_V:
- SrcIndices[0] = 2;
- break;
- case RISCV::VMERGE_VVM:
- SrcIndices.assign({2, 3});
- break;
- case RISCV::VREDSUM_VS:
- case RISCV::VREDMAXU_VS:
- case RISCV::VREDMAX_VS:
- case RISCV::VREDMINU_VS:
- case RISCV::VREDMIN_VS:
- case RISCV::VREDAND_VS:
- case RISCV::VREDOR_VS:
- case RISCV::VREDXOR_VS:
- case RISCV::VWREDSUM_VS:
- case RISCV::VWREDSUMU_VS:
- case RISCV::VFREDUSUM_VS:
- case RISCV::VFREDOSUM_VS:
- case RISCV::VFREDMAX_VS:
- case RISCV::VFREDMIN_VS:
- case RISCV::VFWREDUSUM_VS:
- case RISCV::VFWREDOSUM_VS:
- SrcIndices[0] = 2;
- break;
- }
-
- MachineOperand &VL = MI.getOperand(RISCVII::getVLOpNum(MI.getDesc()));
- if (VL.isImm() && VL.getImm() == RISCV::VLMaxSentinel)
- return false;
-
- bool Changed = false;
- for (unsigned SrcIdx : SrcIndices) {
- Register SrcReg = MI.getOperand(SrcIdx).getReg();
- // Note: one *use*, not one *user*.
- if (!MRI->hasOneUse(SrcReg))
- continue;
-
- MachineInstr *Src = MRI->getVRegDef(SrcReg);
- if (!Src || Src->hasUnmodeledSideEffects() ||
- Src->getParent() != MI.getParent() || Src->getNumDefs() != 1 ||
- !RISCVII::hasVLOp(Src->getDesc().TSFlags) ||
- !RISCVII::hasSEWOp(Src->getDesc().TSFlags))
- continue;
-
- // Src's dest needs to have the same EEW as MI's input.
- if (!hasSameEEW(MI, *Src))
- continue;
-
- bool ElementsDependOnVL = RISCVII::elementsDependOnVL(
- TII->get(RISCV::getRVVMCOpcode(Src->getOpcode())).TSFlags);
- if (ElementsDependOnVL || Src->mayRaiseFPException())
- continue;
-
- MachineOperand &SrcVL =
- Src->getOperand(RISCVII::getVLOpNum(Src->getDesc()));
- if (VL.isIdenticalTo(SrcVL) || !RISCV::isVLKnownLE(VL, SrcVL))
- continue;
-
- if (!ensureDominates(VL, *Src))
- continue;
-
- if (VL.isImm())
- SrcVL.ChangeToImmediate(VL.getImm());
- else if (VL.isReg())
- SrcVL.ChangeToRegister(VL.getReg(), false);
-
- Changed = true;
- }
-
- // TODO: For instructions with a passthru, we could clear the passthru
- // and tail policy since we've just proven the tail is not demanded.
- return Changed;
-}
-
/// Check if an operand is an immediate or a materialized ADDI $x0, imm.
std::optional<unsigned>
RISCVVectorPeephole::getConstant(const MachineOperand &VL) const {
@@ -530,34 +429,6 @@ bool RISCVVectorPeephole::convertToUnmasked(MachineInstr &MI) const {
return true;
}
-/// Check if it's safe to move From down to To, checking that no physical
-/// registers are clobbered.
-static bool isSafeToMove(const MachineInstr &From, const MachineInstr &To) {
- assert(From.getParent() == To.getParent());
- SmallVector<Register> PhysUses, PhysDefs;
- for (const MachineOperand &MO : From.all_uses())
- if (MO.getReg().isPhysical())
- PhysUses.push_back(MO.getReg());
- for (const MachineOperand &MO : From.all_defs())
- if (MO.getReg().isPhysical())
- PhysDefs.push_back(MO.getReg());
- bool SawStore = false;
- for (auto II = std::next(From.getIterator()); II != To.getIterator(); II++) {
- for (Register PhysReg : PhysUses)
- if (II->definesRegister(PhysReg, nullptr))
- return false;
- for (Register PhysReg : PhysDefs)
- if (II->definesRegister(PhysReg, nullptr) ||
- II->readsRegister(PhysReg, nullptr))
- return false;
- if (II->mayStore()) {
- SawStore = true;
- break;
- }
- }
- return From.isSafeToMove(SawStore);
-}
-
/// Given A and B are in the same MBB, returns true if A comes before B.
static bool dominates(MachineBasicBlock::const_iterator A,
MachineBasicBlock::const_iterator B) {
@@ -585,7 +456,7 @@ bool RISCVVectorPeephole::ensureDominates(const MachineOperand &MO,
MachineInstr *Def = MRI->getVRegDef(MO.getReg());
if (Def->getParent() == Src.getParent() && !dominates(Def, Src)) {
- if (!isSafeToMove(Src, *Def->getNextNode()))
+ if (!RISCVInstrInfo::isSafeToMove(Src, *Def->getNextNode()))
return false;
Src.moveBefore(Def->getNextNode());
}
@@ -631,7 +502,7 @@ bool RISCVVectorPeephole::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
///
/// %x = PseudoVADD_V_V_M1 %passthru, %a, %b, %vl1, sew, policy
/// %y = PseudoVMV_V_V_M1 %passthru, %x, %vl2, sew, policy
-/// (where %vl1 <= %vl2, see related tryToReduceVL)
+/// (where %vl1 <= %vl2)
///
/// ->
///
@@ -674,7 +545,7 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
NeedsCommute = {OpIdx1, OpIdx2};
}
- // Src VL will have already been reduced if legal (see tryToReduceVL),
+ // Src VL will have already been reduced if legal by RISCVVLOptimizer,
// so we don't need to handle a smaller source VL here. However, the
// user's VL may be larger
MachineOperand &SrcVL = Src->getOperand(RISCVII::getVLOpNum(Src->getDesc()));
@@ -908,7 +779,6 @@ bool RISCVVectorPeephole::runOnMachineFunction(MachineFunction &MF) {
for (MachineInstr &MI : make_early_inc_range(MBB)) {
Changed |= convertToVLMAX(MI);
- Changed |= tryToReduceVL(MI);
Changed |= convertToUnmasked(MI);
Changed |= convertToWholeRegister(MI);
Changed |= convertAllOnesVMergeToVMv(MI);
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vadd.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vadd.ll
index c3cc472c4706f..e07548f45492a 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vadd.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vadd.ll
@@ -221,8 +221,8 @@ entry:
define <vscale x 64 x i8> @intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i8> %2, <vscale x 64 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv64i8_nxv64i8_nxv64i8:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
+; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
@@ -420,8 +420,8 @@ entry:
define <vscale x 32 x i16> @intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i16> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv32i16_nxv32i16_nxv32i16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
+; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
@@ -586,8 +586,8 @@ entry:
define <vscale x 16 x i32> @intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i32> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv16i32_nxv16i32_nxv16i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re32.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
+; CHECK-NEXT: vle32.v v24, (a0)
; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
@@ -719,8 +719,8 @@ entry:
define <vscale x 8 x i64> @intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i64> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i64_nxv8i64_nxv8i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vfadd.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vfadd.ll
index 1dd3a831903b5..d53c3609f88ef 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vfadd.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vfadd.ll
@@ -216,9 +216,9 @@ entry:
define <vscale x 32 x half> @intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16(<vscale x 32 x half> %0, <vscale x 32 x half> %1, <vscale x 32 x half> %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re16.v v24, (a0)
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
+; CHECK-NEXT: vle16.v v24, (a0)
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
@@ -402,9 +402,9 @@ entry:
define <vscale x 16 x float> @intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32(<vscale x 16 x float> %0, <vscale x 16 x float> %1, <vscale x 16 x float> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re32.v v24, (a0)
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
+; CHECK-NEXT: vle32.v v24, (a0)
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
@@ -551,9 +551,9 @@ entry:
define <vscale x 8 x double> @intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x double> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vl8re64.v v24, (a0)
-; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu
+; CHECK-NEXT: vle64.v v24, (a0)
+; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll b/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
index ae797de91b857..c399a1c3ca07f 100644
--- a/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
+++ b/llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
@@ -24,8 +24,6 @@ define void @last_chance_recoloring_failure() {
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 16 * vlenb
; CHECK-NEXT: li a0, 55
-; CHECK-NEXT: vsetvli a2, zero, e8, m2, ta, ma
-; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vloxseg2ei32.v v16, (a1), v8
; CHECK-NEXT: csrr a0, vlenb
@@ -35,6 +33,7 @@ define void @last_chance_recoloring_failure() {
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; CHECK-NEXT: li s0, 36
; CHECK-NEXT: vsetvli zero, s0, e16, m4, ta, ma
+; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: vfwadd.vv v16, v8, v12, v0.t
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
@@ -76,8 +75,6 @@ define void @last_chance_recoloring_failure() {
; SUBREGLIVENESS-NEXT: sub sp, sp, a0
; SUBREGLIVENESS-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x20, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 32 + 16 * vlenb
; SUBREGLIVENESS-NEXT: li a0, 55
-; SUBREGLIVENESS-NEXT: vsetvli a2, zero, e8, m2, ta, ma
-; SUBREGLIVENESS-NEXT: vmclr.m v0
; SUBREGLIVENESS-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; SUBREGLIVENESS-NEXT: vloxseg2ei32.v v16, (a1), v8
; SUBREGLIVENESS-NEXT: csrr a0, vlenb
@@ -87,6 +84,7 @@ define void @last_chance_recoloring_failure() {
; SUBREGLIVENESS-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; SUBREGLIVENESS-NEXT: li s0, 36
; SUBREGLIVENESS-NEXT: vsetvli zero, s0, e16, m4, ta, ma
+; SUBREGLIVENESS-NEXT: vmclr.m v0
; SUBREGLIVENESS-NEXT: vfwadd.vv v16, v8, v12, v0.t
; SUBREGLIVENESS-NEXT: addi a0, sp, 16
; SUBREGLIVENESS-NEXT: vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
diff --git a/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll b/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
index 4aaaa88db8b6e..dfde5607eb542 100644
--- a/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
@@ -30,13 +30,13 @@ define <vscale x 1 x i64> @access_fixed_and_vector_objects(ptr %val) {
; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: sub sp, sp, a0
; RV64IV-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x90, 0x04, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 528 + 1 * vlenb
-; RV64IV-NEXT: addi a0, sp, 8
-; RV64IV-NEXT: vl1re64.v v8, (a0)
-; RV64IV-NEXT: addi a0, sp, 528
-; RV64IV-NEXT: vl1re64.v v9, (a0)
; RV64IV-NEXT: ld a0, 520(sp)
+; RV64IV-NEXT: addi a1, sp, 8
+; RV64IV-NEXT: addi a2, sp, 528
; RV64IV-NEXT: vsetvli zero, a0, e64, m1, ta, ma
-; RV64IV-NEXT: vadd.vv v8, v8, v9
+; RV64IV-NEXT: vle64.v v8, (a2)
+; RV64IV-NEXT: vle64.v v9, (a1)
+; RV64IV-NEXT: vadd.vv v8, v9, v8
; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: add sp, sp, a0
; RV64IV-NEXT: .cfi_def_cfa sp, 528
@@ -76,13 +76,14 @@ define <vscale x 1 x i64> @probe_fixed_and_vector_objects(ptr %val, <vscale x 1
; RV64IV-NEXT: .cfi_def_cfa_register sp
; RV64IV-NEXT: sub sp, sp, t1
; RV64IV-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x90, 0x04, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 528 + 1 * vlenb
-; RV64IV-NEXT: addi a0, sp, 8
-; RV64IV-NEXT: vl1re64.v v9, (a0)
-; RV64IV-NEXT: addi a0, sp, 528
-; RV64IV-NEXT: vl1re64.v v10, (a0)
; RV64IV-NEXT: ld a0, 520(sp)
-; RV64IV-NEXT: vsetvli zero, a0, e64, m1, tu, ma
-; RV64IV-NEXT: vadd.vv v8, v9, v10
+; RV64IV-NEXT: addi a1, sp, 8
+; RV64IV-NEXT: addi a2, sp, 528
+; RV64IV-NEXT: vsetvli zero, a0, e64, m1, ta, ma
+; RV64IV-NEXT: vle64.v v9, (a2)
+; RV64IV-NEXT: vle64.v v10, (a1)
+; RV64IV-NEXT: vsetvli zero, zero, e64, m1, tu, ma
+; RV64IV-NEXT: vadd.vv v8, v10, v9
; RV64IV-NEXT: csrr a0, vlenb
; RV64IV-NEXT: add sp, sp, a0
; RV64IV-NEXT: .cfi_def_cfa sp, 528
diff --git a/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll b/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
index 96252f070a580..550869b10d3f3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/combine-reduce-add-to-vcpop.ll
@@ -191,11 +191,10 @@ define i32 @test_nxv1i1(<vscale x 1 x i1> %x) {
;
; ZVE-LABEL: test_nxv1i1:
; ZVE: # %bb.0: # %entry
-; ZVE-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; ZVE-NEXT: ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/184297
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