[llvm] [RISCV] Sink instructions so AVL dominates in RISCVVLOptimizer (PR #184155)

[Luke Lau via llvm-commits]

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@@ -1255,10 +1255,20 @@ bool RISCVVLOptimizer::tryReduceVL(MachineInstr &MI,
     VLOp.ChangeToImmediate(CommonVL.getImm());
     return true;
   }
-  const MachineInstr *VLMI = MRI->getVRegDef(CommonVL.getReg());
-  if (!MDT->dominates(VLMI, &MI)) {
-    LLVM_DEBUG(dbgs() << "  Abort due to VL not dominating.\n");
-    return false;
+  MachineInstr *VLMI = MRI->getVRegDef(CommonVL.getReg());
+  auto VLDominates = [this, &VLMI](MachineInstr &MI) {
+    return MDT->dominates(VLMI, &MI);
+  };
+  if (!VLDominates(MI)) {
+    assert(MI.getNumExplicitDefs() == 1);
+    if (VLMI->getParent() == MI.getParent() &&
+        all_of(MRI->use_instructions(MI.getOperand(0).getReg()), VLDominates) &&
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lukel97 wrote:

Good catch, I've relaxed it now and added a test in 4dc5ba73b1a46458facc438e7c30642ec659b5a3 / 70e7fb2f52b7

https://github.com/llvm/llvm-project/pull/184155