[llvm] [AArch64] Fix type mismatch in bitconvert + vec_extract patterns (PR #183549)

[David Green via llvm-commits]

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@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple aarch64-none-linux-gnu -stop-after=finalize-isel | FileCheck %s --check-prefix=CHECK
+
+define half @test_vext_v8i16_0(<8 x i16> %a) {
+  ; CHECK-LABEL: name: test_vext_v8i16_0
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   liveins: $q0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:fpr128 = COPY $q0
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
+  ; CHECK-NEXT:   $h0 = COPY [[COPY2]]
+  ; CHECK-NEXT:   RET_ReallyLR implicit $h0
+entry:
+  %b = extractelement <8 x i16> %a, i32 0
+  %c = bitcast i16 %b to half
+  ret half %c
+
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davemgreen wrote:

Can remove this blank line.

https://github.com/llvm/llvm-project/pull/183549