[llvm] [RISCV] Promote i8/i16/i32 scalable vector CLMUL to i64 CLMUL with Zvbc. (PR #184265)

[Pengcheng Wang via llvm-commits]

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@@ -1116,8 +1116,18 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
         }
       }
 
-      if (Subtarget.hasStdExtZvbc() && VT.getVectorElementType() == MVT::i64)
-        setOperationAction({ISD::CLMUL, ISD::CLMULH}, VT, Legal);
+      if (Subtarget.hasStdExtZvbc() && Subtarget.hasVInstructionsI64()) {
+        if (VT.getVectorElementType() == MVT::i64)
+          setOperationAction({ISD::CLMUL, ISD::CLMULH}, VT, Legal);
+        else {
+          // Promote to i64 if the lmul is small enough.
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wangpc-pp wrote:

Can we add a TODO for Zvbc32e?

https://github.com/llvm/llvm-project/pull/184265