[llvm] [AMDGPU] Implement LSR cost model for GFX9+ (PR #184138)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions h,cpp -- llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
index d50dd5bbb..eb7911737 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp
@@ -15,8 +15,8 @@
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPUTargetTransformInfo.h"
-#include "AMDGPUTargetMachine.h"
 #include "AMDGPUSubtarget.h"
+#include "AMDGPUTargetMachine.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "SIModeRegisterDefaults.h"
 #include "llvm/Analysis/InlineCost.h"
@@ -1706,9 +1706,9 @@ GCNTTIImpl::getInstructionUniformity(const Value *V) const {
 }
 
 InstructionCost GCNTTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
-                                                  StackOffset BaseOffset,
-                                                  bool HasBaseReg, int64_t Scale,
-                                                  unsigned AddrSpace) const {
+                                                 StackOffset BaseOffset,
+                                                 bool HasBaseReg, int64_t Scale,
+                                                 unsigned AddrSpace) const {
   // AMDGPU has limited addressing modes. base+scale*index requires an extra
   // ADD instruction, unlike architectures with rich addressing modes.
   if (HasBaseReg && Scale != 0)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
index 24d4ec8d8..dc7d01533 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h
@@ -313,8 +313,8 @@ public:
   InstructionUniformity getInstructionUniformity(const Value *V) const override;
 
   InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
-                                       StackOffset BaseOffset,
-                                       bool HasBaseReg, int64_t Scale,
+                                       StackOffset BaseOffset, bool HasBaseReg,
+                                       int64_t Scale,
                                        unsigned AddrSpace) const override;
 
   bool isLSRCostLess(const TTI::LSRCost &A,

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https://github.com/llvm/llvm-project/pull/184138