[llvm] [AMDGPU] Exec-protect regular VGPR spill saves under narrowed exec (PR #184135)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 2c86ab1d7..055199976 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -2463,7 +2463,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
       Register ExecCopyReg = MFI->getSGPRForEXECCopy();
       if (ExecCopyReg) {
         TII->insertScratchExecCopy(*MF, *MBB, MI, DL, ExecCopyReg,
-                                  RS->isRegUsed(AMDGPU::SCC));
+                                   RS->isRegUsed(AMDGPU::SCC));
       }
       buildSpillLoadStore(
           *MBB, MI, DL, Opc, Index, VData->getReg(), VData->isKill(), FrameReg,
@@ -2547,8 +2547,7 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
       }
 
       auto *MBB = MI->getParent();
-      bool IsWWMRegSpill =
-          TII->isWWMRegSpillOpcode(MI->getOpcode());
+      bool IsWWMRegSpill = TII->isWWMRegSpillOpcode(MI->getOpcode());
       Register ExecCopyReg =
           IsWWMRegSpill ? MFI->getSGPRForEXECCopy() : Register();
       if (ExecCopyReg) {

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https://github.com/llvm/llvm-project/pull/184135