[llvm] e0fa495 - [ARM] Format ARMLoadStoreOptimizer Pass classes. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 2 06:21:19 PST 2026
Author: David Green
Date: 2026-03-02T14:21:12Z
New Revision: e0fa4952fd7853c542639f0747a8a06435486a7d
URL: https://github.com/llvm/llvm-project/commit/e0fa4952fd7853c542639f0747a8a06435486a7d
DIFF: https://github.com/llvm/llvm-project/commit/e0fa4952fd7853c542639f0747a8a06435486a7d.diff
LOG: [ARM] Format ARMLoadStoreOptimizer Pass classes. NFC
These will need modifications to support the NPM, pre-format the classes to
reduce the needed differences.
Added:
Modified:
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index db37b769efcad..de56822565441 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -96,103 +96,105 @@ AssumeMisalignedLoadStores("arm-assume-misaligned-load-store", cl::Hidden,
namespace {
- /// Post- register allocation pass the combine load / store instructions to
- /// form ldm / stm instructions.
- struct ARMLoadStoreOpt : public MachineFunctionPass {
- static char ID;
-
- const MachineFunction *MF;
- const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
- const ARMSubtarget *STI;
- const TargetLowering *TL;
- ARMFunctionInfo *AFI;
- LiveRegUnits LiveRegs;
- RegisterClassInfo RegClassInfo;
- MachineBasicBlock::const_iterator LiveRegPos;
- bool LiveRegsValid;
- bool RegClassInfoValid;
- bool isThumb1, isThumb2;
-
- ARMLoadStoreOpt() : MachineFunctionPass(ID) {}
-
- bool runOnMachineFunction(MachineFunction &Fn) override;
-
- MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties().setNoVRegs();
- }
+/// Post- register allocation pass the combine load / store instructions to
+/// form ldm / stm instructions.
+struct ARMLoadStoreOpt : public MachineFunctionPass {
+ static char ID;
+
+ const MachineFunction *MF;
+ const TargetInstrInfo *TII;
+ const TargetRegisterInfo *TRI;
+ const ARMSubtarget *STI;
+ const TargetLowering *TL;
+ ARMFunctionInfo *AFI;
+ LiveRegUnits LiveRegs;
+ RegisterClassInfo RegClassInfo;
+ MachineBasicBlock::const_iterator LiveRegPos;
+ bool LiveRegsValid;
+ bool RegClassInfoValid;
+ bool isThumb1, isThumb2;
+
+ ARMLoadStoreOpt() : MachineFunctionPass(ID) {}
+
+ bool runOnMachineFunction(MachineFunction &Fn) override;
+
+ MachineFunctionProperties getRequiredProperties() const override {
+ return MachineFunctionProperties().setNoVRegs();
+ }
- StringRef getPassName() const override { return ARM_LOAD_STORE_OPT_NAME; }
+ StringRef getPassName() const override { return ARM_LOAD_STORE_OPT_NAME; }
- private:
- /// A set of load/store MachineInstrs with same base register sorted by
- /// offset.
- struct MemOpQueueEntry {
- MachineInstr *MI;
- int Offset; ///< Load/Store offset.
- unsigned Position; ///< Position as counted from end of basic block.
+private:
+ /// A set of load/store MachineInstrs with same base register sorted by
+ /// offset.
+ struct MemOpQueueEntry {
+ MachineInstr *MI;
+ int Offset; ///< Load/Store offset.
+ unsigned Position; ///< Position as counted from end of basic block.
- MemOpQueueEntry(MachineInstr &MI, int Offset, unsigned Position)
- : MI(&MI), Offset(Offset), Position(Position) {}
- };
- using MemOpQueue = SmallVector<MemOpQueueEntry, 8>;
+ MemOpQueueEntry(MachineInstr &MI, int Offset, unsigned Position)
+ : MI(&MI), Offset(Offset), Position(Position) {}
+ };
+ using MemOpQueue = SmallVector<MemOpQueueEntry, 8>;
- /// A set of MachineInstrs that fulfill (nearly all) conditions to get
- /// merged into a LDM/STM.
- struct MergeCandidate {
- /// List of instructions ordered by load/store offset.
- SmallVector<MachineInstr*, 4> Instrs;
+ /// A set of MachineInstrs that fulfill (nearly all) conditions to get
+ /// merged into a LDM/STM.
+ struct MergeCandidate {
+ /// List of instructions ordered by load/store offset.
+ SmallVector<MachineInstr *, 4> Instrs;
- /// Index in Instrs of the instruction being latest in the schedule.
- unsigned LatestMIIdx;
+ /// Index in Instrs of the instruction being latest in the schedule.
+ unsigned LatestMIIdx;
- /// Index in Instrs of the instruction being earliest in the schedule.
- unsigned EarliestMIIdx;
+ /// Index in Instrs of the instruction being earliest in the schedule.
+ unsigned EarliestMIIdx;
- /// Index into the basic block where the merged instruction will be
- /// inserted. (See MemOpQueueEntry.Position)
- unsigned InsertPos;
+ /// Index into the basic block where the merged instruction will be
+ /// inserted. (See MemOpQueueEntry.Position)
+ unsigned InsertPos;
- /// Whether the instructions can be merged into a ldm/stm instruction.
- bool CanMergeToLSMulti;
+ /// Whether the instructions can be merged into a ldm/stm instruction.
+ bool CanMergeToLSMulti;
- /// Whether the instructions can be merged into a ldrd/strd instruction.
- bool CanMergeToLSDouble;
- };
- SpecificBumpPtrAllocator<MergeCandidate> Allocator;
- SmallVector<const MergeCandidate*,4> Candidates;
- SmallVector<MachineInstr*,4> MergeBaseCandidates;
-
- void moveLiveRegsBefore(const MachineBasicBlock &MBB,
- MachineBasicBlock::const_iterator Before);
- unsigned findFreeReg(const TargetRegisterClass &RegClass);
- void UpdateBaseRegUses(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
- unsigned Base, unsigned WordOffset,
- ARMCC::CondCodes Pred, unsigned PredReg);
- MachineInstr *CreateLoadStoreMulti(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
- int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
- ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
- ArrayRef<std::pair<unsigned, bool>> Regs,
- ArrayRef<MachineInstr*> Instrs);
- MachineInstr *CreateLoadStoreDouble(
- MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
- int Offset, unsigned Base, bool BaseKill, unsigned Opcode,
- ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
- ArrayRef<std::pair<unsigned, bool>> Regs,
- ArrayRef<MachineInstr*> Instrs) const;
- void FormCandidates(const MemOpQueue &MemOps);
- MachineInstr *MergeOpsUpdate(const MergeCandidate &Cand);
- bool FixInvalidRegPairOp(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI);
- bool MergeBaseUpdateLoadStore(MachineInstr *MI);
- bool MergeBaseUpdateLSMultiple(MachineInstr *MI);
- bool MergeBaseUpdateLSDouble(MachineInstr &MI) const;
- bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
- bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
- bool CombineMovBx(MachineBasicBlock &MBB);
+ /// Whether the instructions can be merged into a ldrd/strd instruction.
+ bool CanMergeToLSDouble;
};
+ SpecificBumpPtrAllocator<MergeCandidate> Allocator;
+ SmallVector<const MergeCandidate *, 4> Candidates;
+ SmallVector<MachineInstr *, 4> MergeBaseCandidates;
+
+ void moveLiveRegsBefore(const MachineBasicBlock &MBB,
+ MachineBasicBlock::const_iterator Before);
+ unsigned findFreeReg(const TargetRegisterClass &RegClass);
+ void UpdateBaseRegUses(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
+ unsigned Base, unsigned WordOffset,
+ ARMCC::CondCodes Pred, unsigned PredReg);
+ MachineInstr *CreateLoadStoreMulti(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator InsertBefore,
+ int Offset, unsigned Base, bool BaseKill,
+ unsigned Opcode, ARMCC::CondCodes Pred,
+ unsigned PredReg, const DebugLoc &DL,
+ ArrayRef<std::pair<unsigned, bool>> Regs,
+ ArrayRef<MachineInstr *> Instrs);
+ MachineInstr *CreateLoadStoreDouble(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator InsertBefore,
+ int Offset, unsigned Base, bool BaseKill,
+ unsigned Opcode, ARMCC::CondCodes Pred,
+ unsigned PredReg, const DebugLoc &DL,
+ ArrayRef<std::pair<unsigned, bool>> Regs,
+ ArrayRef<MachineInstr *> Instrs) const;
+ void FormCandidates(const MemOpQueue &MemOps);
+ MachineInstr *MergeOpsUpdate(const MergeCandidate &Cand);
+ bool FixInvalidRegPairOp(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator &MBBI);
+ bool MergeBaseUpdateLoadStore(MachineInstr *MI);
+ bool MergeBaseUpdateLSMultiple(MachineInstr *MI);
+ bool MergeBaseUpdateLSDouble(MachineInstr &MI) const;
+ bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
+ bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
+ bool CombineMovBx(MachineBasicBlock &MBB);
+};
} // end anonymous namespace
@@ -2134,48 +2136,48 @@ bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
namespace {
- /// Pre- register allocation pass that move load / stores from consecutive
- /// locations close to make it more likely they will be combined later.
- struct ARMPreAllocLoadStoreOpt : public MachineFunctionPass{
- static char ID;
+/// Pre- register allocation pass that move load / stores from consecutive
+/// locations close to make it more likely they will be combined later.
+struct ARMPreAllocLoadStoreOpt : public MachineFunctionPass {
+ static char ID;
- AliasAnalysis *AA;
- const DataLayout *TD;
- const TargetInstrInfo *TII;
- const TargetRegisterInfo *TRI;
- const ARMSubtarget *STI;
- MachineRegisterInfo *MRI;
- MachineDominatorTree *DT;
- MachineFunction *MF;
+ AliasAnalysis *AA;
+ const DataLayout *TD;
+ const TargetInstrInfo *TII;
+ const TargetRegisterInfo *TRI;
+ const ARMSubtarget *STI;
+ MachineRegisterInfo *MRI;
+ MachineDominatorTree *DT;
+ MachineFunction *MF;
- ARMPreAllocLoadStoreOpt() : MachineFunctionPass(ID) {}
+ ARMPreAllocLoadStoreOpt() : MachineFunctionPass(ID) {}
- bool runOnMachineFunction(MachineFunction &Fn) override;
+ bool runOnMachineFunction(MachineFunction &Fn) override;
- StringRef getPassName() const override {
- return ARM_PREALLOC_LOAD_STORE_OPT_NAME;
- }
+ StringRef getPassName() const override {
+ return ARM_PREALLOC_LOAD_STORE_OPT_NAME;
+ }
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.addRequired<AAResultsWrapperPass>();
- AU.addRequired<MachineDominatorTreeWrapperPass>();
- AU.addPreserved<MachineDominatorTreeWrapperPass>();
- MachineFunctionPass::getAnalysisUsage(AU);
- }
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.addRequired<AAResultsWrapperPass>();
+ AU.addRequired<MachineDominatorTreeWrapperPass>();
+ AU.addPreserved<MachineDominatorTreeWrapperPass>();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
- private:
- bool CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl,
- unsigned &NewOpc, Register &EvenReg, Register &OddReg,
- Register &BaseReg, int &Offset, Register &PredReg,
- ARMCC::CondCodes &Pred, bool &isT2);
- bool RescheduleOps(
- MachineBasicBlock *MBB, SmallVectorImpl<MachineInstr *> &Ops,
- unsigned Base, bool isLd, DenseMap<MachineInstr *, unsigned> &MI2LocMap,
- SmallDenseMap<Register, SmallVector<MachineInstr *>, 8> &RegisterMap);
- bool RescheduleLoadStoreInstrs(MachineBasicBlock *MBB);
- bool DistributeIncrements();
- bool DistributeIncrements(Register Base);
- };
+private:
+ bool CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl,
+ unsigned &NewOpc, Register &EvenReg, Register &OddReg,
+ Register &BaseReg, int &Offset, Register &PredReg,
+ ARMCC::CondCodes &Pred, bool &isT2);
+ bool RescheduleOps(
+ MachineBasicBlock *MBB, SmallVectorImpl<MachineInstr *> &Ops,
+ unsigned Base, bool isLd, DenseMap<MachineInstr *, unsigned> &MI2LocMap,
+ SmallDenseMap<Register, SmallVector<MachineInstr *>, 8> &RegisterMap);
+ bool RescheduleLoadStoreInstrs(MachineBasicBlock *MBB);
+ bool DistributeIncrements();
+ bool DistributeIncrements(Register Base);
+};
} // end anonymous namespace
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