[llvm] [RISCV] Handle Zvabd and XRivosVizip EEWs in RISCVVLOptimizer (PR #184117)
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 2 05:23:16 PST 2026
https://github.com/lukel97 created https://github.com/llvm/llvm-project/pull/184117
This allows the VL optimizer to handle more cases that RISCVVectorPeephole currently catches.
The XRivosVizip instructions have ReadsPastVL=true, so only the vl of the zip instruction itself is reduced, not its inputs.
>From 769274022205a205ba875da4e663b198435ae5bc Mon Sep 17 00:00:00 2001
From: Luke Lau <luke at igalia.com>
Date: Mon, 2 Mar 2026 21:20:30 +0800
Subject: [PATCH] [RISCV] Handle Zvabd and XRivosVizip EEWs in RISCVVLOptimizer
This allows the VL optimizer to handle more cases that RISCVVectorPeephole currently catches.
The XRivosVizip instructions have ReadsPastVL=true, so only the vl of the zip instruction itself is reduced, not its inputs.
---
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 16 ++++++++++++++++
.../rvv/fixed-vectors-shuffle-deinterleave2.ll | 4 ++--
llvm/test/CodeGen/RISCV/rvv/vabd.ll | 4 ++--
llvm/test/CodeGen/RISCV/rvv/vabdu.ll | 4 ++--
llvm/test/CodeGen/RISCV/rvv/vl-opt.mir | 2 +-
5 files changed, 23 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 99eaf2683e1cc..fce023cadd99c 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -586,6 +586,19 @@ static std::optional<unsigned> getOperandLog2EEW(const MachineOperand &MO) {
// Vector Carry-less Multiply Return High Half
case RISCV::VCLMULH_VV:
case RISCV::VCLMULH_VX:
+
+ // Zvabd
+ case RISCV::VABS_V:
+ case RISCV::VABD_VV:
+ case RISCV::VABDU_VV:
+
+ // XRivosVizip
+ case RISCV::RI_VZIPEVEN_VV:
+ case RISCV::RI_VZIPODD_VV:
+ case RISCV::RI_VZIP2A_VV:
+ case RISCV::RI_VZIP2B_VV:
+ case RISCV::RI_VUNZIP2A_VV:
+ case RISCV::RI_VUNZIP2B_VV:
return MILog2SEW;
// Vector Widening Shift Left Logical (Zvbb)
@@ -651,6 +664,9 @@ static std::optional<unsigned> getOperandLog2EEW(const MachineOperand &MO) {
case RISCV::VFWCVT_F_X_V:
case RISCV::VFWCVT_F_F_V:
case RISCV::VFWCVTBF16_F_F_V:
+ // Zvabd
+ case RISCV::VWABDA_VV:
+ case RISCV::VWABDAU_VV:
return IsMODef ? MILog2SEW + 1 : MILog2SEW;
// Def and Op1 uses EEW=2*SEW. Op2 uses EEW=SEW.
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
index 06c3bc656f16a..3a14f87c3f18a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave2.ll
@@ -415,8 +415,8 @@ define void @vnsrl_0_double(ptr %in, ptr %out) {
; ZIP: # %bb.0: # %entry
; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
; ZIP-NEXT: vle64.v v8, (a0)
-; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9
; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZIP-NEXT: ri.vunzip2a.vv v10, v8, v9
; ZIP-NEXT: vse64.v v10, (a1)
; ZIP-NEXT: ret
entry:
@@ -450,8 +450,8 @@ define void @vnsrl_64_double(ptr %in, ptr %out) {
; ZIP: # %bb.0: # %entry
; ZIP-NEXT: vsetivli zero, 4, e64, m1, ta, ma
; ZIP-NEXT: vle64.v v8, (a0)
-; ZIP-NEXT: ri.vunzip2b.vv v10, v8, v9
; ZIP-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; ZIP-NEXT: ri.vunzip2b.vv v10, v8, v9
; ZIP-NEXT: vse64.v v10, (a1)
; ZIP-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vabd.ll b/llvm/test/CodeGen/RISCV/rvv/vabd.ll
index f3750e7f4513d..189131ee14360 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vabd.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vabd.ll
@@ -167,8 +167,8 @@ define <vscale x 64 x i8> @vabd_vv_i8m8(<vscale x 64 x i8> %a, <vscale x 64 x i8
define <vscale x 64 x i8> @vabd_vv_mask_i8m8(<vscale x 64 x i8> %passthru, <vscale x 64 x i8> %a, <vscale x 64 x i8> %b, <vscale x 64 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabd_vv_mask_i8m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
+; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vabd.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 64 x i8> @llvm.riscv.vabd.mask(
@@ -318,8 +318,8 @@ define <vscale x 32 x i16> @vabd_vv_i16m8(<vscale x 32 x i16> %a, <vscale x 32 x
define <vscale x 32 x i16> @vabd_vv_mask_i16m8(<vscale x 32 x i16> %passthru, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b, <vscale x 32 x i1> %mask,iXLen %vl) {
; CHECK-LABEL: vabd_vv_mask_i16m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
+; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vabd.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 32 x i16> @llvm.riscv.vabd.mask(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vabdu.ll b/llvm/test/CodeGen/RISCV/rvv/vabdu.ll
index e629e41b61172..0592b28b370b9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vabdu.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vabdu.ll
@@ -167,8 +167,8 @@ define <vscale x 64 x i8> @vabdu_vv_i8m8(<vscale x 64 x i8> %a, <vscale x 64 x i
define <vscale x 64 x i8> @vabdu_vv_mask_i8m8(<vscale x 64 x i8> %passthru, <vscale x 64 x i8> %a, <vscale x 64 x i8> %b, <vscale x 64 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_mask_i8m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
+; CHECK-NEXT: vle8.v v24, (a0)
; CHECK-NEXT: vabdu.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 64 x i8> @llvm.riscv.vabdu.mask(
@@ -318,8 +318,8 @@ define <vscale x 32 x i16> @vabdu_vv_i16m8(<vscale x 32 x i16> %a, <vscale x 32
define <vscale x 32 x i16> @vabdu_vv_mask_i16m8(<vscale x 32 x i16> %passthru, <vscale x 32 x i16> %a, <vscale x 32 x i16> %b, <vscale x 32 x i1> %mask, iXLen %vl) {
; CHECK-LABEL: vabdu_vv_mask_i16m8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl8re16.v v24, (a0)
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
+; CHECK-NEXT: vle16.v v24, (a0)
; CHECK-NEXT: vabdu.vv v8, v16, v24, v0.t
; CHECK-NEXT: ret
%res = call <vscale x 32 x i16> @llvm.riscv.vabdu.mask(
diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
index 111266d2e988c..8c3414bc27577 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
@@ -833,7 +833,7 @@ body: |
; CHECK-LABEL: name: vabs_v
; CHECK: liveins: $x8
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %x:vr = PseudoVABS_V_M1 $noreg, $noreg, -1 /* vl=VLMAX */, 5 /* e32 */, 0 /* tu, mu */
+ ; CHECK-NEXT: %x:vr = PseudoVABS_V_M1 $noreg, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1 /* vl */, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: $v8 = COPY %y
%x:vr = PseudoVABS_V_M1 $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */
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