[llvm] [DAG] isKnownNeverZero - add ISD::SRA/SRL DemandedElts handling and tests (PR #183577)

[Pranshu Goyal via llvm-commits]

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@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc  -mtriple=aarch64-linux-gnu < %s | FileCheck %s
+
+define i1 at srl_neverzero(<4 x i32> %v){
+; CHECK-LABEL: srl_neverzero:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    orr v0.4s, #128, lsl #24
+; CHECK-NEXT:    sshr v0.4s, v0.4s, #1
+; CHECK-NEXT:    fmov w8, s0
+; CHECK-NEXT:    cmp w8, #0
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
+  %forced_nonzero = or <4 x i32> %v, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
+  %shift = ashr <4 x i32> %forced_nonzero, <i32 1, i32 1, i32 1, i32 1>
+  %lane = extractelement <4 x i32> %shift, i32 0
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pranshoe wrote:

Could you make another issue for the scalarization one, I could look into it in the coming days?

https://github.com/llvm/llvm-project/pull/183577