[llvm] 4922ab9 - [RISCV] Relax codegen predicates for HINT-based instructions (#179872)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Mar 2 01:24:27 PST 2026
Author: Kito Cheng
Date: 2026-03-02T17:24:22+08:00
New Revision: 4922ab9915b0bc8cb6528583fe2da324d2d4bdeb
URL: https://github.com/llvm/llvm-project/commit/4922ab9915b0bc8cb6528583fe2da324d2d4bdeb
DIFF: https://github.com/llvm/llvm-project/commit/4922ab9915b0bc8cb6528583fe2da324d2d4bdeb.diff
LOG: [RISCV] Relax codegen predicates for HINT-based instructions (#179872)
Following the assembler/disassembler changes in #178609, this patch also
relaxes the codegen predicates for HINT-based instructions. Since these
instructions use encodings that are architecturally guaranteed not to
trap, the compiler can safely generate them regardless of extension
availability.
Changes:
- int_riscv_pause: Remove HasStdExtZihintpause predicate. The pause
intrinsic now generates the FENCE hint encoding unconditionally.
- NTL hints: Remove hasStdExtZihintntl() check in emitNTLHint().
Non-temporal locality hints are now emitted for all nontemporal memory
operations.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/prefetch.ll
llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 9740123d3859e..eb15227a72a83 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -273,18 +273,19 @@ bool RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst,
// instructions) auto-generated.
#include "RISCVGenMCPseudoLowering.inc"
-// If the target supports Zihintntl and the instruction has a nontemporal
-// MachineMemOperand, emit an NTLH hint instruction before it.
+// If the instruction has a nontemporal MachineMemOperand, emit an NTL hint
+// instruction before it. NTL hints are always safe to emit since they use
+// HINT encodings that are guaranteed not to trap
+// (riscv-non-isa/riscv-elf-psabi-doc#474).
void RISCVAsmPrinter::emitNTLHint(const MachineInstr *MI) {
- if (!STI->hasStdExtZihintntl())
+ if (!STI->getInstrInfo()->requiresNTLHint(*MI))
return;
- if (MI->memoperands_empty())
- return;
+ assert(!MI->memoperands_empty());
MachineMemOperand *MMO = *(MI->memoperands_begin());
- if (!MMO->isNonTemporal())
- return;
+
+ assert(MMO->isNonTemporal());
unsigned NontemporalMode = 0;
if (MMO->getFlags() & MONontemporalBit0)
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 38e39250f0b12..6387ab998d7b8 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3061,6 +3061,11 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
return;
}
case ISD::PREFETCH:
+ // MIPS's prefetch instruction already encodes the hint within the
+ // instruction itself, so no extra NTL hint is needed.
+ if (Subtarget->hasVendorXMIPSCBOP())
+ break;
+
unsigned Locality = Node->getConstantOperandVal(3);
if (Locality > 2)
break;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index e4624064e4c37..fa388a3ec64d8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1994,16 +1994,13 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
*MF.getTarget().getMCAsmInfo());
}
- if (!MI.memoperands_empty()) {
- MachineMemOperand *MMO = *(MI.memoperands_begin());
- if (STI.hasStdExtZihintntl() && MMO->isNonTemporal()) {
- if (STI.hasStdExtZca()) {
- if (isCompressibleInst(MI, STI))
- return 4; // c.ntl.all + c.load/c.store
- return 6; // c.ntl.all + load/store
- }
- return 8; // ntl.all + load/store
+ if (requiresNTLHint(MI)) {
+ if (STI.hasStdExtZca()) {
+ if (isCompressibleInst(MI, STI))
+ return 4; // c.ntl.all + c.load/c.store
+ return 6; // c.ntl.all + load/store
}
+ return 8; // ntl.all + load/store
}
if (Opcode == TargetOpcode::BUNDLE)
@@ -5326,3 +5323,14 @@ bool RISCVInstrInfo::isVRegCopy(const MachineInstr *MI, unsigned LMul) const {
RISCVVType::decodeVLMUL(RISCVRI::getLMul(RC->TSFlags));
return (!RCFractional && LMul == RCLMul) || (RCFractional && LMul == 1);
}
+
+bool RISCVInstrInfo::requiresNTLHint(const MachineInstr &MI) const {
+ if (MI.memoperands_empty())
+ return false;
+
+ MachineMemOperand *MMO = *(MI.memoperands_begin());
+ if (!MMO->isNonTemporal())
+ return false;
+
+ return true;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index cfe2e5c474fbd..15d0e4d3e7d52 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -330,6 +330,9 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
/// or any kind of vector registers when \p LMul is zero.
bool isVRegCopy(const MachineInstr *MI, unsigned LMul = 0) const;
+ /// Return true if the instruction requires an NTL hint to be emitted.
+ bool requiresNTLHint(const MachineInstr &MI) const;
+
/// Return true if pairing the given load or store may be paired with another.
static bool isPairableLdStInstOpc(unsigned Opc);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index ba5a468916125..a5c0e016aaa83 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -2316,8 +2316,8 @@ def : Pat<(i64 (add GPR:$rs1, negImm:$rs2)), (SUB GPR:$rs1, negImm:$rs2)>;
// Zihintpause
//===----------------------------------------------------------------------===//
-// Zihintpause
-let Predicates = [HasStdExtZihintpause] in
+// int_riscv_pause is always available since pause is a HINT encoding that is
+// guaranteed not to trap (riscv-non-isa/riscv-elf-psabi-doc#474).
def : Pat<(int_riscv_pause), (FENCE 0x1, 0x0)>;
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/CodeGen/RISCV/prefetch.ll b/llvm/test/CodeGen/RISCV/prefetch.ll
index ba33ed7ac1a59..dbce4e74954ca 100644
--- a/llvm/test/CodeGen/RISCV/prefetch.ll
+++ b/llvm/test/CodeGen/RISCV/prefetch.ll
@@ -1,696 +1,347 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64I %s
-; RUN: llc -mtriple=riscv32 -mattr=+zicbop -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV32ZICBOP %s
-; RUN: llc -mtriple=riscv64 -mattr=+zicbop -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64ZICBOP %s
-; RUN: llc -mtriple=riscv64 -mattr=+zicbop,+zihintntl -verify-machineinstrs < %s \
-; RUN: | FileCheck -check-prefix=RV64ZICBOPZIHINTNTL %s
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck -check-prefix=NOZICBOP %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck -check-prefix=NOZICBOP %s
+; RUN: llc -mtriple=riscv32 -mattr=+zicbop -verify-machineinstrs < %s | FileCheck -check-prefix=ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+zicbop -verify-machineinstrs < %s | FileCheck -check-prefix=ZICBOP %s
+; RUN: llc -mtriple=riscv64 -mattr=+zicbop,+zihintntl -verify-machineinstrs < %s | FileCheck -check-prefix=ZICBOP %s
define void @test_prefetch_read_locality_0(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_read_locality_0:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_read_locality_0:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_read_locality_0:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_read_locality_0:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_read_locality_0:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_read_locality_0:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_read_locality_0:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_write_locality_0(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_write_locality_0:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_write_locality_0:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_write_locality_0:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.w 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_write_locality_0:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.w 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_write_locality_0:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.w 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_write_locality_0:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_write_locality_0:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.w 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 1, i32 0, i32 1)
ret void
}
define void @test_prefetch_instruction_locality_0(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_instruction_locality_0:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_instruction_locality_0:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_instruction_locality_0:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.i 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_instruction_locality_0:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.i 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_instruction_locality_0:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.i 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_instruction_locality_0:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_instruction_locality_0:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.i 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 0, i32 0, i32 0)
ret void
}
define void @test_prefetch_read_locality_1(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_read_locality_1:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_read_locality_1:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_read_locality_1:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_read_locality_1:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_read_locality_1:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.pall
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_read_locality_1:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_read_locality_1:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.pall
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 0, i32 1, i32 1)
ret void
}
define void @test_prefetch_write_locality_1(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_write_locality_1:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_write_locality_1:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_write_locality_1:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.w 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_write_locality_1:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.w 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_write_locality_1:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.pall
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.w 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_write_locality_1:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_write_locality_1:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.pall
+; ZICBOP-NEXT: prefetch.w 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 1, i32 1, i32 1)
ret void
}
define void @test_prefetch_instruction_locality_1(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_instruction_locality_1:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_instruction_locality_1:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_instruction_locality_1:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.i 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_instruction_locality_1:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.i 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_instruction_locality_1:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.pall
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.i 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_instruction_locality_1:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_instruction_locality_1:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.pall
+; ZICBOP-NEXT: prefetch.i 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 0, i32 1, i32 0)
ret void
}
define void @test_prefetch_read_locality_2(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_read_locality_2:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_read_locality_2:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_read_locality_2:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_read_locality_2:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_read_locality_2:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.p1
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_read_locality_2:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_read_locality_2:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.p1
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 0, i32 2, i32 1)
ret void
}
define void @test_prefetch_write_locality_2(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_write_locality_2:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_write_locality_2:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_write_locality_2:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.w 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_write_locality_2:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.w 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_write_locality_2:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.p1
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.w 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_write_locality_2:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_write_locality_2:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.p1
+; ZICBOP-NEXT: prefetch.w 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 1, i32 2, i32 1)
ret void
}
define void @test_prefetch_instruction_locality_2(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_instruction_locality_2:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_instruction_locality_2:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_instruction_locality_2:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.i 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_instruction_locality_2:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.i 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_instruction_locality_2:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.p1
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.i 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_instruction_locality_2:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_instruction_locality_2:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.p1
+; ZICBOP-NEXT: prefetch.i 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 0, i32 2, i32 0)
ret void
}
define void @test_prefetch_read_locality_3(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_read_locality_3:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_read_locality_3:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_read_locality_3:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_read_locality_3:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_read_locality_3:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_read_locality_3:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_read_locality_3:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 0, i32 3, i32 1)
ret void
}
define void @test_prefetch_write_locality_3(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_write_locality_3:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_write_locality_3:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_write_locality_3:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.w 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_write_locality_3:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.w 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_write_locality_3:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.w 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_write_locality_3:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_write_locality_3:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: prefetch.w 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 1, i32 3, i32 1)
ret void
}
define void @test_prefetch_instruction_locality_3(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_instruction_locality_3:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_instruction_locality_3:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_instruction_locality_3:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.i 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_instruction_locality_3:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.i 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_instruction_locality_3:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.i 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_instruction_locality_3:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_instruction_locality_3:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: prefetch.i 0(a0)
+; ZICBOP-NEXT: ret
call void @llvm.prefetch(ptr %a, i32 0, i32 3, i32 0)
ret void
}
define void @test_prefetch_offsetable_0(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_0:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_0:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_0:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.r 2016(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_0:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.r 2016(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_0:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 2016(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_0:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_offsetable_0:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 2016(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 2016
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_offsetable_1(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_1:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_1:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_1:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_1:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_1:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_1:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_offsetable_1:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -2048(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 -2048
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_offsetable_2(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_2:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_2:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_2:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.r 32(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_2:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.r 32(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_2:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 32(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_2:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_offsetable_2:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 32(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 32
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_offsetable_3(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_3:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_3:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_3:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: prefetch.r -32(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_3:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: prefetch.r -32(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_3:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -32(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_3:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_offsetable_3:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -32(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 -32
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_offsetable_4(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_4:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_4:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_4:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi a0, a0, 32
-; RV32ZICBOP-NEXT: prefetch.r 2016(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_4:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi a0, a0, 32
-; RV64ZICBOP-NEXT: prefetch.r 2016(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_4:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 32
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 2016(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_4:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_offsetable_4:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi a0, a0, 32
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 2016(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 2048
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_offsetable_5(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_5:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_5:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_5:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi a0, a0, -1
-; RV32ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_5:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi a0, a0, -1
-; RV64ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_5:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, -1
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_5:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_offsetable_5:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi a0, a0, -1
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -2048(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 -2049
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_offsetable_6(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_6:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_6:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_6:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi a0, a0, 16
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_6:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi a0, a0, 16
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_6:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 16
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_6:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_offsetable_6:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi a0, a0, 16
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 16
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_offsetable_7(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_7:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_7:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_7:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi a0, a0, -16
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_7:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi a0, a0, -16
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_7:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, -16
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_7:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_offsetable_7:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi a0, a0, -16
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 -16
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_offsetable_9(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_9:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_9:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_9:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a1, 1
-; RV32ZICBOP-NEXT: add a0, a0, a1
-; RV32ZICBOP-NEXT: prefetch.r 64(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_9:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a1, 1
-; RV64ZICBOP-NEXT: add a0, a0, a1
-; RV64ZICBOP-NEXT: prefetch.r 64(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_9:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a1, 1
-; RV64ZICBOPZIHINTNTL-NEXT: add a0, a0, a1
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 64(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_9:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_offsetable_9:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a1, 1
+; ZICBOP-NEXT: add a0, a0, a1
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 64(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 4160
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_offsetable_8(ptr %a) nounwind {
-; RV32I-LABEL: test_prefetch_offsetable_8:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_offsetable_8:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_offsetable_8:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a1, 1048575
-; RV32ZICBOP-NEXT: add a0, a0, a1
-; RV32ZICBOP-NEXT: prefetch.r -64(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_offsetable_8:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a1, 1048575
-; RV64ZICBOP-NEXT: add a0, a0, a1
-; RV64ZICBOP-NEXT: prefetch.r -64(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_offsetable_8:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a1, 1048575
-; RV64ZICBOPZIHINTNTL-NEXT: add a0, a0, a1
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -64(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_offsetable_8:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_offsetable_8:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a1, 1048575
+; ZICBOP-NEXT: add a0, a0, a1
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -64(a0)
+; ZICBOP-NEXT: ret
%addr = getelementptr i8, ptr %a, i64 -4160
call void @llvm.prefetch(ptr %addr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_frameindex_0() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_0:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -512
-; RV32I-NEXT: addi sp, sp, 512
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_0:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -512
-; RV64I-NEXT: addi sp, sp, 512
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_0:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi sp, sp, -512
-; RV32ZICBOP-NEXT: prefetch.r 0(sp)
-; RV32ZICBOP-NEXT: addi sp, sp, 512
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_0:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi sp, sp, -512
-; RV64ZICBOP-NEXT: prefetch.r 0(sp)
-; RV64ZICBOP-NEXT: addi sp, sp, 512
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_0:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(sp)
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_0:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: addi sp, sp, -512
+; NOZICBOP-NEXT: addi sp, sp, 512
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_frameindex_0:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi sp, sp, -512
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(sp)
+; ZICBOP-NEXT: addi sp, sp, 512
+; ZICBOP-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 0
@@ -699,62 +350,28 @@ define void @test_prefetch_frameindex_0() nounwind {
}
define void @test_prefetch_frameindex_1() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_1:
-; RV32I: # %bb.0:
-; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: addi a0, a0, 16
-; RV32I-NEXT: sub sp, sp, a0
-; RV32I-NEXT: lui a0, 1
-; RV32I-NEXT: addi a0, a0, 16
-; RV32I-NEXT: add sp, sp, a0
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_1:
-; RV64I: # %bb.0:
-; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: addi a0, a0, 16
-; RV64I-NEXT: sub sp, sp, a0
-; RV64I-NEXT: lui a0, 1
-; RV64I-NEXT: addi a0, a0, 16
-; RV64I-NEXT: add sp, sp, a0
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_1:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, 1
-; RV32ZICBOP-NEXT: addi a0, a0, 16
-; RV32ZICBOP-NEXT: sub sp, sp, a0
-; RV32ZICBOP-NEXT: addi a0, sp, 16
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: lui a0, 1
-; RV32ZICBOP-NEXT: addi a0, a0, 16
-; RV32ZICBOP-NEXT: add sp, sp, a0
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_1:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, 1
-; RV64ZICBOP-NEXT: addi a0, a0, 16
-; RV64ZICBOP-NEXT: sub sp, sp, a0
-; RV64ZICBOP-NEXT: addi a0, sp, 16
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: lui a0, 1
-; RV64ZICBOP-NEXT: addi a0, a0, 16
-; RV64ZICBOP-NEXT: add sp, sp, a0
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_1:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 16
-; RV64ZICBOPZIHINTNTL-NEXT: sub sp, sp, a0
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, sp, 16
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 16
-; RV64ZICBOPZIHINTNTL-NEXT: add sp, sp, a0
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_1:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: lui a0, 1
+; NOZICBOP-NEXT: addi a0, a0, 16
+; NOZICBOP-NEXT: sub sp, sp, a0
+; NOZICBOP-NEXT: lui a0, 1
+; NOZICBOP-NEXT: addi a0, a0, 16
+; NOZICBOP-NEXT: add sp, sp, a0
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_frameindex_1:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, 1
+; ZICBOP-NEXT: addi a0, a0, 16
+; ZICBOP-NEXT: sub sp, sp, a0
+; ZICBOP-NEXT: addi a0, sp, 16
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: lui a0, 1
+; ZICBOP-NEXT: addi a0, a0, 16
+; ZICBOP-NEXT: add sp, sp, a0
+; ZICBOP-NEXT: ret
%data = alloca [1024 x i32], align 4
%ptr = bitcast ptr %data to ptr
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
@@ -762,42 +379,20 @@ define void @test_prefetch_frameindex_1() nounwind {
}
define void @test_prefetch_frameindex_2() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_2:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -512
-; RV32I-NEXT: addi sp, sp, 512
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_2:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -512
-; RV64I-NEXT: addi sp, sp, 512
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_2:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi sp, sp, -512
-; RV32ZICBOP-NEXT: addi a0, sp, 16
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: addi sp, sp, 512
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_2:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi sp, sp, -512
-; RV64ZICBOP-NEXT: addi a0, sp, 16
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: addi sp, sp, 512
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_2:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, sp, 16
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_2:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: addi sp, sp, -512
+; NOZICBOP-NEXT: addi sp, sp, 512
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_frameindex_2:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi sp, sp, -512
+; ZICBOP-NEXT: addi a0, sp, 16
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: addi sp, sp, 512
+; ZICBOP-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 4
@@ -806,42 +401,20 @@ define void @test_prefetch_frameindex_2() nounwind {
}
define void @test_prefetch_frameindex_3() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_3:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -512
-; RV32I-NEXT: addi sp, sp, 512
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_3:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -512
-; RV64I-NEXT: addi sp, sp, 512
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_3:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi sp, sp, -512
-; RV32ZICBOP-NEXT: addi a0, sp, -16
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: addi sp, sp, 512
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_3:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi sp, sp, -512
-; RV64ZICBOP-NEXT: addi a0, sp, -16
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: addi sp, sp, 512
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_3:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, sp, -16
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_3:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: addi sp, sp, -512
+; NOZICBOP-NEXT: addi sp, sp, 512
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_frameindex_3:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi sp, sp, -512
+; ZICBOP-NEXT: addi a0, sp, -16
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: addi sp, sp, 512
+; ZICBOP-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 -4
@@ -850,39 +423,19 @@ define void @test_prefetch_frameindex_3() nounwind {
}
define void @test_prefetch_frameindex_4() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_4:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -512
-; RV32I-NEXT: addi sp, sp, 512
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_4:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -512
-; RV64I-NEXT: addi sp, sp, 512
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_4:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi sp, sp, -512
-; RV32ZICBOP-NEXT: prefetch.r 32(sp)
-; RV32ZICBOP-NEXT: addi sp, sp, 512
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_4:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi sp, sp, -512
-; RV64ZICBOP-NEXT: prefetch.r 32(sp)
-; RV64ZICBOP-NEXT: addi sp, sp, 512
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_4:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 32(sp)
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_4:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: addi sp, sp, -512
+; NOZICBOP-NEXT: addi sp, sp, 512
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_frameindex_4:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi sp, sp, -512
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 32(sp)
+; ZICBOP-NEXT: addi sp, sp, 512
+; ZICBOP-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 8
@@ -891,39 +444,19 @@ define void @test_prefetch_frameindex_4() nounwind {
}
define void @test_prefetch_frameindex_5() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_5:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -512
-; RV32I-NEXT: addi sp, sp, 512
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_5:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -512
-; RV64I-NEXT: addi sp, sp, 512
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_5:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi sp, sp, -512
-; RV32ZICBOP-NEXT: prefetch.r -32(sp)
-; RV32ZICBOP-NEXT: addi sp, sp, 512
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_5:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi sp, sp, -512
-; RV64ZICBOP-NEXT: prefetch.r -32(sp)
-; RV64ZICBOP-NEXT: addi sp, sp, 512
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_5:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -32(sp)
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_5:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: addi sp, sp, -512
+; NOZICBOP-NEXT: addi sp, sp, 512
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_frameindex_5:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi sp, sp, -512
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -32(sp)
+; ZICBOP-NEXT: addi sp, sp, 512
+; ZICBOP-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 -8
@@ -932,39 +465,19 @@ define void @test_prefetch_frameindex_5() nounwind {
}
define void @test_prefetch_frameindex_6() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_6:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -512
-; RV32I-NEXT: addi sp, sp, 512
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_6:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -512
-; RV64I-NEXT: addi sp, sp, 512
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_6:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi sp, sp, -512
-; RV32ZICBOP-NEXT: prefetch.r 2016(sp)
-; RV32ZICBOP-NEXT: addi sp, sp, 512
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_6:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi sp, sp, -512
-; RV64ZICBOP-NEXT: prefetch.r 2016(sp)
-; RV64ZICBOP-NEXT: addi sp, sp, 512
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_6:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 2016(sp)
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_6:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: addi sp, sp, -512
+; NOZICBOP-NEXT: addi sp, sp, 512
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_frameindex_6:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi sp, sp, -512
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 2016(sp)
+; ZICBOP-NEXT: addi sp, sp, 512
+; ZICBOP-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 504
@@ -973,39 +486,19 @@ define void @test_prefetch_frameindex_6() nounwind {
}
define void @test_prefetch_frameindex_7() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_7:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -512
-; RV32I-NEXT: addi sp, sp, 512
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_7:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -512
-; RV64I-NEXT: addi sp, sp, 512
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_7:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi sp, sp, -512
-; RV32ZICBOP-NEXT: prefetch.r -2048(sp)
-; RV32ZICBOP-NEXT: addi sp, sp, 512
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_7:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi sp, sp, -512
-; RV64ZICBOP-NEXT: prefetch.r -2048(sp)
-; RV64ZICBOP-NEXT: addi sp, sp, 512
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_7:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -2048(sp)
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_7:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: addi sp, sp, -512
+; NOZICBOP-NEXT: addi sp, sp, 512
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_frameindex_7:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi sp, sp, -512
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -2048(sp)
+; ZICBOP-NEXT: addi sp, sp, 512
+; ZICBOP-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 -512
@@ -1014,42 +507,20 @@ define void @test_prefetch_frameindex_7() nounwind {
}
define void @test_prefetch_frameindex_8() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_8:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -512
-; RV32I-NEXT: addi sp, sp, 512
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_8:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -512
-; RV64I-NEXT: addi sp, sp, 512
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_8:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi sp, sp, -512
-; RV32ZICBOP-NEXT: addi a0, sp, 2020
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: addi sp, sp, 512
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_8:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi sp, sp, -512
-; RV64ZICBOP-NEXT: addi a0, sp, 2020
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: addi sp, sp, 512
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_8:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, sp, 2020
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_8:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: addi sp, sp, -512
+; NOZICBOP-NEXT: addi sp, sp, 512
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_frameindex_8:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi sp, sp, -512
+; ZICBOP-NEXT: addi a0, sp, 2020
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: addi sp, sp, 512
+; ZICBOP-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 505
@@ -1058,45 +529,21 @@ define void @test_prefetch_frameindex_8() nounwind {
}
define void @test_prefetch_frameindex_9() nounwind {
-; RV32I-LABEL: test_prefetch_frameindex_9:
-; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -512
-; RV32I-NEXT: addi sp, sp, 512
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_frameindex_9:
-; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -512
-; RV64I-NEXT: addi sp, sp, 512
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_frameindex_9:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: addi sp, sp, -512
-; RV32ZICBOP-NEXT: mv a0, sp
-; RV32ZICBOP-NEXT: addi a0, a0, -4
-; RV32ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV32ZICBOP-NEXT: addi sp, sp, 512
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_frameindex_9:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: addi sp, sp, -512
-; RV64ZICBOP-NEXT: mv a0, sp
-; RV64ZICBOP-NEXT: addi a0, a0, -4
-; RV64ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOP-NEXT: addi sp, sp, 512
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_frameindex_9:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, -512
-; RV64ZICBOPZIHINTNTL-NEXT: mv a0, sp
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, -4
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: addi sp, sp, 512
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_frameindex_9:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: addi sp, sp, -512
+; NOZICBOP-NEXT: addi sp, sp, 512
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_frameindex_9:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: addi sp, sp, -512
+; ZICBOP-NEXT: mv a0, sp
+; ZICBOP-NEXT: addi a0, a0, -4
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -2048(a0)
+; ZICBOP-NEXT: addi sp, sp, 512
+; ZICBOP-NEXT: ret
%data = alloca [128 x i32], align 4
%base = bitcast ptr %data to ptr
%ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 -513
@@ -1105,134 +552,66 @@ define void @test_prefetch_frameindex_9() nounwind {
}
define void @test_prefetch_constant_address_0() nounwind {
-; RV32I-LABEL: test_prefetch_constant_address_0:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_constant_address_0:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_constant_address_0:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, 1
-; RV32ZICBOP-NEXT: prefetch.r 32(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_constant_address_0:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, 1
-; RV64ZICBOP-NEXT: prefetch.r 32(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_constant_address_0:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 32(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_constant_address_0:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_constant_address_0:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, 1
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 32(a0)
+; ZICBOP-NEXT: ret
%ptr = inttoptr i64 4128 to ptr
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_constant_address_1() nounwind {
-; RV32I-LABEL: test_prefetch_constant_address_1:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_constant_address_1:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_constant_address_1:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, 1
-; RV32ZICBOP-NEXT: addi a0, a0, 31
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_constant_address_1:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, 1
-; RV64ZICBOP-NEXT: addi a0, a0, 31
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_constant_address_1:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 31
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_constant_address_1:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_constant_address_1:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, 1
+; ZICBOP-NEXT: addi a0, a0, 31
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
%ptr = inttoptr i64 4127 to ptr
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_constant_address_2() nounwind {
-; RV32I-LABEL: test_prefetch_constant_address_2:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_constant_address_2:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_constant_address_2:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, 1048561
-; RV32ZICBOP-NEXT: prefetch.r 32(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_constant_address_2:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, 1048561
-; RV64ZICBOP-NEXT: prefetch.r 32(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_constant_address_2:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1048561
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 32(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_constant_address_2:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_constant_address_2:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, 1048561
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 32(a0)
+; ZICBOP-NEXT: ret
%ptr = inttoptr i64 18446744073709490208 to ptr
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_constant_address_3() nounwind {
-; RV32I-LABEL: test_prefetch_constant_address_3:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_constant_address_3:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_constant_address_3:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, 1048561
-; RV32ZICBOP-NEXT: addi a0, a0, 31
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_constant_address_3:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, 1048561
-; RV64ZICBOP-NEXT: addi a0, a0, 31
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_constant_address_3:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, 1048561
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, 31
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_constant_address_3:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_constant_address_3:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, 1048561
+; ZICBOP-NEXT: addi a0, a0, 31
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
%ptr = inttoptr i64 18446744073709490207 to ptr
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
@@ -1241,315 +620,153 @@ define void @test_prefetch_constant_address_3() nounwind {
@g = external global [1024 x i32], align 4
define void @test_prefetch_global_0() nounwind {
-; RV32I-LABEL: test_prefetch_global_0:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_global_0:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_global_0:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, %hi(g)
-; RV32ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_global_0:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, %hi(g)
-; RV64ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_0:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g)
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_global_0:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_global_0:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, %hi(g)
+; ZICBOP-NEXT: addi a0, a0, %lo(g)
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
%ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 0
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_global_1() nounwind {
-; RV32I-LABEL: test_prefetch_global_1:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_global_1:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_global_1:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, %hi(g+16)
-; RV32ZICBOP-NEXT: addi a0, a0, %lo(g+16)
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_global_1:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, %hi(g+16)
-; RV64ZICBOP-NEXT: addi a0, a0, %lo(g+16)
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_1:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g+16)
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g+16)
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_global_1:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_global_1:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, %hi(g+16)
+; ZICBOP-NEXT: addi a0, a0, %lo(g+16)
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
%ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 4
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_global_2() nounwind {
-; RV32I-LABEL: test_prefetch_global_2:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_global_2:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_global_2:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, %hi(g-16)
-; RV32ZICBOP-NEXT: addi a0, a0, %lo(g-16)
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_global_2:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, %hi(g-16)
-; RV64ZICBOP-NEXT: addi a0, a0, %lo(g-16)
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_2:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g-16)
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g-16)
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_global_2:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_global_2:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, %hi(g-16)
+; ZICBOP-NEXT: addi a0, a0, %lo(g-16)
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
%ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 -4
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_global_3() nounwind {
-; RV32I-LABEL: test_prefetch_global_3:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_global_3:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_global_3:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, %hi(g)
-; RV32ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV32ZICBOP-NEXT: prefetch.r 32(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_global_3:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, %hi(g)
-; RV64ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOP-NEXT: prefetch.r 32(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_3:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g)
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 32(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_global_3:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_global_3:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, %hi(g)
+; ZICBOP-NEXT: addi a0, a0, %lo(g)
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 32(a0)
+; ZICBOP-NEXT: ret
%ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 8
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_global_4() nounwind {
-; RV32I-LABEL: test_prefetch_global_4:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_global_4:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_global_4:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, %hi(g)
-; RV32ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV32ZICBOP-NEXT: prefetch.r -32(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_global_4:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, %hi(g)
-; RV64ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOP-NEXT: prefetch.r -32(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_4:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g)
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -32(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_global_4:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_global_4:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, %hi(g)
+; ZICBOP-NEXT: addi a0, a0, %lo(g)
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -32(a0)
+; ZICBOP-NEXT: ret
%ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 -8
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_global_5() nounwind {
-; RV32I-LABEL: test_prefetch_global_5:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_global_5:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_global_5:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, %hi(g)
-; RV32ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV32ZICBOP-NEXT: prefetch.r 2016(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_global_5:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, %hi(g)
-; RV64ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOP-NEXT: prefetch.r 2016(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_5:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g)
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 2016(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_global_5:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_global_5:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, %hi(g)
+; ZICBOP-NEXT: addi a0, a0, %lo(g)
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 2016(a0)
+; ZICBOP-NEXT: ret
%ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 504
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_global_6() nounwind {
-; RV32I-LABEL: test_prefetch_global_6:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_global_6:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_global_6:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, %hi(g)
-; RV32ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV32ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_global_6:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, %hi(g)
-; RV64ZICBOP-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_6:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g)
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g)
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_global_6:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_global_6:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, %hi(g)
+; ZICBOP-NEXT: addi a0, a0, %lo(g)
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -2048(a0)
+; ZICBOP-NEXT: ret
%ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 -512
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_global_7() nounwind {
-; RV32I-LABEL: test_prefetch_global_7:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_global_7:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_global_7:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, %hi(g+2020)
-; RV32ZICBOP-NEXT: addi a0, a0, %lo(g+2020)
-; RV32ZICBOP-NEXT: prefetch.r 0(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_global_7:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, %hi(g+2020)
-; RV64ZICBOP-NEXT: addi a0, a0, %lo(g+2020)
-; RV64ZICBOP-NEXT: prefetch.r 0(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_7:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g+2020)
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g+2020)
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r 0(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_global_7:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_global_7:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, %hi(g+2020)
+; ZICBOP-NEXT: addi a0, a0, %lo(g+2020)
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r 0(a0)
+; ZICBOP-NEXT: ret
%ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 505
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
}
define void @test_prefetch_global_8() nounwind {
-; RV32I-LABEL: test_prefetch_global_8:
-; RV32I: # %bb.0:
-; RV32I-NEXT: ret
-;
-; RV64I-LABEL: test_prefetch_global_8:
-; RV64I: # %bb.0:
-; RV64I-NEXT: ret
-;
-; RV32ZICBOP-LABEL: test_prefetch_global_8:
-; RV32ZICBOP: # %bb.0:
-; RV32ZICBOP-NEXT: lui a0, %hi(g-4)
-; RV32ZICBOP-NEXT: addi a0, a0, %lo(g-4)
-; RV32ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV32ZICBOP-NEXT: ret
-;
-; RV64ZICBOP-LABEL: test_prefetch_global_8:
-; RV64ZICBOP: # %bb.0:
-; RV64ZICBOP-NEXT: lui a0, %hi(g-4)
-; RV64ZICBOP-NEXT: addi a0, a0, %lo(g-4)
-; RV64ZICBOP-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOP-NEXT: ret
-;
-; RV64ZICBOPZIHINTNTL-LABEL: test_prefetch_global_8:
-; RV64ZICBOPZIHINTNTL: # %bb.0:
-; RV64ZICBOPZIHINTNTL-NEXT: lui a0, %hi(g-4)
-; RV64ZICBOPZIHINTNTL-NEXT: addi a0, a0, %lo(g-4)
-; RV64ZICBOPZIHINTNTL-NEXT: ntl.all
-; RV64ZICBOPZIHINTNTL-NEXT: prefetch.r -2048(a0)
-; RV64ZICBOPZIHINTNTL-NEXT: ret
+; NOZICBOP-LABEL: test_prefetch_global_8:
+; NOZICBOP: # %bb.0:
+; NOZICBOP-NEXT: ret
+;
+; ZICBOP-LABEL: test_prefetch_global_8:
+; ZICBOP: # %bb.0:
+; ZICBOP-NEXT: lui a0, %hi(g-4)
+; ZICBOP-NEXT: addi a0, a0, %lo(g-4)
+; ZICBOP-NEXT: ntl.all
+; ZICBOP-NEXT: prefetch.r -2048(a0)
+; ZICBOP-NEXT: ret
%ptr = getelementptr [1024 x i32], ptr @g, i32 0, i32 -513
call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
ret void
diff --git a/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll b/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
index 46e06875efe7a..2df7983eb6ae7 100644
--- a/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
+++ b/llvm/test/CodeGen/RISCV/riscv-zihintpause.ll
@@ -1,12 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+zihintpause -verify-machineinstrs < %s \
-; RUN: | FileCheck %s -check-prefix=RVPAUSE
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+zihintpause -verify-machineinstrs < %s | FileCheck %s
+
+; The pause intrinsic is always available since pause is a HINT encoding.
define void @test_pause() {
-; RVPAUSE-LABEL: test_pause:
-; RVPAUSE: # %bb.0:
-; RVPAUSE-NEXT: pause
-; RVPAUSE-NEXT: ret
+; CHECK-LABEL: test_pause:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pause
+; CHECK-NEXT: ret
call void @llvm.riscv.pause()
ret void
}
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