[llvm] [AMDGPU] AMDGPUIGroupLP: Avoid repeating reachability checks in greedy algorithm (PR #182463)

[Frederik Harwath via llvm-commits]

================
@@ -729,21 +733,38 @@ void PipelineSolver::greedyFind(
       LLVM_DEBUG(dbgs() << "SGID # " << CandSGID << " has conflicting rule\n");
       continue;
     }
-    TempCost = addEdges(SyncPipeline, CurrSU.first, CandSGID, AddedEdges);
+
+    std::list<std::pair<SUnit *, SUnit *>> TempEdges;
+    TempCost = addEdges(SyncPipeline, CurrSU.first, CandSGID, TempEdges);
     LLVM_DEBUG(dbgs() << "Cost of Group " << TempCost << "\n");
+
     if (TempCost < BestNodeCost || BestNodeCost == -1) {
+      BestEdges = TempEdges;
       BestGroup = Match;
       BestNodeCost = TempCost;
       BestGroupID = CandSGID;
+
+      if (BestNodeCost == 0)
+        break;
+
+      removeEdges(BestEdges);
     }
-    removeEdges(AddedEdges);
-    if (BestNodeCost == 0)
-      break;
+
+    removeEdges(TempEdges);
   }
 
   if (BestGroupID != -1) {
     BestGroup->add(*CurrSU.first);
-    addEdges(SyncPipeline, CurrSU.first, BestGroupID, AddedEdges);
+    if (AddedEdges.empty())
+      AddedEdges = BestEdges;
+    else
----------------
frederik-h wrote:

Yes, `llvm/test/CodeGen/AMDGPU/sched-group-barrier-pipeline-solver.mir` does. A - perhaps somewhat degenerated but valid - reduced version:
```
---
name:            sched_group_barrier_2_VMEM_10_ALU_5_MFMA_2_VMEM_WRITE
tracksRegLiveness: true

body:             |
  bb.0:
    %17:sreg_64_xexec_xnull = IMPLICIT_DEF
    %18:vgpr_32 = IMPLICIT_DEF
    GLOBAL_STORE_DWORD_SADDR undef %18, undef %18, undef %17, 512, 0, implicit $exec
    SCHED_GROUP_BARRIER 16, 2, 0
    S_ENDPGM 0
...
```

https://github.com/llvm/llvm-project/pull/182463