[llvm] [AArch64] Fix performZExtUZPCombine() DAG combine (PR #183765)

[Gaëtan Bossu via llvm-commits]

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@@ -24348,6 +24357,9 @@ static SDValue performZExtUZPCombine(SDNode *N, SelectionDAG &DAG) {
     if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
       ExtOffset = Op.getConstantOperandVal(1);
       Op = Op.getOperand(0);
+      // Avoid NVCAST from a scalable vector to a fixed-size one.
+      if (Op.getValueType().isScalableVector())
+        return SDValue();
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gbossu wrote:

I think that in theory, this is a case that could happen, but I haven't managed to write a test because SDAG just does so many things in one pass. I'll try a bit more and report back :)

https://github.com/llvm/llvm-project/pull/183765