[llvm] Improved ISD::SRL handling in isKnownToBeAPowerOfTwo (PR #182562)

[Simon Pilgrim via llvm-commits]

================
@@ -4723,12 +4723,12 @@ bool SelectionDAG::isKnownToBeAPowerOfTwo(SDValue Val,
   case ISD::SRL: {
     // A logical right-shift of a constant sign-bit will have exactly
     // one bit set.
-    auto *C = isConstOrConstSplat(Val.getOperand(0));
+    auto *C = isConstOrConstSplat(Val.getOperand(0), DemandedElts);
     if (C && C->getAPIntValue().isSignMask())
       return true;
-    return isKnownToBeAPowerOfTwo(Val.getOperand(0), /*OrZero=*/false,
-                                  Depth + 1) &&
-           isKnownNeverZero(Val, Depth);
+    return (OrZero || isKnownNeverZero(Val, Depth)) &&
----------------
RKSimon wrote:

#182679 will shortly allow us to change this to:
```suggestion
    return (OrZero || isKnownNeverZero(Val, DemandedElts, Depth)) &&
```

https://github.com/llvm/llvm-project/pull/182562