[llvm] [PowerPC] Custom Lower ABDU using branchless carry (PR #182704)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 21 15:28:51 PST 2026
https://github.com/SiliconA-Z updated https://github.com/llvm/llvm-project/pull/182704
>From e454c140d3bc7f477ce351926f411afec9cb2dad Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sat, 21 Feb 2026 16:44:56 -0500
Subject: [PATCH 1/2] Pre-commit tests
---
llvm/test/CodeGen/PowerPC/abdu-neg.ll | 931 ++++++++++++++++++++++++
llvm/test/CodeGen/PowerPC/abdu.ll | 982 ++++++++++++++++++++++++++
2 files changed, 1913 insertions(+)
create mode 100644 llvm/test/CodeGen/PowerPC/abdu-neg.ll
create mode 100644 llvm/test/CodeGen/PowerPC/abdu.ll
diff --git a/llvm/test/CodeGen/PowerPC/abdu-neg.ll b/llvm/test/CodeGen/PowerPC/abdu-neg.ll
new file mode 100644
index 0000000000000..bfd656bd0f56f
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/abdu-neg.ll
@@ -0,0 +1,931 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc-unknown-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,PPC32
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,PPC64
+
+;
+; trunc(nabs(sub(zext(a),zext(b)))) -> nabdu(a,b)
+;
+
+define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
+; PPC32-LABEL: abd_ext_i8:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 24
+; PPC32-NEXT: clrlwi 4, 4, 24
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i8:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 56
+; PPC64-NEXT: clrldi 4, 4, 56
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+ %aext = zext i8 %a to i64
+ %bext = zext i8 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %nabs = sub i64 0, %abs
+ %trunc = trunc i64 %nabs to i8
+ ret i8 %trunc
+}
+
+define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
+; PPC32-LABEL: abd_ext_i8_i16:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: clrlwi 3, 3, 24
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i8_i16:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 56
+; PPC64-NEXT: clrldi 4, 4, 48
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+ %aext = zext i8 %a to i64
+ %bext = zext i16 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %nabs = sub i64 0, %abs
+ %trunc = trunc i64 %nabs to i8
+ ret i8 %trunc
+}
+
+define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
+; PPC32-LABEL: abd_ext_i8_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 24
+; PPC32-NEXT: clrlwi 4, 4, 24
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i8_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 56
+; PPC64-NEXT: clrldi 4, 4, 56
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+ %aext = zext i8 %a to i64
+ %bext = zext i8 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
+ %nabs = sub i64 0, %abs
+ %trunc = trunc i64 %nabs to i8
+ ret i8 %trunc
+}
+
+define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
+; PPC32-LABEL: abd_ext_i16:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 16
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i16:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 48
+; PPC64-NEXT: clrldi 4, 4, 48
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+ %aext = zext i16 %a to i64
+ %bext = zext i16 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %nabs = sub i64 0, %abs
+ %trunc = trunc i64 %nabs to i16
+ ret i16 %trunc
+}
+
+define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
+; PPC32-LABEL: abd_ext_i16_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 16
+; PPC32-NEXT: cmplw 3, 4
+; PPC32-NEXT: bgt 0, .LBB4_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: neg 3, 3
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB4_2:
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: neg 3, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i16_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 48
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+ %aext = zext i16 %a to i64
+ %bext = zext i32 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %nabs = sub i64 0, %abs
+ %trunc = trunc i64 %nabs to i16
+ ret i16 %trunc
+}
+
+define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
+; PPC32-LABEL: abd_ext_i16_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 16
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i16_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 48
+; PPC64-NEXT: clrldi 4, 4, 48
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+ %aext = zext i16 %a to i64
+ %bext = zext i16 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
+ %nabs = sub i64 0, %abs
+ %trunc = trunc i64 %nabs to i16
+ ret i16 %trunc
+}
+
+define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
+; PPC32-LABEL: abd_ext_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: cmplw 3, 4
+; PPC32-NEXT: bgt 0, .LBB6_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: neg 3, 3
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB6_2:
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: neg 3, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+ %aext = zext i32 %a to i64
+ %bext = zext i32 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %nabs = sub i64 0, %abs
+ %trunc = trunc i64 %nabs to i32
+ ret i32 %trunc
+}
+
+define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
+; PPC32-LABEL: abd_ext_i32_i16:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: cmplw 3, 4
+; PPC32-NEXT: bgt 0, .LBB7_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: neg 3, 3
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB7_2:
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: neg 3, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i32_i16:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: clrldi 4, 4, 48
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+ %aext = zext i32 %a to i64
+ %bext = zext i16 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %nabs = sub i64 0, %abs
+ %trunc = trunc i64 %nabs to i32
+ ret i32 %trunc
+}
+
+define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
+; PPC32-LABEL: abd_ext_i32_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: cmplw 3, 4
+; PPC32-NEXT: bgt 0, .LBB8_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: neg 3, 3
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB8_2:
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: neg 3, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i32_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+ %aext = zext i32 %a to i64
+ %bext = zext i32 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
+ %nabs = sub i64 0, %abs
+ %trunc = trunc i64 %nabs to i32
+ ret i32 %trunc
+}
+
+define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_ext_i64:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: addze. 5, 7
+; PPC32-NEXT: li 5, -1
+; PPC32-NEXT: bc 12, 2, .LBB9_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 5, 0
+; PPC32-NEXT: .LBB9_2:
+; PPC32-NEXT: xor 4, 4, 5
+; PPC32-NEXT: xor 3, 3, 5
+; PPC32-NEXT: subc 4, 4, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: subfic 4, 4, 0
+; PPC32-NEXT: subfze 3, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i64:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 4
+; PPC64-NEXT: bgt 0, .LBB9_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: neg 3, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB9_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: neg 3, 3
+; PPC64-NEXT: blr
+ %aext = zext i64 %a to i128
+ %bext = zext i64 %b to i128
+ %sub = sub i128 %aext, %bext
+ %abs = call i128 @llvm.abs.i128(i128 %sub, i1 false)
+ %nabs = sub i128 0, %abs
+ %trunc = trunc i128 %nabs to i64
+ ret i64 %trunc
+}
+
+define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_ext_i64_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: addze. 5, 7
+; PPC32-NEXT: li 5, -1
+; PPC32-NEXT: bc 12, 2, .LBB10_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 5, 0
+; PPC32-NEXT: .LBB10_2:
+; PPC32-NEXT: xor 4, 4, 5
+; PPC32-NEXT: xor 3, 3, 5
+; PPC32-NEXT: subc 4, 4, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: subfic 4, 4, 0
+; PPC32-NEXT: subfze 3, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i64_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 4
+; PPC64-NEXT: bgt 0, .LBB10_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: neg 3, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB10_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: neg 3, 3
+; PPC64-NEXT: blr
+ %aext = zext i64 %a to i128
+ %bext = zext i64 %b to i128
+ %sub = sub i128 %aext, %bext
+ %abs = call i128 @llvm.abs.i128(i128 %sub, i1 true)
+ %nabs = sub i128 0, %abs
+ %trunc = trunc i128 %nabs to i64
+ ret i64 %trunc
+}
+
+define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
+; PPC32-LABEL: abd_ext_i128:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 6, 6, 10
+; PPC32-NEXT: subfe 5, 9, 5
+; PPC32-NEXT: subfe 4, 8, 4
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: addze. 7, 11
+; PPC32-NEXT: li 7, -1
+; PPC32-NEXT: bc 12, 2, .LBB11_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: .LBB11_2:
+; PPC32-NEXT: xor 6, 6, 7
+; PPC32-NEXT: xor 5, 5, 7
+; PPC32-NEXT: subc 6, 6, 7
+; PPC32-NEXT: xor 4, 4, 7
+; PPC32-NEXT: subfe 5, 7, 5
+; PPC32-NEXT: xor 3, 3, 7
+; PPC32-NEXT: subfe 4, 7, 4
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: subfic 6, 6, 0
+; PPC32-NEXT: subfze 5, 5
+; PPC32-NEXT: subfze 4, 4
+; PPC32-NEXT: subfze 3, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i128:
+; PPC64: # %bb.0:
+; PPC64-NEXT: subc 4, 4, 6
+; PPC64-NEXT: li 7, 0
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: addze 5, 7
+; PPC64-NEXT: addic 5, 5, -1
+; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: xor 4, 4, 5
+; PPC64-NEXT: xor 3, 3, 5
+; PPC64-NEXT: subc 4, 4, 5
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: subfic 4, 4, 0
+; PPC64-NEXT: subfze 3, 3
+; PPC64-NEXT: blr
+ %aext = zext i128 %a to i256
+ %bext = zext i128 %b to i256
+ %sub = sub i256 %aext, %bext
+ %abs = call i256 @llvm.abs.i256(i256 %sub, i1 false)
+ %nabs = sub i256 0, %abs
+ %trunc = trunc i256 %nabs to i128
+ ret i128 %trunc
+}
+
+define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
+; PPC32-LABEL: abd_ext_i128_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 6, 6, 10
+; PPC32-NEXT: subfe 5, 9, 5
+; PPC32-NEXT: subfe 4, 8, 4
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: addze. 7, 11
+; PPC32-NEXT: li 7, -1
+; PPC32-NEXT: bc 12, 2, .LBB12_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: .LBB12_2:
+; PPC32-NEXT: xor 6, 6, 7
+; PPC32-NEXT: xor 5, 5, 7
+; PPC32-NEXT: subc 6, 6, 7
+; PPC32-NEXT: xor 4, 4, 7
+; PPC32-NEXT: subfe 5, 7, 5
+; PPC32-NEXT: xor 3, 3, 7
+; PPC32-NEXT: subfe 4, 7, 4
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: subfic 6, 6, 0
+; PPC32-NEXT: subfze 5, 5
+; PPC32-NEXT: subfze 4, 4
+; PPC32-NEXT: subfze 3, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i128_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: subc 4, 4, 6
+; PPC64-NEXT: li 7, 0
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: addze 5, 7
+; PPC64-NEXT: addic 5, 5, -1
+; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: xor 4, 4, 5
+; PPC64-NEXT: xor 3, 3, 5
+; PPC64-NEXT: subc 4, 4, 5
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: subfic 4, 4, 0
+; PPC64-NEXT: subfze 3, 3
+; PPC64-NEXT: blr
+ %aext = zext i128 %a to i256
+ %bext = zext i128 %b to i256
+ %sub = sub i256 %aext, %bext
+ %abs = call i256 @llvm.abs.i256(i256 %sub, i1 true)
+ %nabs = sub i256 0, %abs
+ %trunc = trunc i256 %nabs to i128
+ ret i128 %trunc
+}
+
+;
+; sub(umin(a,b),umax(a,b)) -> nabdu(a,b)
+;
+
+define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: abd_minmax_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 4, 4, 24
+; CHECK-NEXT: clrlwi 3, 3, 24
+; CHECK-NEXT: cmplw 3, 4
+; CHECK-NEXT: mr 5, 3
+; CHECK-NEXT: bge 0, .LBB13_3
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ble 0, .LBB13_4
+; CHECK-NEXT: .LBB13_2:
+; CHECK-NEXT: sub 3, 5, 3
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB13_3:
+; CHECK-NEXT: mr 5, 4
+; CHECK-NEXT: bgt 0, .LBB13_2
+; CHECK-NEXT: .LBB13_4:
+; CHECK-NEXT: mr 3, 4
+; CHECK-NEXT: sub 3, 5, 3
+; CHECK-NEXT: blr
+ %min = call i8 @llvm.umin.i8(i8 %a, i8 %b)
+ %max = call i8 @llvm.umax.i8(i8 %a, i8 %b)
+ %sub = sub i8 %min, %max
+ ret i8 %sub
+}
+
+define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
+; CHECK-LABEL: abd_minmax_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 4, 4, 16
+; CHECK-NEXT: clrlwi 3, 3, 16
+; CHECK-NEXT: cmplw 3, 4
+; CHECK-NEXT: mr 5, 3
+; CHECK-NEXT: bge 0, .LBB14_3
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ble 0, .LBB14_4
+; CHECK-NEXT: .LBB14_2:
+; CHECK-NEXT: sub 3, 5, 3
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB14_3:
+; CHECK-NEXT: mr 5, 4
+; CHECK-NEXT: bgt 0, .LBB14_2
+; CHECK-NEXT: .LBB14_4:
+; CHECK-NEXT: mr 3, 4
+; CHECK-NEXT: sub 3, 5, 3
+; CHECK-NEXT: blr
+ %min = call i16 @llvm.umin.i16(i16 %a, i16 %b)
+ %max = call i16 @llvm.umax.i16(i16 %a, i16 %b)
+ %sub = sub i16 %min, %max
+ ret i16 %sub
+}
+
+define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: abd_minmax_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmplw 3, 4
+; CHECK-NEXT: mr 5, 3
+; CHECK-NEXT: bge 0, .LBB15_3
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ble 0, .LBB15_4
+; CHECK-NEXT: .LBB15_2:
+; CHECK-NEXT: sub 3, 5, 3
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB15_3:
+; CHECK-NEXT: mr 5, 4
+; CHECK-NEXT: bgt 0, .LBB15_2
+; CHECK-NEXT: .LBB15_4:
+; CHECK-NEXT: mr 3, 4
+; CHECK-NEXT: sub 3, 5, 3
+; CHECK-NEXT: blr
+ %min = call i32 @llvm.umin.i32(i32 %a, i32 %b)
+ %max = call i32 @llvm.umax.i32(i32 %a, i32 %b)
+ %sub = sub i32 %min, %max
+ ret i32 %sub
+}
+
+define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_minmax_i64:
+; PPC32: # %bb.0:
+; PPC32-NEXT: cmplw 3, 5
+; PPC32-NEXT: cmplw 1, 4, 6
+; PPC32-NEXT: crandc 20, 0, 2
+; PPC32-NEXT: crand 21, 2, 4
+; PPC32-NEXT: cror 20, 21, 20
+; PPC32-NEXT: mr 7, 3
+; PPC32-NEXT: bc 12, 20, .LBB16_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: mr 7, 5
+; PPC32-NEXT: .LBB16_2:
+; PPC32-NEXT: mr 8, 4
+; PPC32-NEXT: bc 12, 20, .LBB16_4
+; PPC32-NEXT: # %bb.3:
+; PPC32-NEXT: mr 8, 6
+; PPC32-NEXT: .LBB16_4:
+; PPC32-NEXT: crandc 20, 1, 2
+; PPC32-NEXT: crand 21, 2, 5
+; PPC32-NEXT: cror 20, 21, 20
+; PPC32-NEXT: bc 12, 20, .LBB16_6
+; PPC32-NEXT: # %bb.5:
+; PPC32-NEXT: mr 3, 5
+; PPC32-NEXT: .LBB16_6:
+; PPC32-NEXT: bc 12, 20, .LBB16_8
+; PPC32-NEXT: # %bb.7:
+; PPC32-NEXT: mr 4, 6
+; PPC32-NEXT: .LBB16_8:
+; PPC32-NEXT: subc 4, 8, 4
+; PPC32-NEXT: subfe 3, 3, 7
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_minmax_i64:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 4
+; PPC64-NEXT: mr 5, 3
+; PPC64-NEXT: bge 0, .LBB16_3
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: ble 0, .LBB16_4
+; PPC64-NEXT: .LBB16_2:
+; PPC64-NEXT: sub 3, 5, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB16_3:
+; PPC64-NEXT: mr 5, 4
+; PPC64-NEXT: bgt 0, .LBB16_2
+; PPC64-NEXT: .LBB16_4:
+; PPC64-NEXT: mr 3, 4
+; PPC64-NEXT: sub 3, 5, 3
+; PPC64-NEXT: blr
+ %min = call i64 @llvm.umin.i64(i64 %a, i64 %b)
+ %max = call i64 @llvm.umax.i64(i64 %a, i64 %b)
+ %sub = sub i64 %min, %max
+ ret i64 %sub
+}
+
+define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
+; PPC32-LABEL: abd_minmax_i128:
+; PPC32: # %bb.0:
+; PPC32-NEXT: stwu 1, -16(1)
+; PPC32-NEXT: cmplw 3, 7
+; PPC32-NEXT: cmplw 1, 4, 8
+; PPC32-NEXT: xor 11, 3, 7
+; PPC32-NEXT: xor 12, 4, 8
+; PPC32-NEXT: cmplw 5, 5, 9
+; PPC32-NEXT: cmplw 6, 6, 10
+; PPC32-NEXT: crandc 23, 0, 2
+; PPC32-NEXT: crand 26, 2, 4
+; PPC32-NEXT: or 11, 12, 11
+; PPC32-NEXT: crandc 20, 20, 22
+; PPC32-NEXT: crand 24, 22, 24
+; PPC32-NEXT: cror 23, 26, 23
+; PPC32-NEXT: cmplwi 7, 11, 0
+; PPC32-NEXT: cror 20, 24, 20
+; PPC32-NEXT: crandc 23, 23, 30
+; PPC32-NEXT: crand 20, 30, 20
+; PPC32-NEXT: cror 20, 20, 23
+; PPC32-NEXT: mr 11, 3
+; PPC32-NEXT: stw 30, 8(1) # 4-byte Folded Spill
+; PPC32-NEXT: bc 4, 20, .LBB17_11
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: mr 12, 4
+; PPC32-NEXT: bc 4, 20, .LBB17_12
+; PPC32-NEXT: .LBB17_2:
+; PPC32-NEXT: mr 0, 5
+; PPC32-NEXT: bc 4, 20, .LBB17_13
+; PPC32-NEXT: .LBB17_3:
+; PPC32-NEXT: mr 30, 6
+; PPC32-NEXT: bc 12, 20, .LBB17_5
+; PPC32-NEXT: .LBB17_4:
+; PPC32-NEXT: mr 30, 10
+; PPC32-NEXT: .LBB17_5:
+; PPC32-NEXT: crandc 20, 1, 2
+; PPC32-NEXT: crand 23, 2, 5
+; PPC32-NEXT: crandc 21, 21, 22
+; PPC32-NEXT: crand 22, 22, 25
+; PPC32-NEXT: cror 20, 23, 20
+; PPC32-NEXT: cror 21, 22, 21
+; PPC32-NEXT: crandc 20, 20, 30
+; PPC32-NEXT: crand 21, 30, 21
+; PPC32-NEXT: cror 20, 21, 20
+; PPC32-NEXT: bc 4, 20, .LBB17_14
+; PPC32-NEXT: # %bb.6:
+; PPC32-NEXT: bc 4, 20, .LBB17_15
+; PPC32-NEXT: .LBB17_7:
+; PPC32-NEXT: bc 4, 20, .LBB17_16
+; PPC32-NEXT: .LBB17_8:
+; PPC32-NEXT: bc 12, 20, .LBB17_10
+; PPC32-NEXT: .LBB17_9:
+; PPC32-NEXT: mr 6, 10
+; PPC32-NEXT: .LBB17_10:
+; PPC32-NEXT: subc 6, 30, 6
+; PPC32-NEXT: subfe 5, 5, 0
+; PPC32-NEXT: subfe 4, 4, 12
+; PPC32-NEXT: subfe 3, 3, 11
+; PPC32-NEXT: lwz 30, 8(1) # 4-byte Folded Reload
+; PPC32-NEXT: addi 1, 1, 16
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB17_11:
+; PPC32-NEXT: mr 11, 7
+; PPC32-NEXT: mr 12, 4
+; PPC32-NEXT: bc 12, 20, .LBB17_2
+; PPC32-NEXT: .LBB17_12:
+; PPC32-NEXT: mr 12, 8
+; PPC32-NEXT: mr 0, 5
+; PPC32-NEXT: bc 12, 20, .LBB17_3
+; PPC32-NEXT: .LBB17_13:
+; PPC32-NEXT: mr 0, 9
+; PPC32-NEXT: mr 30, 6
+; PPC32-NEXT: bc 4, 20, .LBB17_4
+; PPC32-NEXT: b .LBB17_5
+; PPC32-NEXT: .LBB17_14:
+; PPC32-NEXT: mr 3, 7
+; PPC32-NEXT: bc 12, 20, .LBB17_7
+; PPC32-NEXT: .LBB17_15:
+; PPC32-NEXT: mr 4, 8
+; PPC32-NEXT: bc 12, 20, .LBB17_8
+; PPC32-NEXT: .LBB17_16:
+; PPC32-NEXT: mr 5, 9
+; PPC32-NEXT: bc 4, 20, .LBB17_9
+; PPC32-NEXT: b .LBB17_10
+;
+; PPC64-LABEL: abd_minmax_i128:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 5
+; PPC64-NEXT: cmpld 1, 4, 6
+; PPC64-NEXT: crandc 20, 0, 2
+; PPC64-NEXT: mr 7, 3
+; PPC64-NEXT: crand 21, 2, 4
+; PPC64-NEXT: cror 20, 21, 20
+; PPC64-NEXT: bc 12, 20, .LBB17_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: mr 7, 5
+; PPC64-NEXT: .LBB17_2:
+; PPC64-NEXT: mr 8, 4
+; PPC64-NEXT: bc 12, 20, .LBB17_4
+; PPC64-NEXT: # %bb.3:
+; PPC64-NEXT: mr 8, 6
+; PPC64-NEXT: .LBB17_4:
+; PPC64-NEXT: crandc 20, 1, 2
+; PPC64-NEXT: crand 21, 2, 5
+; PPC64-NEXT: cror 20, 21, 20
+; PPC64-NEXT: bc 12, 20, .LBB17_6
+; PPC64-NEXT: # %bb.5:
+; PPC64-NEXT: mr 3, 5
+; PPC64-NEXT: .LBB17_6:
+; PPC64-NEXT: bc 12, 20, .LBB17_8
+; PPC64-NEXT: # %bb.7:
+; PPC64-NEXT: mr 4, 6
+; PPC64-NEXT: .LBB17_8:
+; PPC64-NEXT: subc 4, 8, 4
+; PPC64-NEXT: subfe 3, 3, 7
+; PPC64-NEXT: blr
+ %min = call i128 @llvm.umin.i128(i128 %a, i128 %b)
+ %max = call i128 @llvm.umax.i128(i128 %a, i128 %b)
+ %sub = sub i128 %min, %max
+ ret i128 %sub
+}
+
+;
+; select(icmp(a,b),sub(a,b),sub(b,a)) -> nabdu(a,b)
+;
+
+define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: abd_cmp_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 5, 4, 24
+; CHECK-NEXT: clrlwi 6, 3, 24
+; CHECK-NEXT: cmplw 6, 5
+; CHECK-NEXT: ble 0, .LBB18_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sub 3, 4, 3
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB18_2:
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %cmp = icmp ule i8 %a, %b
+ %ab = sub i8 %a, %b
+ %ba = sub i8 %b, %a
+ %sel = select i1 %cmp, i8 %ab, i8 %ba
+ ret i8 %sel
+}
+
+define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
+; CHECK-LABEL: abd_cmp_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 5, 4, 16
+; CHECK-NEXT: clrlwi 6, 3, 16
+; CHECK-NEXT: cmplw 6, 5
+; CHECK-NEXT: blt 0, .LBB19_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sub 3, 4, 3
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB19_2:
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %cmp = icmp ult i16 %a, %b
+ %ab = sub i16 %a, %b
+ %ba = sub i16 %b, %a
+ %sel = select i1 %cmp, i16 %ab, i16 %ba
+ ret i16 %sel
+}
+
+define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: abd_cmp_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmplw 3, 4
+; CHECK-NEXT: bge 0, .LBB20_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB20_2:
+; CHECK-NEXT: sub 3, 4, 3
+; CHECK-NEXT: blr
+ %cmp = icmp uge i32 %a, %b
+ %ab = sub i32 %a, %b
+ %ba = sub i32 %b, %a
+ %sel = select i1 %cmp, i32 %ba, i32 %ab
+ ret i32 %sel
+}
+
+define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_cmp_i64:
+; PPC32: # %bb.0:
+; PPC32-NEXT: mr 7, 4
+; PPC32-NEXT: cmplw 1, 4, 6
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: mr 8, 3
+; PPC32-NEXT: cmplw 3, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: crandc 20, 0, 2
+; PPC32-NEXT: crand 21, 2, 4
+; PPC32-NEXT: subc 6, 6, 7
+; PPC32-NEXT: cror 20, 21, 20
+; PPC32-NEXT: subfe 5, 8, 5
+; PPC32-NEXT: bc 12, 20, .LBB21_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: mr 3, 5
+; PPC32-NEXT: .LBB21_2:
+; PPC32-NEXT: bclr 12, 20, 0
+; PPC32-NEXT: # %bb.3:
+; PPC32-NEXT: mr 4, 6
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_cmp_i64:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 4
+; PPC64-NEXT: blt 0, .LBB21_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB21_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
+ %cmp = icmp ult i64 %a, %b
+ %ab = sub i64 %a, %b
+ %ba = sub i64 %b, %a
+ %sel = select i1 %cmp, i64 %ab, i64 %ba
+ ret i64 %sel
+}
+
+define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
+; PPC32-LABEL: abd_cmp_i128:
+; PPC32: # %bb.0:
+; PPC32-NEXT: stwu 1, -16(1)
+; PPC32-NEXT: cmplw 3, 7
+; PPC32-NEXT: cmplw 1, 4, 8
+; PPC32-NEXT: cmplw 5, 5, 9
+; PPC32-NEXT: mr 11, 6
+; PPC32-NEXT: crand 21, 2, 4
+; PPC32-NEXT: cmplw 1, 6, 10
+; PPC32-NEXT: subc 6, 6, 10
+; PPC32-NEXT: stw 30, 8(1) # 4-byte Folded Spill
+; PPC32-NEXT: mr 12, 5
+; PPC32-NEXT: mr 0, 4
+; PPC32-NEXT: mr 30, 3
+; PPC32-NEXT: xor 3, 3, 7
+; PPC32-NEXT: xor 4, 4, 8
+; PPC32-NEXT: subfe 5, 9, 5
+; PPC32-NEXT: or 3, 4, 3
+; PPC32-NEXT: subfe 4, 8, 0
+; PPC32-NEXT: crandc 23, 0, 2
+; PPC32-NEXT: cmplwi 3, 0
+; PPC32-NEXT: subfe 3, 7, 30
+; PPC32-NEXT: crandc 20, 20, 22
+; PPC32-NEXT: crand 22, 22, 4
+; PPC32-NEXT: subc 10, 10, 11
+; PPC32-NEXT: cror 21, 21, 23
+; PPC32-NEXT: cror 20, 22, 20
+; PPC32-NEXT: subfe 9, 12, 9
+; PPC32-NEXT: crandc 21, 21, 2
+; PPC32-NEXT: crand 20, 2, 20
+; PPC32-NEXT: subfe 8, 0, 8
+; PPC32-NEXT: cror 20, 20, 21
+; PPC32-NEXT: subfe 7, 30, 7
+; PPC32-NEXT: bc 4, 20, .LBB22_6
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: bc 4, 20, .LBB22_7
+; PPC32-NEXT: .LBB22_2:
+; PPC32-NEXT: bc 4, 20, .LBB22_8
+; PPC32-NEXT: .LBB22_3:
+; PPC32-NEXT: bc 12, 20, .LBB22_5
+; PPC32-NEXT: .LBB22_4:
+; PPC32-NEXT: mr 6, 10
+; PPC32-NEXT: .LBB22_5:
+; PPC32-NEXT: lwz 30, 8(1) # 4-byte Folded Reload
+; PPC32-NEXT: addi 1, 1, 16
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB22_6:
+; PPC32-NEXT: mr 3, 7
+; PPC32-NEXT: bc 12, 20, .LBB22_2
+; PPC32-NEXT: .LBB22_7:
+; PPC32-NEXT: mr 4, 8
+; PPC32-NEXT: bc 12, 20, .LBB22_3
+; PPC32-NEXT: .LBB22_8:
+; PPC32-NEXT: mr 5, 9
+; PPC32-NEXT: bc 4, 20, .LBB22_4
+; PPC32-NEXT: b .LBB22_5
+;
+; PPC64-LABEL: abd_cmp_i128:
+; PPC64: # %bb.0:
+; PPC64-NEXT: mr 7, 4
+; PPC64-NEXT: cmpld 1, 4, 6
+; PPC64-NEXT: subc 4, 4, 6
+; PPC64-NEXT: mr 8, 3
+; PPC64-NEXT: cmpld 3, 5
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: crandc 20, 0, 2
+; PPC64-NEXT: subc 6, 6, 7
+; PPC64-NEXT: subfe 5, 8, 5
+; PPC64-NEXT: crand 21, 2, 4
+; PPC64-NEXT: cror 20, 21, 20
+; PPC64-NEXT: bc 12, 20, .LBB22_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: mr 3, 5
+; PPC64-NEXT: .LBB22_2:
+; PPC64-NEXT: bclr 12, 20, 0
+; PPC64-NEXT: # %bb.3:
+; PPC64-NEXT: mr 4, 6
+; PPC64-NEXT: blr
+ %cmp = icmp ult i128 %a, %b
+ %ab = sub i128 %a, %b
+ %ba = sub i128 %b, %a
+ %sel = select i1 %cmp, i128 %ab, i128 %ba
+ ret i128 %sel
+}
+
+declare i8 @llvm.abs.i8(i8, i1)
+declare i16 @llvm.abs.i16(i16, i1)
+declare i32 @llvm.abs.i32(i32, i1)
+declare i64 @llvm.abs.i64(i64, i1)
+declare i128 @llvm.abs.i128(i128, i1)
+
+declare i8 @llvm.umax.i8(i8, i8)
+declare i16 @llvm.umax.i16(i16, i16)
+declare i32 @llvm.umax.i32(i32, i32)
+declare i64 @llvm.umax.i64(i64, i64)
+
+declare i8 @llvm.umin.i8(i8, i8)
+declare i16 @llvm.umin.i16(i16, i16)
+declare i32 @llvm.umin.i32(i32, i32)
+declare i64 @llvm.umin.i64(i64, i64)
diff --git a/llvm/test/CodeGen/PowerPC/abdu.ll b/llvm/test/CodeGen/PowerPC/abdu.ll
new file mode 100644
index 0000000000000..b4ae1954d3d59
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/abdu.ll
@@ -0,0 +1,982 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc-unknown-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,PPC32
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,PPC64
+
+;
+; trunc(abs(sub(zext(a),zext(b)))) -> abdu(a,b)
+;
+
+define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
+; PPC32-LABEL: abd_ext_i8:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 24
+; PPC32-NEXT: clrlwi 4, 4, 24
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i8:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrlwi 3, 3, 24
+; PPC64-NEXT: clrlwi 4, 4, 24
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: srawi 4, 3, 31
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+ %aext = zext i8 %a to i64
+ %bext = zext i8 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %trunc = trunc i64 %abs to i8
+ ret i8 %trunc
+}
+
+define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
+; PPC32-LABEL: abd_ext_i8_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 24
+; PPC32-NEXT: clrlwi 4, 4, 24
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i8_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrlwi 3, 3, 24
+; PPC64-NEXT: clrlwi 4, 4, 24
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: srawi 4, 3, 31
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+ %aext = zext i8 %a to i64
+ %bext = zext i8 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
+ %trunc = trunc i64 %abs to i8
+ ret i8 %trunc
+}
+
+define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
+; PPC32-LABEL: abd_ext_i16:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 16
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i16:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrlwi 3, 3, 16
+; PPC64-NEXT: clrlwi 4, 4, 16
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: srawi 4, 3, 31
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+ %aext = zext i16 %a to i64
+ %bext = zext i16 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %trunc = trunc i64 %abs to i16
+ ret i16 %trunc
+}
+
+define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
+; PPC32-LABEL: abd_ext_i16_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 16
+; PPC32-NEXT: cmplw 3, 4
+; PPC32-NEXT: bgt 0, .LBB3_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB3_2:
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i16_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrlwi 3, 3, 16
+; PPC64-NEXT: cmplw 3, 4
+; PPC64-NEXT: bgt 0, .LBB3_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB3_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+ %aext = zext i16 %a to i64
+ %bext = zext i32 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %trunc = trunc i64 %abs to i16
+ ret i16 %trunc
+}
+
+define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
+; PPC32-LABEL: abd_ext_i16_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 16
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i16_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrlwi 3, 3, 16
+; PPC64-NEXT: clrlwi 4, 4, 16
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: srawi 4, 3, 31
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+ %aext = zext i16 %a to i64
+ %bext = zext i16 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
+ %trunc = trunc i64 %abs to i16
+ ret i16 %trunc
+}
+
+define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
+; PPC32-LABEL: abd_ext_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: cmplw 3, 4
+; PPC32-NEXT: bgt 0, .LBB5_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB5_2:
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmplw 3, 4
+; PPC64-NEXT: bgt 0, .LBB5_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB5_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+ %aext = zext i32 %a to i64
+ %bext = zext i32 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %trunc = trunc i64 %abs to i32
+ ret i32 %trunc
+}
+
+define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
+; PPC32-LABEL: abd_ext_i32_i16:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: cmplw 3, 4
+; PPC32-NEXT: bgt 0, .LBB6_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB6_2:
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i32_i16:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrlwi 4, 4, 16
+; PPC64-NEXT: cmplw 3, 4
+; PPC64-NEXT: bgt 0, .LBB6_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB6_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+ %aext = zext i32 %a to i64
+ %bext = zext i16 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %trunc = trunc i64 %abs to i32
+ ret i32 %trunc
+}
+
+define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
+; PPC32-LABEL: abd_ext_i32_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: cmplw 3, 4
+; PPC32-NEXT: bgt 0, .LBB7_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB7_2:
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i32_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmplw 3, 4
+; PPC64-NEXT: bgt 0, .LBB7_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB7_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+ %aext = zext i32 %a to i64
+ %bext = zext i32 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
+ %trunc = trunc i64 %abs to i32
+ ret i32 %trunc
+}
+
+define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_ext_i64:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: addze. 5, 7
+; PPC32-NEXT: li 5, -1
+; PPC32-NEXT: bc 12, 2, .LBB8_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 5, 0
+; PPC32-NEXT: .LBB8_2:
+; PPC32-NEXT: xor 4, 4, 5
+; PPC32-NEXT: xor 3, 3, 5
+; PPC32-NEXT: subc 4, 4, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i64:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 4
+; PPC64-NEXT: bgt 0, .LBB8_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB8_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
+ %aext = zext i64 %a to i128
+ %bext = zext i64 %b to i128
+ %sub = sub i128 %aext, %bext
+ %abs = call i128 @llvm.abs.i128(i128 %sub, i1 false)
+ %trunc = trunc i128 %abs to i64
+ ret i64 %trunc
+}
+
+define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_ext_i64_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: addze. 5, 7
+; PPC32-NEXT: li 5, -1
+; PPC32-NEXT: bc 12, 2, .LBB9_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 5, 0
+; PPC32-NEXT: .LBB9_2:
+; PPC32-NEXT: xor 4, 4, 5
+; PPC32-NEXT: xor 3, 3, 5
+; PPC32-NEXT: subc 4, 4, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i64_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 4
+; PPC64-NEXT: bgt 0, .LBB9_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB9_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
+ %aext = zext i64 %a to i128
+ %bext = zext i64 %b to i128
+ %sub = sub i128 %aext, %bext
+ %abs = call i128 @llvm.abs.i128(i128 %sub, i1 true)
+ %trunc = trunc i128 %abs to i64
+ ret i64 %trunc
+}
+
+define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
+; PPC32-LABEL: abd_ext_i128:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 6, 6, 10
+; PPC32-NEXT: subfe 5, 9, 5
+; PPC32-NEXT: subfe 4, 8, 4
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: addze. 7, 11
+; PPC32-NEXT: li 7, -1
+; PPC32-NEXT: bc 12, 2, .LBB10_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: .LBB10_2:
+; PPC32-NEXT: xor 6, 6, 7
+; PPC32-NEXT: xor 5, 5, 7
+; PPC32-NEXT: subc 6, 6, 7
+; PPC32-NEXT: xor 4, 4, 7
+; PPC32-NEXT: subfe 5, 7, 5
+; PPC32-NEXT: xor 3, 3, 7
+; PPC32-NEXT: subfe 4, 7, 4
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i128:
+; PPC64: # %bb.0:
+; PPC64-NEXT: subc 4, 4, 6
+; PPC64-NEXT: li 7, 0
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: addze 5, 7
+; PPC64-NEXT: addic 5, 5, -1
+; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: xor 4, 4, 5
+; PPC64-NEXT: xor 3, 3, 5
+; PPC64-NEXT: subc 4, 4, 5
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: blr
+ %aext = zext i128 %a to i256
+ %bext = zext i128 %b to i256
+ %sub = sub i256 %aext, %bext
+ %abs = call i256 @llvm.abs.i256(i256 %sub, i1 false)
+ %trunc = trunc i256 %abs to i128
+ ret i128 %trunc
+}
+
+define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
+; PPC32-LABEL: abd_ext_i128_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 6, 6, 10
+; PPC32-NEXT: subfe 5, 9, 5
+; PPC32-NEXT: subfe 4, 8, 4
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: addze. 7, 11
+; PPC32-NEXT: li 7, -1
+; PPC32-NEXT: bc 12, 2, .LBB11_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: .LBB11_2:
+; PPC32-NEXT: xor 6, 6, 7
+; PPC32-NEXT: xor 5, 5, 7
+; PPC32-NEXT: subc 6, 6, 7
+; PPC32-NEXT: xor 4, 4, 7
+; PPC32-NEXT: subfe 5, 7, 5
+; PPC32-NEXT: xor 3, 3, 7
+; PPC32-NEXT: subfe 4, 7, 4
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i128_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: subc 4, 4, 6
+; PPC64-NEXT: li 7, 0
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: addze 5, 7
+; PPC64-NEXT: addic 5, 5, -1
+; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: xor 4, 4, 5
+; PPC64-NEXT: xor 3, 3, 5
+; PPC64-NEXT: subc 4, 4, 5
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: blr
+ %aext = zext i128 %a to i256
+ %bext = zext i128 %b to i256
+ %sub = sub i256 %aext, %bext
+ %abs = call i256 @llvm.abs.i256(i256 %sub, i1 true)
+ %trunc = trunc i256 %abs to i128
+ ret i128 %trunc
+}
+
+;
+; sub(umax(a,b),umin(a,b)) -> abdu(a,b)
+;
+
+define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: abd_minmax_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 3, 3, 24
+; CHECK-NEXT: clrlwi 4, 4, 24
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: srawi 4, 3, 31
+; CHECK-NEXT: xor 3, 3, 4
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %min = call i8 @llvm.umin.i8(i8 %a, i8 %b)
+ %max = call i8 @llvm.umax.i8(i8 %a, i8 %b)
+ %sub = sub i8 %max, %min
+ ret i8 %sub
+}
+
+define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
+; CHECK-LABEL: abd_minmax_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 3, 3, 16
+; CHECK-NEXT: clrlwi 4, 4, 16
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: srawi 4, 3, 31
+; CHECK-NEXT: xor 3, 3, 4
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %min = call i16 @llvm.umin.i16(i16 %a, i16 %b)
+ %max = call i16 @llvm.umax.i16(i16 %a, i16 %b)
+ %sub = sub i16 %max, %min
+ ret i16 %sub
+}
+
+define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: abd_minmax_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmplw 3, 4
+; CHECK-NEXT: bgt 0, .LBB14_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sub 3, 4, 3
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB14_2:
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %min = call i32 @llvm.umin.i32(i32 %a, i32 %b)
+ %max = call i32 @llvm.umax.i32(i32 %a, i32 %b)
+ %sub = sub i32 %max, %min
+ ret i32 %sub
+}
+
+define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_minmax_i64:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: addze. 5, 7
+; PPC32-NEXT: li 5, -1
+; PPC32-NEXT: bc 12, 2, .LBB15_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 5, 0
+; PPC32-NEXT: .LBB15_2:
+; PPC32-NEXT: xor 4, 4, 5
+; PPC32-NEXT: xor 3, 3, 5
+; PPC32-NEXT: subc 4, 4, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_minmax_i64:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 4
+; PPC64-NEXT: bgt 0, .LBB15_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB15_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
+ %min = call i64 @llvm.umin.i64(i64 %a, i64 %b)
+ %max = call i64 @llvm.umax.i64(i64 %a, i64 %b)
+ %sub = sub i64 %max, %min
+ ret i64 %sub
+}
+
+define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
+; PPC32-LABEL: abd_minmax_i128:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 6, 6, 10
+; PPC32-NEXT: subfe 5, 9, 5
+; PPC32-NEXT: subfe 4, 8, 4
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: addze. 7, 11
+; PPC32-NEXT: li 7, -1
+; PPC32-NEXT: bc 12, 2, .LBB16_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: .LBB16_2:
+; PPC32-NEXT: xor 6, 6, 7
+; PPC32-NEXT: xor 5, 5, 7
+; PPC32-NEXT: subc 6, 6, 7
+; PPC32-NEXT: xor 4, 4, 7
+; PPC32-NEXT: subfe 5, 7, 5
+; PPC32-NEXT: xor 3, 3, 7
+; PPC32-NEXT: subfe 4, 7, 4
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_minmax_i128:
+; PPC64: # %bb.0:
+; PPC64-NEXT: subc 4, 4, 6
+; PPC64-NEXT: li 7, 0
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: addze 5, 7
+; PPC64-NEXT: addic 5, 5, -1
+; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: xor 4, 4, 5
+; PPC64-NEXT: xor 3, 3, 5
+; PPC64-NEXT: subc 4, 4, 5
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: blr
+ %min = call i128 @llvm.umin.i128(i128 %a, i128 %b)
+ %max = call i128 @llvm.umax.i128(i128 %a, i128 %b)
+ %sub = sub i128 %max, %min
+ ret i128 %sub
+}
+
+;
+; select(icmp(a,b),sub(a,b),sub(b,a)) -> abdu(a,b)
+;
+
+define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: abd_cmp_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 3, 3, 24
+; CHECK-NEXT: clrlwi 4, 4, 24
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: srawi 4, 3, 31
+; CHECK-NEXT: xor 3, 3, 4
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %cmp = icmp ugt i8 %a, %b
+ %ab = sub i8 %a, %b
+ %ba = sub i8 %b, %a
+ %sel = select i1 %cmp, i8 %ab, i8 %ba
+ ret i8 %sel
+}
+
+define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
+; CHECK-LABEL: abd_cmp_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 3, 3, 16
+; CHECK-NEXT: clrlwi 4, 4, 16
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: srawi 4, 3, 31
+; CHECK-NEXT: xor 3, 3, 4
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %cmp = icmp uge i16 %a, %b
+ %ab = sub i16 %a, %b
+ %ba = sub i16 %b, %a
+ %sel = select i1 %cmp, i16 %ab, i16 %ba
+ ret i16 %sel
+}
+
+define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: abd_cmp_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmplw 3, 4
+; CHECK-NEXT: bgt 0, .LBB19_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sub 3, 4, 3
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB19_2:
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %cmp = icmp ult i32 %a, %b
+ %ab = sub i32 %a, %b
+ %ba = sub i32 %b, %a
+ %sel = select i1 %cmp, i32 %ba, i32 %ab
+ ret i32 %sel
+}
+
+define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_cmp_i64:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: addze. 5, 7
+; PPC32-NEXT: li 5, -1
+; PPC32-NEXT: bc 12, 2, .LBB20_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 5, 0
+; PPC32-NEXT: .LBB20_2:
+; PPC32-NEXT: xor 4, 4, 5
+; PPC32-NEXT: xor 3, 3, 5
+; PPC32-NEXT: subc 4, 4, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_cmp_i64:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 4
+; PPC64-NEXT: bgt 0, .LBB20_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB20_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
+ %cmp = icmp uge i64 %a, %b
+ %ab = sub i64 %a, %b
+ %ba = sub i64 %b, %a
+ %sel = select i1 %cmp, i64 %ab, i64 %ba
+ ret i64 %sel
+}
+
+define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
+; PPC32-LABEL: abd_cmp_i128:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 6, 6, 10
+; PPC32-NEXT: subfe 5, 9, 5
+; PPC32-NEXT: subfe 4, 8, 4
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: addze. 7, 11
+; PPC32-NEXT: li 7, -1
+; PPC32-NEXT: bc 12, 2, .LBB21_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: .LBB21_2:
+; PPC32-NEXT: xor 6, 6, 7
+; PPC32-NEXT: xor 5, 5, 7
+; PPC32-NEXT: subc 6, 6, 7
+; PPC32-NEXT: xor 4, 4, 7
+; PPC32-NEXT: subfe 5, 7, 5
+; PPC32-NEXT: xor 3, 3, 7
+; PPC32-NEXT: subfe 4, 7, 4
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_cmp_i128:
+; PPC64: # %bb.0:
+; PPC64-NEXT: subc 4, 4, 6
+; PPC64-NEXT: li 7, 0
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: addze 5, 7
+; PPC64-NEXT: addic 5, 5, -1
+; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: xor 4, 4, 5
+; PPC64-NEXT: xor 3, 3, 5
+; PPC64-NEXT: subc 4, 4, 5
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: blr
+ %cmp = icmp uge i128 %a, %b
+ %ab = sub i128 %a, %b
+ %ba = sub i128 %b, %a
+ %sel = select i1 %cmp, i128 %ab, i128 %ba
+ ret i128 %sel
+}
+
+;
+; sub(select(icmp(a,b),a,b),select(icmp(a,b),b,a)) -> abdu(a,b)
+;
+
+define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: abd_select_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 3, 3, 24
+; CHECK-NEXT: clrlwi 4, 4, 24
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: srawi 4, 3, 31
+; CHECK-NEXT: xor 3, 3, 4
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %cmp = icmp ult i8 %a, %b
+ %ab = select i1 %cmp, i8 %a, i8 %b
+ %ba = select i1 %cmp, i8 %b, i8 %a
+ %sub = sub i8 %ba, %ab
+ ret i8 %sub
+}
+
+define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
+; CHECK-LABEL: abd_select_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 3, 3, 16
+; CHECK-NEXT: clrlwi 4, 4, 16
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: srawi 4, 3, 31
+; CHECK-NEXT: xor 3, 3, 4
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %cmp = icmp ule i16 %a, %b
+ %ab = select i1 %cmp, i16 %a, i16 %b
+ %ba = select i1 %cmp, i16 %b, i16 %a
+ %sub = sub i16 %ba, %ab
+ ret i16 %sub
+}
+
+define i32 @abd_select_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: abd_select_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmplw 3, 4
+; CHECK-NEXT: bgt 0, .LBB24_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sub 3, 4, 3
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB24_2:
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %cmp = icmp ugt i32 %a, %b
+ %ab = select i1 %cmp, i32 %a, i32 %b
+ %ba = select i1 %cmp, i32 %b, i32 %a
+ %sub = sub i32 %ab, %ba
+ ret i32 %sub
+}
+
+define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_select_i64:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: addze. 5, 7
+; PPC32-NEXT: li 5, -1
+; PPC32-NEXT: bc 12, 2, .LBB25_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 5, 0
+; PPC32-NEXT: .LBB25_2:
+; PPC32-NEXT: xor 4, 4, 5
+; PPC32-NEXT: xor 3, 3, 5
+; PPC32-NEXT: subc 4, 4, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_select_i64:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 4
+; PPC64-NEXT: bgt 0, .LBB25_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB25_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
+ %cmp = icmp uge i64 %a, %b
+ %ab = select i1 %cmp, i64 %a, i64 %b
+ %ba = select i1 %cmp, i64 %b, i64 %a
+ %sub = sub i64 %ab, %ba
+ ret i64 %sub
+}
+
+define i128 @abd_select_i128(i128 %a, i128 %b) nounwind {
+; PPC32-LABEL: abd_select_i128:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 6, 6, 10
+; PPC32-NEXT: subfe 5, 9, 5
+; PPC32-NEXT: subfe 4, 8, 4
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: addze. 7, 11
+; PPC32-NEXT: li 7, -1
+; PPC32-NEXT: bc 12, 2, .LBB26_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: .LBB26_2:
+; PPC32-NEXT: xor 6, 6, 7
+; PPC32-NEXT: xor 5, 5, 7
+; PPC32-NEXT: subc 6, 6, 7
+; PPC32-NEXT: xor 4, 4, 7
+; PPC32-NEXT: subfe 5, 7, 5
+; PPC32-NEXT: xor 3, 3, 7
+; PPC32-NEXT: subfe 4, 7, 4
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_select_i128:
+; PPC64: # %bb.0:
+; PPC64-NEXT: subc 4, 4, 6
+; PPC64-NEXT: li 7, 0
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: addze 5, 7
+; PPC64-NEXT: addic 5, 5, -1
+; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: xor 4, 4, 5
+; PPC64-NEXT: xor 3, 3, 5
+; PPC64-NEXT: subc 4, 4, 5
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: blr
+ %cmp = icmp ult i128 %a, %b
+ %ab = select i1 %cmp, i128 %a, i128 %b
+ %ba = select i1 %cmp, i128 %b, i128 %a
+ %sub = sub i128 %ba, %ab
+ ret i128 %sub
+}
+
+;
+; Operand is guaranteed non-zero: -(x | 1) cannot be 0
+;
+
+define i32 @abd_nonzero_rhs_i32(i32 %a, i32 %b) nounwind {
+; PPC32-LABEL: abd_nonzero_rhs_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: ori 4, 4, 1
+; PPC32-NEXT: neg 5, 4
+; PPC32-NEXT: cmplw 5, 3
+; PPC32-NEXT: blt 0, .LBB27_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: sub 3, 5, 3
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB27_2:
+; PPC32-NEXT: add 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_nonzero_rhs_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: ori 4, 4, 1
+; PPC64-NEXT: neg 5, 4
+; PPC64-NEXT: cmplw 5, 3
+; PPC64-NEXT: blt 0, .LBB27_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 5, 3
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB27_2:
+; PPC64-NEXT: add 3, 3, 4
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+ %b1 = or i32 %b, 1
+ %nb = sub i32 0, %b1
+ %aext = zext i32 %a to i64
+ %bext = zext i32 %nb to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %trunc = trunc i64 %abs to i32
+ ret i32 %trunc
+}
+
+define i64 @abd_nonzero_rhs_i64(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_nonzero_rhs_i64:
+; PPC32: # %bb.0:
+; PPC32-NEXT: ori 6, 6, 1
+; PPC32-NEXT: subfic 6, 6, 0
+; PPC32-NEXT: subfze 5, 5
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: addze. 5, 7
+; PPC32-NEXT: li 5, -1
+; PPC32-NEXT: bc 12, 2, .LBB28_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 5, 0
+; PPC32-NEXT: .LBB28_2:
+; PPC32-NEXT: xor 4, 4, 5
+; PPC32-NEXT: xor 3, 3, 5
+; PPC32-NEXT: subc 4, 4, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_nonzero_rhs_i64:
+; PPC64: # %bb.0:
+; PPC64-NEXT: ori 4, 4, 1
+; PPC64-NEXT: neg 5, 4
+; PPC64-NEXT: cmpld 5, 3
+; PPC64-NEXT: blt 0, .LBB28_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 5, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB28_2:
+; PPC64-NEXT: add 3, 3, 4
+; PPC64-NEXT: blr
+ %b1 = or i64 %b, 1
+ %nb = sub i64 0, %b1
+ %aext = zext i64 %a to i128
+ %bext = zext i64 %nb to i128
+ %sub = sub i128 %aext, %bext
+ %abs = call i128 @llvm.abs.i128(i128 %sub, i1 false)
+ %trunc = trunc i128 %abs to i64
+ ret i64 %trunc
+}
+
+define i32 @abd_nonzero_rhs_i32_select(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: abd_nonzero_rhs_i32_select:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ori 4, 4, 1
+; CHECK-NEXT: neg 5, 4
+; CHECK-NEXT: cmplw 5, 3
+; CHECK-NEXT: blt 0, .LBB29_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sub 3, 5, 3
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB29_2:
+; CHECK-NEXT: add 3, 3, 4
+; CHECK-NEXT: blr
+ %b1 = or i32 %b, 1
+ %nb = sub i32 0, %b1
+ %cmp = icmp ugt i32 %a, %nb
+ %ab = sub i32 %a, %nb
+ %ba = sub i32 %nb, %a
+ %sel = select i1 %cmp, i32 %ab, i32 %ba
+ ret i32 %sel
+}
+
+define i64 @abd_nonzero_rhs_i64_select(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_nonzero_rhs_i64_select:
+; PPC32: # %bb.0:
+; PPC32-NEXT: ori 6, 6, 1
+; PPC32-NEXT: subfic 6, 6, 0
+; PPC32-NEXT: subfze 5, 5
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: addze. 5, 7
+; PPC32-NEXT: li 5, -1
+; PPC32-NEXT: bc 12, 2, .LBB30_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 5, 0
+; PPC32-NEXT: .LBB30_2:
+; PPC32-NEXT: xor 4, 4, 5
+; PPC32-NEXT: xor 3, 3, 5
+; PPC32-NEXT: subc 4, 4, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_nonzero_rhs_i64_select:
+; PPC64: # %bb.0:
+; PPC64-NEXT: ori 4, 4, 1
+; PPC64-NEXT: neg 5, 4
+; PPC64-NEXT: cmpld 5, 3
+; PPC64-NEXT: blt 0, .LBB30_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 5, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB30_2:
+; PPC64-NEXT: add 3, 3, 4
+; PPC64-NEXT: blr
+ %b1 = or i64 %b, 1
+ %nb = sub i64 0, %b1
+ %cmp = icmp ugt i64 %a, %nb
+ %ab = sub i64 %a, %nb
+ %ba = sub i64 %nb, %a
+ %sel = select i1 %cmp, i64 %ab, i64 %ba
+ ret i64 %sel
+}
+
+declare i8 @llvm.abs.i8(i8, i1)
+declare i16 @llvm.abs.i16(i16, i1)
+declare i32 @llvm.abs.i32(i32, i1)
+declare i64 @llvm.abs.i64(i64, i1)
+declare i128 @llvm.abs.i128(i128, i1)
+
+declare i8 @llvm.umax.i8(i8, i8)
+declare i16 @llvm.umax.i16(i16, i16)
+declare i32 @llvm.umax.i32(i32, i32)
+declare i64 @llvm.umax.i64(i64, i64)
+
+declare i8 @llvm.umin.i8(i8, i8)
+declare i16 @llvm.umin.i16(i16, i16)
+declare i32 @llvm.umin.i32(i32, i32)
+declare i64 @llvm.umin.i64(i64, i64)
>From 6bd86346baa683a9593f6609b8a4d622da2e38dc Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sat, 21 Feb 2026 15:27:36 -0500
Subject: [PATCH 2/2] [PowerPC] Custom Lower ABDU using branchless carry
In normal abs, we already do this but with asr 31 instead of sbc, which we can get directly from the subtraction.
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 73 ++++-
llvm/lib/Target/PowerPC/PPCISelLowering.h | 1 +
llvm/test/CodeGen/PowerPC/abdu-neg.ll | 196 +++++--------
llvm/test/CodeGen/PowerPC/abdu.ll | 288 +++++++++-----------
4 files changed, 277 insertions(+), 281 deletions(-)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index bf1755733392c..17037f6525ad2 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -590,10 +590,14 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
// We cannot sextinreg(i1). Expand to shifts.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
- // Custom handling for PowerPC ucmp instruction
+ // Custom handling for ucmp
setOperationAction(ISD::UCMP, MVT::i32, Custom);
setOperationAction(ISD::UCMP, MVT::i64, isPPC64 ? Custom : Expand);
+ // Custom handling for abdu
+ setOperationAction(ISD::ABDU, MVT::i32, Custom);
+ setOperationAction(ISD::ABDU, MVT::i64, isPPC64 ? Custom : Expand);
+
// NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
// SjLj exception handling but a light-weight setjmp/longjmp replacement to
// support continuation, user-level threading, and etc.. As a result, no
@@ -12588,6 +12592,71 @@ SDValue PPCTargetLowering::LowerSADDO(SDValue Op, SelectionDAG &DAG) const {
return DAG.getMergeValues({Sum, OverflowTrunc}, dl);
}
+SDValue PPCTargetLowering::LowerABDU(SDValue Op, SelectionDAG &DAG) const {
+ SDLoc DL(Op);
+ SDValue LHS = Op.getOperand(0);
+ SDValue RHS = Op.getOperand(1);
+ EVT OpVT = LHS.getValueType();
+ EVT VT = Op.getValueType();
+ bool IsNonNegative = DAG.SignBitIsZero(LHS) && DAG.SignBitIsZero(RHS);
+
+ // If the subtract doesn't overflow then just use abs(sub()).
+ if (DAG.willNotOverflowSub(IsNonNegative, LHS, RHS))
+ return DAG.getNode(ISD::ABS, DL, VT,
+ DAG.getNode(ISD::SUB, DL, VT, LHS, RHS));
+
+ if (DAG.willNotOverflowSub(IsNonNegative, RHS, LHS))
+ return DAG.getNode(ISD::ABS, DL, VT,
+ DAG.getNode(ISD::SUB, DL, VT, RHS, LHS));
+
+ // On PPC64, i32 carries are affected by the upper 32 bits of the registers.
+ // We must zero-extend to i64 to ensure the carry reflects the 32-bit unsigned
+ // comparison.
+ if (Subtarget.isPPC64() && OpVT == MVT::i32) {
+ LHS = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, LHS);
+ RHS = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, RHS);
+ OpVT = MVT::i64;
+ }
+
+ // General path: use SUBC (or ADDC when RHS is 0-X) to get
+ // subtract-with-flags, then CMOV to select a-b or b-a. ADDC/SUBC produce the
+ // flags we need.
+ unsigned Opcode = PPCISD::SUBC;
+
+ // Check if RHS is a negation (0 - X). If so, we can use ADDC instead of SUBC:
+ // a - (0 - x) = a + x (mod 2^n)
+ // Same semantics as in LowerCMP; apply same safety checks.
+ if (RHS.getOpcode() == ISD::SUB) {
+ SDValue SubLHS = RHS.getOperand(0);
+ SDValue SubRHS = RHS.getOperand(1);
+
+ if (isNullConstant(SubLHS) && DAG.isKnownNeverZero(SubRHS)) {
+ Opcode = PPCISD::ADDC;
+ RHS = SubRHS;
+ }
+ }
+
+ // Calculate LHS - RHS and capture the carry (CA)
+ SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
+
+ SDValue Res = DAG.getNode(Opcode, DL, VTs, LHS, RHS);
+
+ SDValue CA0 = Res.getValue(1);
+
+ // t2 = A - B + CA0 using SUBE.
+ SDValue ZeroOrNeg1 = DAG.getNode(PPCISD::SUBE, DL, VTs, Res, Res, CA0);
+
+ SDValue Xor = DAG.getNode(ISD::XOR, DL, OpVT, Res, ZeroOrNeg1);
+
+ Res = DAG.getNode(ISD::SUB, DL, OpVT, Xor, ZeroOrNeg1);
+
+ // Truncate back to i32
+ if (OpVT != VT)
+ Res = DAG.getNode(ISD::TRUNCATE, DL, VT, Res);
+
+ return Res;
+}
+
// Lower unsigned 3-way compare producing -1/0/1.
SDValue PPCTargetLowering::LowerUCMP(SDValue Op, SelectionDAG &DAG) const {
SDLoc DL(Op);
@@ -12733,6 +12802,8 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
return LowerADDSUBO_CARRY(Op, DAG);
case ISD::UCMP:
return LowerUCMP(Op, DAG);
+ case ISD::ABDU:
+ return LowerABDU(Op, DAG);
case ISD::STRICT_LRINT:
case ISD::STRICT_LLRINT:
case ISD::STRICT_LROUND:
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index 4e816790b3f02..091605869f58e 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -742,6 +742,7 @@ namespace llvm {
SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerADDSUBO(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerABDU(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerUCMP(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerToLibCall(const char *LibCallName, SDValue Op,
SelectionDAG &DAG) const;
diff --git a/llvm/test/CodeGen/PowerPC/abdu-neg.ll b/llvm/test/CodeGen/PowerPC/abdu-neg.ll
index bfd656bd0f56f..6a6455ec3423b 100644
--- a/llvm/test/CodeGen/PowerPC/abdu-neg.ll
+++ b/llvm/test/CodeGen/PowerPC/abdu-neg.ll
@@ -126,15 +126,10 @@ define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
; PPC32-LABEL: abd_ext_i16_i32:
; PPC32: # %bb.0:
; PPC32-NEXT: clrlwi 3, 3, 16
-; PPC32-NEXT: cmplw 3, 4
-; PPC32-NEXT: bgt 0, .LBB4_2
-; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
; PPC32-NEXT: sub 3, 4, 3
-; PPC32-NEXT: neg 3, 3
-; PPC32-NEXT: blr
-; PPC32-NEXT: .LBB4_2:
-; PPC32-NEXT: sub 3, 3, 4
-; PPC32-NEXT: neg 3, 3
; PPC32-NEXT: blr
;
; PPC64-LABEL: abd_ext_i16_i32:
@@ -187,15 +182,10 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
; PPC32-LABEL: abd_ext_i32:
; PPC32: # %bb.0:
-; PPC32-NEXT: cmplw 3, 4
-; PPC32-NEXT: bgt 0, .LBB6_2
-; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
; PPC32-NEXT: sub 3, 4, 3
-; PPC32-NEXT: neg 3, 3
-; PPC32-NEXT: blr
-; PPC32-NEXT: .LBB6_2:
-; PPC32-NEXT: sub 3, 3, 4
-; PPC32-NEXT: neg 3, 3
; PPC32-NEXT: blr
;
; PPC64-LABEL: abd_ext_i32:
@@ -220,15 +210,10 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
; PPC32-LABEL: abd_ext_i32_i16:
; PPC32: # %bb.0:
; PPC32-NEXT: clrlwi 4, 4, 16
-; PPC32-NEXT: cmplw 3, 4
-; PPC32-NEXT: bgt 0, .LBB7_2
-; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
; PPC32-NEXT: sub 3, 4, 3
-; PPC32-NEXT: neg 3, 3
-; PPC32-NEXT: blr
-; PPC32-NEXT: .LBB7_2:
-; PPC32-NEXT: sub 3, 3, 4
-; PPC32-NEXT: neg 3, 3
; PPC32-NEXT: blr
;
; PPC64-LABEL: abd_ext_i32_i16:
@@ -252,15 +237,10 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
; PPC32-LABEL: abd_ext_i32_undef:
; PPC32: # %bb.0:
-; PPC32-NEXT: cmplw 3, 4
-; PPC32-NEXT: bgt 0, .LBB8_2
-; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
; PPC32-NEXT: sub 3, 4, 3
-; PPC32-NEXT: neg 3, 3
-; PPC32-NEXT: blr
-; PPC32-NEXT: .LBB8_2:
-; PPC32-NEXT: sub 3, 3, 4
-; PPC32-NEXT: neg 3, 3
; PPC32-NEXT: blr
;
; PPC64-LABEL: abd_ext_i32_undef:
@@ -303,15 +283,10 @@ define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
;
; PPC64-LABEL: abd_ext_i64:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmpld 3, 4
-; PPC64-NEXT: bgt 0, .LBB9_2
-; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 4, 3
-; PPC64-NEXT: neg 3, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB9_2:
-; PPC64-NEXT: sub 3, 3, 4
-; PPC64-NEXT: neg 3, 3
; PPC64-NEXT: blr
%aext = zext i64 %a to i128
%bext = zext i64 %b to i128
@@ -344,15 +319,10 @@ define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
;
; PPC64-LABEL: abd_ext_i64_undef:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmpld 3, 4
-; PPC64-NEXT: bgt 0, .LBB10_2
-; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 4, 3
-; PPC64-NEXT: neg 3, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB10_2:
-; PPC64-NEXT: sub 3, 3, 4
-; PPC64-NEXT: neg 3, 3
; PPC64-NEXT: blr
%aext = zext i64 %a to i128
%bext = zext i64 %b to i128
@@ -474,22 +444,12 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_minmax_i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi 4, 4, 24
; CHECK-NEXT: clrlwi 3, 3, 24
-; CHECK-NEXT: cmplw 3, 4
-; CHECK-NEXT: mr 5, 3
-; CHECK-NEXT: bge 0, .LBB13_3
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: ble 0, .LBB13_4
-; CHECK-NEXT: .LBB13_2:
-; CHECK-NEXT: sub 3, 5, 3
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB13_3:
-; CHECK-NEXT: mr 5, 4
-; CHECK-NEXT: bgt 0, .LBB13_2
-; CHECK-NEXT: .LBB13_4:
-; CHECK-NEXT: mr 3, 4
-; CHECK-NEXT: sub 3, 5, 3
+; CHECK-NEXT: clrlwi 4, 4, 24
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: srawi 4, 3, 31
+; CHECK-NEXT: xor 3, 3, 4
+; CHECK-NEXT: sub 3, 4, 3
; CHECK-NEXT: blr
%min = call i8 @llvm.umin.i8(i8 %a, i8 %b)
%max = call i8 @llvm.umax.i8(i8 %a, i8 %b)
@@ -500,22 +460,12 @@ define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_minmax_i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi 4, 4, 16
; CHECK-NEXT: clrlwi 3, 3, 16
-; CHECK-NEXT: cmplw 3, 4
-; CHECK-NEXT: mr 5, 3
-; CHECK-NEXT: bge 0, .LBB14_3
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: ble 0, .LBB14_4
-; CHECK-NEXT: .LBB14_2:
-; CHECK-NEXT: sub 3, 5, 3
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB14_3:
-; CHECK-NEXT: mr 5, 4
-; CHECK-NEXT: bgt 0, .LBB14_2
-; CHECK-NEXT: .LBB14_4:
-; CHECK-NEXT: mr 3, 4
-; CHECK-NEXT: sub 3, 5, 3
+; CHECK-NEXT: clrlwi 4, 4, 16
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: srawi 4, 3, 31
+; CHECK-NEXT: xor 3, 3, 4
+; CHECK-NEXT: sub 3, 4, 3
; CHECK-NEXT: blr
%min = call i16 @llvm.umin.i16(i16 %a, i16 %b)
%max = call i16 @llvm.umax.i16(i16 %a, i16 %b)
@@ -524,23 +474,24 @@ define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
}
define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {
-; CHECK-LABEL: abd_minmax_i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmplw 3, 4
-; CHECK-NEXT: mr 5, 3
-; CHECK-NEXT: bge 0, .LBB15_3
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: ble 0, .LBB15_4
-; CHECK-NEXT: .LBB15_2:
-; CHECK-NEXT: sub 3, 5, 3
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB15_3:
-; CHECK-NEXT: mr 5, 4
-; CHECK-NEXT: bgt 0, .LBB15_2
-; CHECK-NEXT: .LBB15_4:
-; CHECK-NEXT: mr 3, 4
-; CHECK-NEXT: sub 3, 5, 3
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_minmax_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_minmax_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: neg 3, 3
+; PPC64-NEXT: blr
%min = call i32 @llvm.umin.i32(i32 %a, i32 %b)
%max = call i32 @llvm.umax.i32(i32 %a, i32 %b)
%sub = sub i32 %min, %max
@@ -582,20 +533,10 @@ define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {
;
; PPC64-LABEL: abd_minmax_i64:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmpld 3, 4
-; PPC64-NEXT: mr 5, 3
-; PPC64-NEXT: bge 0, .LBB16_3
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: ble 0, .LBB16_4
-; PPC64-NEXT: .LBB16_2:
-; PPC64-NEXT: sub 3, 5, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB16_3:
-; PPC64-NEXT: mr 5, 4
-; PPC64-NEXT: bgt 0, .LBB16_2
-; PPC64-NEXT: .LBB16_4:
-; PPC64-NEXT: mr 3, 4
-; PPC64-NEXT: sub 3, 5, 3
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
; PPC64-NEXT: blr
%min = call i64 @llvm.umin.i64(i64 %a, i64 %b)
%max = call i64 @llvm.umax.i64(i64 %a, i64 %b)
@@ -771,16 +712,24 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
}
define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
-; CHECK-LABEL: abd_cmp_i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmplw 3, 4
-; CHECK-NEXT: bge 0, .LBB20_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB20_2:
-; CHECK-NEXT: sub 3, 4, 3
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_cmp_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_cmp_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: neg 3, 3
+; PPC64-NEXT: blr
%cmp = icmp uge i32 %a, %b
%ab = sub i32 %a, %b
%ba = sub i32 %b, %a
@@ -813,13 +762,10 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
;
; PPC64-LABEL: abd_cmp_i64:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmpld 3, 4
-; PPC64-NEXT: blt 0, .LBB21_2
-; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 4, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB21_2:
-; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: blr
%cmp = icmp ult i64 %a, %b
%ab = sub i64 %a, %b
diff --git a/llvm/test/CodeGen/PowerPC/abdu.ll b/llvm/test/CodeGen/PowerPC/abdu.ll
index b4ae1954d3d59..07baf8a32e6de 100644
--- a/llvm/test/CodeGen/PowerPC/abdu.ll
+++ b/llvm/test/CodeGen/PowerPC/abdu.ll
@@ -97,25 +97,19 @@ define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
; PPC32-LABEL: abd_ext_i16_i32:
; PPC32: # %bb.0:
; PPC32-NEXT: clrlwi 3, 3, 16
-; PPC32-NEXT: cmplw 3, 4
-; PPC32-NEXT: bgt 0, .LBB3_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: sub 3, 4, 3
-; PPC32-NEXT: blr
-; PPC32-NEXT: .LBB3_2:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
; PPC32-NEXT: sub 3, 3, 4
; PPC32-NEXT: blr
;
; PPC64-LABEL: abd_ext_i16_i32:
; PPC64: # %bb.0:
-; PPC64-NEXT: clrlwi 3, 3, 16
-; PPC64-NEXT: cmplw 3, 4
-; PPC64-NEXT: bgt 0, .LBB3_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 4, 3
-; PPC64-NEXT: clrldi 3, 3, 32
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB3_2:
+; PPC64-NEXT: clrldi 3, 3, 48
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: clrldi 3, 3, 32
; PPC64-NEXT: blr
@@ -159,24 +153,19 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
; PPC32-LABEL: abd_ext_i32:
; PPC32: # %bb.0:
-; PPC32-NEXT: cmplw 3, 4
-; PPC32-NEXT: bgt 0, .LBB5_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: sub 3, 4, 3
-; PPC32-NEXT: blr
-; PPC32-NEXT: .LBB5_2:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
; PPC32-NEXT: sub 3, 3, 4
; PPC32-NEXT: blr
;
; PPC64-LABEL: abd_ext_i32:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmplw 3, 4
-; PPC64-NEXT: bgt 0, .LBB5_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 4, 3
; PPC64-NEXT: clrldi 3, 3, 32
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB5_2:
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: clrldi 3, 3, 32
; PPC64-NEXT: blr
@@ -192,25 +181,19 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
; PPC32-LABEL: abd_ext_i32_i16:
; PPC32: # %bb.0:
; PPC32-NEXT: clrlwi 4, 4, 16
-; PPC32-NEXT: cmplw 3, 4
-; PPC32-NEXT: bgt 0, .LBB6_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: sub 3, 4, 3
-; PPC32-NEXT: blr
-; PPC32-NEXT: .LBB6_2:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
; PPC32-NEXT: sub 3, 3, 4
; PPC32-NEXT: blr
;
; PPC64-LABEL: abd_ext_i32_i16:
; PPC64: # %bb.0:
-; PPC64-NEXT: clrlwi 4, 4, 16
-; PPC64-NEXT: cmplw 3, 4
-; PPC64-NEXT: bgt 0, .LBB6_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 4, 3
; PPC64-NEXT: clrldi 3, 3, 32
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB6_2:
+; PPC64-NEXT: clrldi 4, 4, 48
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: clrldi 3, 3, 32
; PPC64-NEXT: blr
@@ -225,24 +208,19 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
; PPC32-LABEL: abd_ext_i32_undef:
; PPC32: # %bb.0:
-; PPC32-NEXT: cmplw 3, 4
-; PPC32-NEXT: bgt 0, .LBB7_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: sub 3, 4, 3
-; PPC32-NEXT: blr
-; PPC32-NEXT: .LBB7_2:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
; PPC32-NEXT: sub 3, 3, 4
; PPC32-NEXT: blr
;
; PPC64-LABEL: abd_ext_i32_undef:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmplw 3, 4
-; PPC64-NEXT: bgt 0, .LBB7_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 4, 3
; PPC64-NEXT: clrldi 3, 3, 32
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB7_2:
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: clrldi 3, 3, 32
; PPC64-NEXT: blr
@@ -274,12 +252,9 @@ define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
;
; PPC64-LABEL: abd_ext_i64:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmpld 3, 4
-; PPC64-NEXT: bgt 0, .LBB8_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 4, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB8_2:
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: blr
%aext = zext i64 %a to i128
@@ -310,12 +285,9 @@ define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
;
; PPC64-LABEL: abd_ext_i64_undef:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmpld 3, 4
-; PPC64-NEXT: bgt 0, .LBB9_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 4, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB9_2:
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: blr
%aext = zext i64 %a to i128
@@ -453,16 +425,23 @@ define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
}
define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {
-; CHECK-LABEL: abd_minmax_i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmplw 3, 4
-; CHECK-NEXT: bgt 0, .LBB14_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: sub 3, 4, 3
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB14_2:
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_minmax_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_minmax_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
%min = call i32 @llvm.umin.i32(i32 %a, i32 %b)
%max = call i32 @llvm.umax.i32(i32 %a, i32 %b)
%sub = sub i32 %max, %min
@@ -489,12 +468,9 @@ define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {
;
; PPC64-LABEL: abd_minmax_i64:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmpld 3, 4
-; PPC64-NEXT: bgt 0, .LBB15_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 4, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB15_2:
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: blr
%min = call i64 @llvm.umin.i64(i64 %a, i64 %b)
@@ -585,16 +561,23 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
}
define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
-; CHECK-LABEL: abd_cmp_i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmplw 3, 4
-; CHECK-NEXT: bgt 0, .LBB19_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: sub 3, 4, 3
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB19_2:
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_cmp_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_cmp_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
%cmp = icmp ult i32 %a, %b
%ab = sub i32 %a, %b
%ba = sub i32 %b, %a
@@ -622,12 +605,9 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
;
; PPC64-LABEL: abd_cmp_i64:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmpld 3, 4
-; PPC64-NEXT: bgt 0, .LBB20_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 4, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB20_2:
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: blr
%cmp = icmp uge i64 %a, %b
@@ -720,16 +700,23 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
}
define i32 @abd_select_i32(i32 %a, i32 %b) nounwind {
-; CHECK-LABEL: abd_select_i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmplw 3, 4
-; CHECK-NEXT: bgt 0, .LBB24_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: sub 3, 4, 3
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB24_2:
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_select_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_select_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
%cmp = icmp ugt i32 %a, %b
%ab = select i1 %cmp, i32 %a, i32 %b
%ba = select i1 %cmp, i32 %b, i32 %a
@@ -757,12 +744,9 @@ define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {
;
; PPC64-LABEL: abd_select_i64:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmpld 3, 4
-; PPC64-NEXT: bgt 0, .LBB25_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 4, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB25_2:
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: blr
%cmp = icmp uge i64 %a, %b
@@ -824,28 +808,22 @@ define i32 @abd_nonzero_rhs_i32(i32 %a, i32 %b) nounwind {
; PPC32-LABEL: abd_nonzero_rhs_i32:
; PPC32: # %bb.0:
; PPC32-NEXT: ori 4, 4, 1
-; PPC32-NEXT: neg 5, 4
-; PPC32-NEXT: cmplw 5, 3
-; PPC32-NEXT: blt 0, .LBB27_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: sub 3, 5, 3
-; PPC32-NEXT: blr
-; PPC32-NEXT: .LBB27_2:
-; PPC32-NEXT: add 3, 3, 4
+; PPC32-NEXT: addc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
; PPC32-NEXT: blr
;
; PPC64-LABEL: abd_nonzero_rhs_i32:
; PPC64: # %bb.0:
; PPC64-NEXT: ori 4, 4, 1
-; PPC64-NEXT: neg 5, 4
-; PPC64-NEXT: cmplw 5, 3
-; PPC64-NEXT: blt 0, .LBB27_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 5, 3
; PPC64-NEXT: clrldi 3, 3, 32
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB27_2:
-; PPC64-NEXT: add 3, 3, 4
+; PPC64-NEXT: neg 4, 4
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: clrldi 3, 3, 32
; PPC64-NEXT: blr
%b1 = or i32 %b, 1
@@ -882,14 +860,10 @@ define i64 @abd_nonzero_rhs_i64(i64 %a, i64 %b) nounwind {
; PPC64-LABEL: abd_nonzero_rhs_i64:
; PPC64: # %bb.0:
; PPC64-NEXT: ori 4, 4, 1
-; PPC64-NEXT: neg 5, 4
-; PPC64-NEXT: cmpld 5, 3
-; PPC64-NEXT: blt 0, .LBB28_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 5, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB28_2:
-; PPC64-NEXT: add 3, 3, 4
+; PPC64-NEXT: addc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: blr
%b1 = or i64 %b, 1
%nb = sub i64 0, %b1
@@ -902,18 +876,26 @@ define i64 @abd_nonzero_rhs_i64(i64 %a, i64 %b) nounwind {
}
define i32 @abd_nonzero_rhs_i32_select(i32 %a, i32 %b) nounwind {
-; CHECK-LABEL: abd_nonzero_rhs_i32_select:
-; CHECK: # %bb.0:
-; CHECK-NEXT: ori 4, 4, 1
-; CHECK-NEXT: neg 5, 4
-; CHECK-NEXT: cmplw 5, 3
-; CHECK-NEXT: blt 0, .LBB29_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: sub 3, 5, 3
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB29_2:
-; CHECK-NEXT: add 3, 3, 4
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_nonzero_rhs_i32_select:
+; PPC32: # %bb.0:
+; PPC32-NEXT: ori 4, 4, 1
+; PPC32-NEXT: addc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_nonzero_rhs_i32_select:
+; PPC64: # %bb.0:
+; PPC64-NEXT: ori 4, 4, 1
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: neg 4, 4
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
%b1 = or i32 %b, 1
%nb = sub i32 0, %b1
%cmp = icmp ugt i32 %a, %nb
@@ -947,14 +929,10 @@ define i64 @abd_nonzero_rhs_i64_select(i64 %a, i64 %b) nounwind {
; PPC64-LABEL: abd_nonzero_rhs_i64_select:
; PPC64: # %bb.0:
; PPC64-NEXT: ori 4, 4, 1
-; PPC64-NEXT: neg 5, 4
-; PPC64-NEXT: cmpld 5, 3
-; PPC64-NEXT: blt 0, .LBB30_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 5, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB30_2:
-; PPC64-NEXT: add 3, 3, 4
+; PPC64-NEXT: addc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: blr
%b1 = or i64 %b, 1
%nb = sub i64 0, %b1
More information about the llvm-commits
mailing list