[llvm] Improved ISD::SRL handling in isKnownToBeAPowerOfTwo (PR #182562)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 21 09:10:16 PST 2026
https://github.com/Iasonaskrpr updated https://github.com/llvm/llvm-project/pull/182562
>From da79801ebe57ba54a226ceb337654613a18c5f1b Mon Sep 17 00:00:00 2001
From: Iasonaskrpr <iaskarapro at gmail.com>
Date: Thu, 19 Feb 2026 21:21:53 +0200
Subject: [PATCH 1/6] Made changes will also add tests
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 581553d41cb6d..ae03ae64c0797 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4723,12 +4723,13 @@ bool SelectionDAG::isKnownToBeAPowerOfTwo(SDValue Val,
case ISD::SRL: {
// A logical right-shift of a constant sign-bit will have exactly
// one bit set.
- auto *C = isConstOrConstSplat(Val.getOperand(0));
+ auto *C = isConstOrConstSplat(Val.getOperand(0), DemandedElts);
if (C && C->getAPIntValue().isSignMask())
return true;
- return isKnownToBeAPowerOfTwo(Val.getOperand(0), /*OrZero=*/false,
- Depth + 1) &&
- isKnownNeverZero(Val, Depth);
+ return (OrZero || isKnownNeverZero(Val, Depth)) &&
+ isKnownToBeAPowerOfTwo(Val.getOperand(0), DemandedElts, OrZero,
+ Depth + 1);
+
}
case ISD::ROTL:
>From adb615f3714088e6850b831fb6fef05a0df90d0e Mon Sep 17 00:00:00 2001
From: Iasonaskrpr <iaskarapro at gmail.com>
Date: Thu, 19 Feb 2026 21:22:32 +0200
Subject: [PATCH 2/6] Formatted changes
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index ae03ae64c0797..35a1b89448f59 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4726,10 +4726,9 @@ bool SelectionDAG::isKnownToBeAPowerOfTwo(SDValue Val,
auto *C = isConstOrConstSplat(Val.getOperand(0), DemandedElts);
if (C && C->getAPIntValue().isSignMask())
return true;
- return (OrZero || isKnownNeverZero(Val, Depth)) &&
- isKnownToBeAPowerOfTwo(Val.getOperand(0), DemandedElts, OrZero,
+ return (OrZero || isKnownNeverZero(Val, Depth)) &&
+ isKnownToBeAPowerOfTwo(Val.getOperand(0), DemandedElts, OrZero,
Depth + 1);
-
}
case ISD::ROTL:
>From 3fc5665b205841666f93dde23e51cff4bbe3769b Mon Sep 17 00:00:00 2001
From: Iasonaskrpr <iaskarapro at gmail.com>
Date: Fri, 20 Feb 2026 20:21:17 +0200
Subject: [PATCH 3/6] Added unit tests
---
.../AArch64/AArch64SelectionDAGTest.cpp | 76 ++++++++++++++++++-
1 file changed, 75 insertions(+), 1 deletion(-)
diff --git a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
index b2b8dfb0c21fc..910baa7073745 100644
--- a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
+++ b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
@@ -918,7 +918,7 @@ TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_Select) {
SDLoc Loc;
auto Cst0 = DAG->getConstant(0, Loc, MVT::i32);
auto Cst3 = DAG->getConstant(3, Loc, MVT::i32);
- auto Cst4 = DAG->getConstant(4, Loc, MVT::i32);
+ auto Cst4 = DAG->getConstant(4, Loc, MVT::i32);
auto CstBig = DAG->getConstant(2 << 17, Loc, MVT::i32);
auto Cond = DAG->getCopyFromReg(DAG->getEntryNode(), Loc, 1, MVT::i1);
@@ -971,6 +971,80 @@ TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_Select) {
DAG->isKnownToBeAPowerOfTwo(VSelect444Big, DemandAll, /*OrZero=*/true));
}
+TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_ISD_SRL) {
+ SDLoc Loc;
+ auto Cst0 = DAG->getConstant(0, Loc, MVT::i32);
+ auto Cst1 = DAG->getConstant(1, Loc, MVT::i32);
+ auto Cst4 = DAG->getConstant(4, Loc, MVT::i32);
+ auto Cst7 = DAG->getConstant(7, Loc, MVT::i32);
+ auto CstBig = DAG->getConstant(2 << 17, Loc, MVT::i32);
+
+ auto SRL40 = DAG->getNode(ISD::SRL, Loc, MVT::i32, Cst4, Cst0);
+ auto SRL41 = DAG->getNode(ISD::SRL, Loc, MVT::i32, Cst4, Cst1);
+ auto SRL44 = DAG->getNode(ISD::SRL, Loc, MVT::i32, Cst4, Cst4);
+ auto SRL71 = DAG->getNode(ISD::SRL, Loc, MVT::i32, Cst7, Cst1);
+ auto SRLBig4 = DAG->getNode(ISD::SRL, Loc, MVT::i32, CstBig, Cst4);
+
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL40));
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL41));
+ EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRL44));
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL44, /*OrZero=*/ true));
+ EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRL71));
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRLBig4));
+
+ auto VecVT = MVT::v2i16;
+ auto Vec00 = DAG->getBuildVector(VecVT, Loc, {Cst0, Cst0});
+ auto Vec04 = DAG->getBuildVector(VecVT, Loc, {Cst0, Cst4});
+ auto Vec11 = DAG->getBuildVector(VecVT, Loc, {Cst1, Cst1});
+ auto Vec44 = DAG->getBuildVector(VecVT, Loc, {Cst4, Cst4});
+ auto Vec74 = DAG->getBuildVector(VecVT, Loc, {Cst7, Cst4});
+ auto Vec4Big = DAG->getBuildVector(VecVT, Loc, {Cst4, CstBig});
+
+ auto SRL4404 = DAG->getNode(ISD::SRL, Loc, VecVT, Vec44, Vec04);
+ auto SRL7411 = DAG->getNode(ISD::SRL, Loc, VecVT, Vec74, Vec11);
+ auto SRL4Big04 = DAG->getNode(ISD::SRL, Loc, VecVT, Vec4Big, Vec04);
+ auto SRL4Big00 = DAG->getNode(ISD::SRL, Loc, VecVT, Vec4Big, Vec00);
+
+ EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRL4404));
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL4404, /*OrZero=*/true));
+ EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRL7411));
+ EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRL7411, /*OrZero=*/true));
+ EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRL4Big00));
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL4Big00, /*OrZero=*/true));
+
+ APInt DemandLo(2, 1);
+ EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRL7411, DemandLo));
+ EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRL7411, DemandLo, /*OrZero=*/true));
+
+ APInt DemandHi(2, 2);
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL7411, DemandHi));
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL7411, DemandHi, /*OrZero=*/true));
+
+ APInt DemandAll(2, 3);
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL4Big04, DemandHi));
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL4Big04, DemandHi, /*OrZero=*/true));
+
+ auto SplatVT = MVT::nxv2i16;
+ auto Splat0 = DAG->getSplat(SplatVT, Loc, Cst0);
+ auto Splat4 = DAG->getSplat(SplatVT, Loc, Cst4);
+ auto SplatBig = DAG->getSplat(SplatVT, Loc, CstBig);
+
+ auto SRLSplatBig0 = DAG->getNode(ISD::SRL, Loc, VecVT, SplatBig, Splat0);
+ auto SRLSplatBig4 = DAG->getNode(ISD::SRL, Loc, VecVT, SplatBig, Splat4);
+ auto SRLSplat44 = DAG->getNode(ISD::SRL, Loc, VecVT, Splat4, Splat4);
+ auto SRLSplat40 = DAG->getNode(ISD::SRL, Loc, VecVT, Splat4, Splat0);
+
+ EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRLSplatBig0));
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRLSplatBig0, /*OrZero=*/true));
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRLSplatBig4));
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRLSplatBig4, /*OrZero=*/true));
+ EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRLSplat44));
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRLSplat44, /*OrZero=*/true));
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRLSplat40));
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRLSplat40, /*OrZero=*/true));
+}
+
+
TEST_F(AArch64SelectionDAGTest, isSplatValue_Fixed_BUILD_VECTOR) {
TargetLowering TL(*TM, *STI);
>From 1a12d544838cb521f0aa37d26fe9c54b59fede13 Mon Sep 17 00:00:00 2001
From: Iasonaskrpr <iaskarapro at gmail.com>
Date: Fri, 20 Feb 2026 20:22:05 +0200
Subject: [PATCH 4/6] Formatted tests
---
.../Target/AArch64/AArch64SelectionDAGTest.cpp | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
index 910baa7073745..705b370206529 100644
--- a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
+++ b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
@@ -918,7 +918,7 @@ TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_Select) {
SDLoc Loc;
auto Cst0 = DAG->getConstant(0, Loc, MVT::i32);
auto Cst3 = DAG->getConstant(3, Loc, MVT::i32);
- auto Cst4 = DAG->getConstant(4, Loc, MVT::i32);
+ auto Cst4 = DAG->getConstant(4, Loc, MVT::i32);
auto CstBig = DAG->getConstant(2 << 17, Loc, MVT::i32);
auto Cond = DAG->getCopyFromReg(DAG->getEntryNode(), Loc, 1, MVT::i1);
@@ -978,7 +978,7 @@ TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_ISD_SRL) {
auto Cst4 = DAG->getConstant(4, Loc, MVT::i32);
auto Cst7 = DAG->getConstant(7, Loc, MVT::i32);
auto CstBig = DAG->getConstant(2 << 17, Loc, MVT::i32);
-
+
auto SRL40 = DAG->getNode(ISD::SRL, Loc, MVT::i32, Cst4, Cst0);
auto SRL41 = DAG->getNode(ISD::SRL, Loc, MVT::i32, Cst4, Cst1);
auto SRL44 = DAG->getNode(ISD::SRL, Loc, MVT::i32, Cst4, Cst4);
@@ -988,7 +988,7 @@ TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_ISD_SRL) {
EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL40));
EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL41));
EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRL44));
- EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL44, /*OrZero=*/ true));
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL44, /*OrZero=*/true));
EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRL71));
EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRLBig4));
@@ -1022,7 +1022,8 @@ TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_ISD_SRL) {
APInt DemandAll(2, 3);
EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL4Big04, DemandHi));
- EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL4Big04, DemandHi, /*OrZero=*/true));
+ EXPECT_TRUE(
+ DAG->isKnownToBeAPowerOfTwo(SRL4Big04, DemandHi, /*OrZero=*/true));
auto SplatVT = MVT::nxv2i16;
auto Splat0 = DAG->getSplat(SplatVT, Loc, Cst0);
@@ -1044,7 +1045,6 @@ TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_ISD_SRL) {
EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRLSplat40, /*OrZero=*/true));
}
-
TEST_F(AArch64SelectionDAGTest, isSplatValue_Fixed_BUILD_VECTOR) {
TargetLowering TL(*TM, *STI);
>From 8abf005fd55d40a55ec5e2697c5bdfd5fe740d79 Mon Sep 17 00:00:00 2001
From: Iasonaskrpr <iaskarapro at gmail.com>
Date: Sat, 21 Feb 2026 18:16:43 +0200
Subject: [PATCH 5/6] Fixed tests
---
.../AArch64/AArch64SelectionDAGTest.cpp | 22 +++++--------------
1 file changed, 6 insertions(+), 16 deletions(-)
diff --git a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
index 705b370206529..d6a122366be3c 100644
--- a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
+++ b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
@@ -979,13 +979,11 @@ TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_ISD_SRL) {
auto Cst7 = DAG->getConstant(7, Loc, MVT::i32);
auto CstBig = DAG->getConstant(2 << 17, Loc, MVT::i32);
- auto SRL40 = DAG->getNode(ISD::SRL, Loc, MVT::i32, Cst4, Cst0);
auto SRL41 = DAG->getNode(ISD::SRL, Loc, MVT::i32, Cst4, Cst1);
auto SRL44 = DAG->getNode(ISD::SRL, Loc, MVT::i32, Cst4, Cst4);
auto SRL71 = DAG->getNode(ISD::SRL, Loc, MVT::i32, Cst7, Cst1);
auto SRLBig4 = DAG->getNode(ISD::SRL, Loc, MVT::i32, CstBig, Cst4);
- EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL40));
EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL41));
EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRL44));
EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL44, /*OrZero=*/true));
@@ -993,7 +991,6 @@ TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_ISD_SRL) {
EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRLBig4));
auto VecVT = MVT::v2i16;
- auto Vec00 = DAG->getBuildVector(VecVT, Loc, {Cst0, Cst0});
auto Vec04 = DAG->getBuildVector(VecVT, Loc, {Cst0, Cst4});
auto Vec11 = DAG->getBuildVector(VecVT, Loc, {Cst1, Cst1});
auto Vec44 = DAG->getBuildVector(VecVT, Loc, {Cst4, Cst4});
@@ -1003,14 +1000,14 @@ TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_ISD_SRL) {
auto SRL4404 = DAG->getNode(ISD::SRL, Loc, VecVT, Vec44, Vec04);
auto SRL7411 = DAG->getNode(ISD::SRL, Loc, VecVT, Vec74, Vec11);
auto SRL4Big04 = DAG->getNode(ISD::SRL, Loc, VecVT, Vec4Big, Vec04);
- auto SRL4Big00 = DAG->getNode(ISD::SRL, Loc, VecVT, Vec4Big, Vec00);
+ auto SRL4411 = DAG->getNode(ISD::SRL, Loc, VecVT, Vec44, Vec11);
EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRL4404));
EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL4404, /*OrZero=*/true));
EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRL7411));
EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRL7411, /*OrZero=*/true));
- EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRL4Big00));
- EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL4Big00, /*OrZero=*/true));
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL4411));
+ EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL4411, /*OrZero=*/true));
APInt DemandLo(2, 1);
EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRL7411, DemandLo));
@@ -1021,28 +1018,21 @@ TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_ISD_SRL) {
EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL7411, DemandHi, /*OrZero=*/true));
APInt DemandAll(2, 3);
- EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRL4Big04, DemandHi));
+ EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRL4Big04, DemandAll));
EXPECT_TRUE(
- DAG->isKnownToBeAPowerOfTwo(SRL4Big04, DemandHi, /*OrZero=*/true));
+ DAG->isKnownToBeAPowerOfTwo(SRL4Big04, DemandAll, /*OrZero=*/true));
auto SplatVT = MVT::nxv2i16;
- auto Splat0 = DAG->getSplat(SplatVT, Loc, Cst0);
auto Splat4 = DAG->getSplat(SplatVT, Loc, Cst4);
auto SplatBig = DAG->getSplat(SplatVT, Loc, CstBig);
- auto SRLSplatBig0 = DAG->getNode(ISD::SRL, Loc, VecVT, SplatBig, Splat0);
auto SRLSplatBig4 = DAG->getNode(ISD::SRL, Loc, VecVT, SplatBig, Splat4);
auto SRLSplat44 = DAG->getNode(ISD::SRL, Loc, VecVT, Splat4, Splat4);
- auto SRLSplat40 = DAG->getNode(ISD::SRL, Loc, VecVT, Splat4, Splat0);
- EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRLSplatBig0));
- EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRLSplatBig0, /*OrZero=*/true));
- EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRLSplatBig4));
+ EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRLSplatBig4));
EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRLSplatBig4, /*OrZero=*/true));
EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRLSplat44));
EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRLSplat44, /*OrZero=*/true));
- EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRLSplat40));
- EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRLSplat40, /*OrZero=*/true));
}
TEST_F(AArch64SelectionDAGTest, isSplatValue_Fixed_BUILD_VECTOR) {
>From f0fd95df161d01bb2aa9991647feee8687a35825 Mon Sep 17 00:00:00 2001
From: Iasonaskrpr <iaskarapro at gmail.com>
Date: Sat, 21 Feb 2026 19:09:56 +0200
Subject: [PATCH 6/6] Fixed test assertion failure
---
llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
index d6a122366be3c..983c4d7f327c5 100644
--- a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
+++ b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
@@ -1026,8 +1026,8 @@ TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_ISD_SRL) {
auto Splat4 = DAG->getSplat(SplatVT, Loc, Cst4);
auto SplatBig = DAG->getSplat(SplatVT, Loc, CstBig);
- auto SRLSplatBig4 = DAG->getNode(ISD::SRL, Loc, VecVT, SplatBig, Splat4);
- auto SRLSplat44 = DAG->getNode(ISD::SRL, Loc, VecVT, Splat4, Splat4);
+ auto SRLSplatBig4 = DAG->getNode(ISD::SRL, Loc, SplatVT, SplatBig, Splat4);
+ auto SRLSplat44 = DAG->getNode(ISD::SRL, Loc, SplatVT, Splat4, Splat4);
EXPECT_FALSE(DAG->isKnownToBeAPowerOfTwo(SRLSplatBig4));
EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SRLSplatBig4, /*OrZero=*/true));
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