[llvm] [DAG] Improved ISD::SHL handling in isKnownToBeAPowerOfTwo (PR #181882)

[Aadarsh Keshri via llvm-commits]

Aadarsh-Keshri wrote:

Regenerated `known-pow2.ll` and removed unnecessary includes from `llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp` that were introduced in this PR.

I'll take a few days off to work myself on proofing/verification and also better understand `isKnownToBeAPowerOfTwo` , `ISD::SHL` and  `computeKnownBits`.
After that, I'll get back to this issue to test `computeKnownBits` implementation as suggested by @arsenm .

https://github.com/llvm/llvm-project/pull/181882