[llvm] [SDPatternMatch] Add `m_ConstInt` overloads with `uint64_t`/`int64_t` operands (PR #182615)

[via llvm-commits]

https://github.com/zGoldthorpe created https://github.com/llvm/llvm-project/pull/182615

Adds overloads
```cpp
auto m_ConstInt(uint64_t &)
auto m_ConstInt(int64_t &)
```
which behaves analogously to `m_ConstInt(APInt &)`, but only matches if the captured integer fits within 64 bits.

>From 387646a7a70ae4b1ca2895dcf8d19e3251290128 Mon Sep 17 00:00:00 2001
From: Zach Goldthorpe <Zach.Goldthorpe at amd.com>
Date: Fri, 20 Feb 2026 16:54:35 -0600
Subject: [PATCH] Added `m_ConstInt` overloads that do not use `APInt`.

---
 llvm/include/llvm/CodeGen/SDPatternMatch.h    | 49 +++++++++++++++++++
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp |  6 +--
 .../CodeGen/SelectionDAGPatternMatchTest.cpp  |  9 +++-
 3 files changed, 60 insertions(+), 4 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/SDPatternMatch.h b/llvm/include/llvm/CodeGen/SDPatternMatch.h
index 7a158dc87f9ae..1579d5fc9c170 100644
--- a/llvm/include/llvm/CodeGen/SDPatternMatch.h
+++ b/llvm/include/llvm/CodeGen/SDPatternMatch.h
@@ -1159,11 +1159,60 @@ struct ConstantInt_match {
                                       BindVal ? *BindVal : Discard);
   }
 };
+
+struct ConstantUnsigned64_match {
+  uint64_t &BindVal;
+
+  explicit ConstantUnsigned64_match(uint64_t &V) : BindVal(V) {}
+
+  template <typename MatchContext>
+  bool match(const MatchContext &Ctx, SDValue N) {
+    APInt V;
+    if (!ConstantInt_match(&V).match(Ctx, N))
+      return false;
+    if (V.getActiveBits() > 64)
+      return false;
+
+    BindVal = V.getZExtValue();
+    return true;
+  }
+};
+
+struct ConstantSigned64_match {
+  int64_t &BindVal;
+
+  explicit ConstantSigned64_match(int64_t &V) : BindVal(V) {}
+
+  template <typename MatchContext>
+  bool match(const MatchContext &Ctx, SDValue N) {
+    APInt V;
+    if (!ConstantInt_match(&V).match(Ctx, N))
+      return false;
+    if (V.getActiveBits() > 64)
+      return false;
+
+    BindVal = V.getSExtValue();
+    return true;
+  }
+};
+
 /// Match any integer constants or splat of an integer constant.
 inline ConstantInt_match m_ConstInt() { return ConstantInt_match(nullptr); }
 /// Match any integer constants or splat of an integer constant; return the
 /// specific constant or constant splat value.
 inline ConstantInt_match m_ConstInt(APInt &V) { return ConstantInt_match(&V); }
+/// Match any integer constants or splat of an integer constant that can fit in
+/// 64 bits; return the specific constant or constant splat value, zero-extended
+/// to 64 bits.
+inline ConstantUnsigned64_match m_ConstInt(uint64_t &V) {
+  return ConstantUnsigned64_match(V);
+}
+/// Match any integer constants or splat of an integer constant that can fit in
+/// 64 bits; return the specific constant or constant splat value, sign-extended
+/// to 64 bits.
+inline ConstantSigned64_match m_ConstInt(int64_t &V) {
+  return ConstantSigned64_match(V);
+}
 
 struct SpecificInt_match {
   APInt IntVal;
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 723f838da1246..04c172b04234b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4079,7 +4079,7 @@ static SDValue foldSubCtlzNot(SDNode *N, SelectionDAG &DAG) {
 
   APInt AndMask;
   APInt XorMask;
-  APInt BitWidthDiff;
+  uint64_t BitWidthDiff;
 
   SDValue CtlzOp;
   SDValue Src;
@@ -4100,9 +4100,9 @@ static SDValue foldSubCtlzNot(SDNode *N, SelectionDAG &DAG) {
                                     m_ConstInt(AndMask)))) {
     // Type Legalisation Pattern:
     // (sub (ctlz (and (xor Op XorMask) AndMask)) BitWidthDiff)
-    if (BitWidthDiff.getZExtValue() >= BitWidth)
+    if (BitWidthDiff >= BitWidth)
       return SDValue();
-    unsigned AndMaskWidth = BitWidth - BitWidthDiff.getZExtValue();
+    unsigned AndMaskWidth = BitWidth - BitWidthDiff;
     if (!(AndMask.isMask(AndMaskWidth) && XorMask.countr_one() >= AndMaskWidth))
       return SDValue();
   } else
diff --git a/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp b/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
index 8f04aa67d729a..72c25ea927078 100644
--- a/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
+++ b/llvm/unittests/CodeGen/SelectionDAGPatternMatchTest.cpp
@@ -616,7 +616,7 @@ TEST_F(SelectionDAGPatternMatchTest, matchUnaryOp) {
 
   SDValue Op0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Int32VT);
   SDValue Op1 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Int64VT);
-  SDValue Op2 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, FloatVT);  
+  SDValue Op2 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, FloatVT);
   SDValue Op3 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 3, Int32VT);
 
   SDValue ZExt = DAG->getNode(ISD::ZERO_EXTEND, DL, Int64VT, Op0);
@@ -775,6 +775,7 @@ TEST_F(SelectionDAGPatternMatchTest, matchConstants) {
 
   SDValue Const3 = DAG->getConstant(3, DL, Int32VT);
   SDValue Const87 = DAG->getConstant(87, DL, Int32VT);
+  SDValue ConstNeg1 = DAG->getConstant(4294967295, DL, Int32VT);
   SDValue Splat = DAG->getSplat(VInt32VT, DL, Arg0);
   SDValue ConstSplat = DAG->getSplat(VInt32VT, DL, Const3);
   SDValue Zero = DAG->getConstant(0, DL, Int32VT);
@@ -790,6 +791,12 @@ TEST_F(SelectionDAGPatternMatchTest, matchConstants) {
   APInt ConstVal;
   EXPECT_TRUE(sd_match(ConstSplat, m_ConstInt(ConstVal)));
   EXPECT_EQ(ConstVal, 3);
+  uint64_t ConstUnsignedInt64Val;
+  EXPECT_TRUE(sd_match(ConstNeg1, m_ConstInt(ConstUnsignedInt64Val)));
+  EXPECT_EQ(ConstUnsignedInt64Val, 4294967295);
+  int64_t ConstSignedInt64Val;
+  EXPECT_TRUE(sd_match(ConstNeg1, m_ConstInt(ConstSignedInt64Val)));
+  EXPECT_EQ(ConstSignedInt64Val, -1);
   EXPECT_FALSE(sd_match(Splat, m_ConstInt()));
 
   EXPECT_TRUE(sd_match(Const87, m_SpecificInt(87)));