[llvm] [NVPTX] Support intrinsics for reserved shared memory special registers (PR #182354)

[via llvm-commits]

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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_80 -mattr=+ptx76 | FileCheck %s
+; RUN: %if ptxas-sm_80 && ptxas-isa-7.6 %{ llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_80 -mattr=+ptx76 | %ptxas-verify -arch=sm_80 %}
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yasmincs wrote:

yes, this passed

https://github.com/llvm/llvm-project/pull/182354