[llvm] [RISCV] Remove srl from (srl (and X, (1 << C)), C) used as czero.eqz/nez condition. (PR #182598)

[Sam Elliott via llvm-commits]

lenary wrote:

> > LGTM - is the hope here that this might be more compressible than the `bexti`?
> 
> Yeah. Does Xqci have any compressible bit test instructions that cover this range?

Yes, we have a `qc.c.bexti rd', shamt` (bit extract) and `qc.c.extu rd, width` (extract from LSB up to width).

https://github.com/llvm/llvm-project/pull/182598