[llvm] [SystemZ][z/OS] Emit prolog size (PR #181850)
Tony Tao via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 20 10:46:09 PST 2026
https://github.com/tltao updated https://github.com/llvm/llvm-project/pull/181850
>From fee299a04c1c13f1934c74a314c4fe7380216966 Mon Sep 17 00:00:00 2001
From: Tony Tao <tonytao at ca.ibm.com>
Date: Fri, 20 Feb 2026 13:44:01 -0500
Subject: [PATCH 1/2] [SystemZ][z/OS] Emit prolog length
The PPA1 contains fields recording the length of the prolog and the
offset to the instruction updating the stack pointer register. The
implementation consists of the following parts:
- the instructions belonging to the prolog are marked with the
FrameSetup flag (including the expansion of the inline stack probe)
- the basic blocks belonging to the prolog are in a fixed
- before emitting the instructions, the first basic blocks of a function
are searched for the last marked instruction. Inside this range, the
instruction which updates the stack pointer can be found, too.
Symbols are attached to both instruction.
- when emitting the PPA1, those symbols are used to calculate the
length and the offset.
---
.../MCTargetDesc/SystemZHLASMAsmStreamer.cpp | 5 +
.../MCTargetDesc/SystemZHLASMAsmStreamer.h | 1 +
llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp | 105 ++++++++-
llvm/lib/Target/SystemZ/SystemZAsmPrinter.h | 2 +
.../Target/SystemZ/SystemZFrameLowering.cpp | 11 +
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 8 +
llvm/lib/Target/SystemZ/SystemZInstrInfo.h | 3 +
llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 7 +
llvm/lib/Target/SystemZ/SystemZLongBranch.cpp | 1 +
llvm/test/CodeGen/SystemZ/call-zos-01.ll | 215 ++++++++++++++++++
llvm/test/CodeGen/SystemZ/call-zos-vararg.ll | 39 ++++
llvm/test/CodeGen/SystemZ/zos-ada.ll | 8 +-
.../CodeGen/SystemZ/zos-prologue-epilog.ll | 117 ++++++----
13 files changed, 476 insertions(+), 46 deletions(-)
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
index 8a559e1ab261b..41cf5a66016b6 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.cpp
@@ -23,6 +23,11 @@ void SystemZHLASMAsmStreamer::visitUsedSymbol(const MCSymbol &Sym) {
Assembler->registerSymbol(Sym);
}
+void SystemZHLASMAsmStreamer::emitRawComment(const Twine &T, bool TabPrefix) {
+ OS << MAI->getCommentString() << T;
+ EmitEOL();
+}
+
void SystemZHLASMAsmStreamer::EmitEOL() {
// Comments are emitted on a new line before the instruction.
if (IsVerboseAsm)
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.h
index 1eb358d45e0f4..2132b7501b312 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.h
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZHLASMAsmStreamer.h
@@ -93,6 +93,7 @@ class SystemZHLASMAsmStreamer final : public MCStreamer {
void emitCodeAlignment(Align Alignment, const MCSubtargetInfo *STI,
unsigned MaxBytesToEmit = 0) override;
+ void emitRawComment(const Twine &T, bool TabPrefix = false) override;
/// Return true if this streamer supports verbose assembly at all.
bool isVerboseAsm() const override { return IsVerboseAsm; }
diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
index 58c8b30f96b4c..f0afc5e49445b 100644
--- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
@@ -768,6 +768,9 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
return;
}
+ case SystemZ::FENCE:
+ OutStreamer->emitRawComment("FENCE");
+ [[fallthrough]];
// EH_SjLj_Setup is a dummy terminator instruction of size 0.
// It is used to handle the clobber register for builtin setjmp.
case SystemZ::EH_SjLj_Setup:
@@ -1378,6 +1381,8 @@ void SystemZAsmPrinter::emitFunctionBodyEnd() {
CurrentFnPPA1Sym = nullptr;
CurrentFnEPMarkerSym = nullptr;
+ EndOfPrologSym = nullptr;
+ StackUpdateSym = nullptr;
}
}
@@ -1561,7 +1566,6 @@ void SystemZAsmPrinter::emitPPA1(MCSymbol *FnEndSym) {
uint8_t FrameReg = TRI->getEncodingValue(TRI->getFrameRegister(*MF));
uint8_t AllocaReg = ZFL->hasFP(*MF) ? FrameReg : 0;
assert(AllocaReg < 16 && "Can't have alloca register larger than 15");
- (void)AllocaReg;
// Build FPR save area offset.
uint32_t FrameAndFPROffset = 0;
@@ -1621,6 +1625,29 @@ void SystemZAsmPrinter::emitPPA1(MCSymbol *FnEndSym) {
OutStreamer->AddComment("Length/4 of Parms");
OutStreamer->emitInt16(
static_cast<uint16_t>(ZFI->getSizeOfFnParams() / 4)); // Parms/4.
+
+ OutStreamer->AddComment("Length/2 of Prolog ");
+ if (EndOfPrologSym)
+ OutStreamer->emitValue(
+ getTargetStreamer()->createWordDiffExpr(OutContext, EndOfPrologSym, CurrentFnSym), 1);
+ else
+ OutStreamer->emitInt8(0);
+
+ OutStreamer->AddComment("Alloca Reg + Offset/2 to SP Update");
+ OutStreamer->AddComment(
+ Twine(" Bit 0-3: Register R").concat(utostr(AllocaReg)).str());
+ OutStreamer->AddComment(" Bit 4-8: Offset ");
+ const MCExpr *AllocaRegExpr =
+ MCConstantExpr::create(AllocaReg << 4, OutContext);
+ if (StackUpdateSym)
+ OutStreamer->emitValue(
+ MCBinaryExpr::createOr(
+ getTargetStreamer()->createWordDiffExpr(OutContext, StackUpdateSym, CurrentFnSym),
+ AllocaRegExpr, OutContext),
+ 1);
+ else
+ OutStreamer->emitValue(AllocaRegExpr, 1);
+
OutStreamer->AddComment("Length of Code");
OutStreamer->emitAbsoluteSymbolDiff(FnEndSym, CurrentFnEPMarkerSym, 4);
@@ -1866,12 +1893,88 @@ const MCExpr *SystemZAsmPrinter::lowerConstant(const Constant *CV,
return AsmPrinter::lowerConstant(CV);
}
+// Determine the end of the prolog and the instructions which updates the stack
+// register, and attach symbols to those instructions.
+static void determinePrologueStackUpdateSym(MachineFunction *MF,
+ MCSymbol *&EndOfPrologSym,
+ MCSymbol *&StackUpdateSym) {
+ EndOfPrologSym = nullptr;
+ StackUpdateSym = nullptr;
+
+
+ // Scan the basic block for the FENCE instruction which marks the end
+ // of the prologue. We know
+ // the prologue is spread at most across the first 3 basic blocks. Also record
+ // the first instruction updating the stack pointer.
+ const SystemZSubtarget &STI = MF->getSubtarget<SystemZSubtarget>();
+ auto &Regs = STI.getSpecialRegisters<SystemZXPLINK64Registers>();
+ MachineInstr *EndOfPrologMI = nullptr;
+ MachineInstr *StackUpdateMI = nullptr;
+ unsigned BBCount = 1;
+
+ for (auto &MBB : *MF) {
+ for (auto &I : MBB) {
+ if (I.getOpcode() == SystemZ::FENCE)
+ EndOfPrologMI = &I;
+ else if (!StackUpdateMI) {
+ unsigned Opcode = I.getOpcode();
+ if ((Opcode == SystemZ::AGHI || Opcode == SystemZ::AGFI) &&
+ I.getOperand(0).getReg() == Regs.getStackPointerRegister())
+ StackUpdateMI = &I;
+ }
+ }
+
+ // Prologue can be a max of 3 BBs if we need to call stack extension code
+ if (EndOfPrologMI || BBCount == 3)
+ break;
+
+ ++BBCount;
+ }
+
+ // Leaf functions do not have a prologue.
+ if (EndOfPrologMI == nullptr)
+ return;
+
+#ifdef EXPENSIVE_CHECKS
+ // Check that the prolog length is valid.
+ auto *TII = STI.getInstrInfo();
+ size_t Size = 0;
+
+ for (auto &MBB : *MF) {
+ bool TerminateLoop = false;
+ for (auto &I : MBB) {
+ Size += TII->getInstSizeInBytes(I);
+ if (&I == EndOfPrologMI) {
+ TerminateLoop = true;
+ break;
+ }
+ }
+ if (TerminateLoop)
+ break;
+ }
+ if (Size > 128)
+ report_fatal_error(Twine(MF->getName()).concat(": Prolog exceeds 128 bytes"));
+#endif
+
+ // Attach a temporary symbol to mark the end of the prolog.
+ EndOfPrologSym = MF->getContext().createTempSymbol("end_of_prologue");
+ EndOfPrologMI->setPostInstrSymbol(*MF, EndOfPrologSym);
+
+ if (StackUpdateMI) {
+ StackUpdateSym = MF->getContext().createTempSymbol("stack_update");
+ StackUpdateMI->setPreInstrSymbol(*MF, StackUpdateSym);
+ }
+}
+
void SystemZAsmPrinter::emitFunctionEntryLabel() {
const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
if (Subtarget.getTargetTriple().isOSzOS()) {
MCContext &OutContext = OutStreamer->getContext();
+ // Add symbols to mark the end of the prolog and the stack updating instr.
+ determinePrologueStackUpdateSym(MF, EndOfPrologSym, StackUpdateSym);
+
// Save information for later use.
std::string N(MF->getFunction().hasName()
? Twine(MF->getFunction().getName()).concat("_").str()
diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
index 0f87eb0307911..94918d35eb318 100644
--- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
+++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.h
@@ -30,6 +30,8 @@ class LLVM_LIBRARY_VISIBILITY SystemZAsmPrinter : public AsmPrinter {
private:
MCSymbol *CurrentFnPPA1Sym; // PPA1 Symbol.
MCSymbol *CurrentFnEPMarkerSym; // Entry Point Marker.
+ MCSymbol *EndOfPrologSym; // Symbol marking the end of the prolog.
+ MCSymbol *StackUpdateSym; // Symbol marking the stack updating instr.
MCSymbol *PPA2Sym;
SystemZTargetStreamer *getTargetStreamer() {
diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
index d4c8f61245ae1..58d01388d8a9a 100644
--- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
@@ -1240,6 +1240,7 @@ bool SystemZXPLINKFrameLowering::restoreCalleeSavedRegisters(
void SystemZXPLINKFrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
+ unsigned InstCount = MBB.size();
const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
SystemZMachineFunctionInfo *ZFI = MF.getInfo<SystemZMachineFunctionInfo>();
MachineBasicBlock::iterator MBBI = MBB.begin();
@@ -1350,6 +1351,16 @@ void SystemZXPLINKFrameLowering::emitPrologue(MachineFunction &MF,
MBB.addLiveIn(Reg);
}
}
+
+ // Check if any new instructions were inserted. If not, it means no there is no
+ // prologue and thus no need for a fence.
+ // The fence is required because moving instructions inside the prologue might
+ // violate some of the rules required to hold for prologues, for example the
+ // maximum lengths of the prologue code. See all rules at
+ // https://www.ibm.com/docs/en/zos/3.1.0?topic=SSLTBW_3.1.0/com.ibm.zos.v3r1.ceev100/cee1v2319.html
+ if (InstCount < MBB.size()) {
+ BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::FENCE));
+ }
}
void SystemZXPLINKFrameLowering::emitEpilogue(MachineFunction &MF,
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 93ce36ab06435..63c00d14e4d35 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -2380,6 +2380,14 @@ SystemZInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
return ArrayRef(TargetFlags);
}
+bool SystemZInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
+ const MachineBasicBlock *MBB,
+ const MachineFunction &MF) const {
+ if (TargetInstrInfo::isSchedulingBoundary(MI, MBB, MF))
+ return true;
+ return MI.getOpcode() == SystemZ::FENCE;
+}
+
MCInst SystemZInstrInfo::getNop() const {
return MCInstBuilder(SystemZ::NOPR).addReg(0);
}
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
index 8e834c74f5031..22079b3709e4c 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
@@ -393,6 +393,9 @@ class SystemZInstrInfo : public SystemZGenInstrInfo {
getSerializableDirectMachineOperandTargetFlags() const override;
MCInst getNop() const override;
+ bool isSchedulingBoundary(const MachineInstr &MI,
+ const MachineBasicBlock *MBB,
+ const MachineFunction &MF) const override;
};
} // end namespace llvm
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 4f75e0132610e..250174fab8b49 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -9,6 +9,13 @@
def IsTargetXPLINK64 : Predicate<"Subtarget->isTargetXPLINK64()">;
def IsTargetELF : Predicate<"Subtarget->isTargetELF()">;
+//===----------------------------------------------------------------------===//
+// Compiler fence
+//===----------------------------------------------------------------------===//
+
+let hasNoSchedulingInfo = 1 in
+ def FENCE : Pseudo<(outs), (ins), []>;
+
//===----------------------------------------------------------------------===//
// Stack allocation
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
index b7a93e7babefe..ce05d7962b492 100644
--- a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
@@ -217,6 +217,7 @@ static unsigned getInstSizeInBytes(const MachineInstr &MI,
MI.isImplicitDef() || MI.getOpcode() == TargetOpcode::MEMBARRIER ||
MI.getOpcode() == TargetOpcode::INIT_UNDEF || MI.isFakeUse() ||
MI.getOpcode() == TargetOpcode::RELOC_NONE ||
+ MI.getOpcode() == SystemZ::FENCE ||
// These have a size that may be zero:
MI.isInlineAsm() || MI.getOpcode() == SystemZ::STACKMAP ||
MI.getOpcode() == SystemZ::PATCHPOINT ||
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-01.ll b/llvm/test/CodeGen/SystemZ/call-zos-01.ll
index 7a2fb3f2dfc49..e4ff63764f653 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-01.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-01.ll
@@ -5,6 +5,20 @@
; CHECK-LABEL: call_char DS 0H
; CHECK: lghi 1,8
define i8 @call_char(){
+; CHECK-LABEL: call_char:
+; CHECK: stmg 6, 7, 1872(4)
+; CHECK-NEXT: @@stack_update0:
+; CHECK-NEXT: aghi 4, -192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue0:
+; CHECK-NEXT: lg 6, 8(5)
+; CHECK-NEXT: lg 5, 0(5)
+; CHECK-NEXT: lghi 1, 8
+; CHECK-NEXT: basr 7, 6
+; CHECK-NEXT: bcr 0, 0
+; CHECK-NEXT: lg 7, 2072(4)
+; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: b 2(7)
%retval = call i8 (i8) @pass_char(i8 8)
ret i8 %retval
}
@@ -12,6 +26,20 @@ define i8 @call_char(){
; CHECK-LABEL: call_short DS 0H
; CHECK: lghi 1,16
define i16 @call_short() {
+; CHECK-LABEL: call_short:
+; CHECK: stmg 6, 7, 1872(4)
+; CHECK-NEXT: @@stack_update1:
+; CHECK-NEXT: aghi 4, -192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue1:
+; CHECK-NEXT: lg 6, 24(5)
+; CHECK-NEXT: lg 5, 16(5)
+; CHECK-NEXT: lghi 1, 16
+; CHECK-NEXT: basr 7, 6
+; CHECK-NEXT: bcr 0, 0
+; CHECK-NEXT: lg 7, 2072(4)
+; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: b 2(7)
entry:
%retval = call i16 (i16) @pass_short(i16 16)
ret i16 %retval
@@ -21,6 +49,21 @@ entry:
; CHECK: lghi 1,32
; CHECK: lghi 2,33
define i32 @call_int() {
+; CHECK-LABEL: call_int:
+; CHECK: stmg 6, 7, 1872(4)
+; CHECK-NEXT: @@stack_update2:
+; CHECK-NEXT: aghi 4, -192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue2:
+; CHECK-NEXT: lg 6, 40(5)
+; CHECK-NEXT: lg 5, 32(5)
+; CHECK-NEXT: lghi 1, 32
+; CHECK-NEXT: lghi 2, 33
+; CHECK-NEXT: basr 7, 6
+; CHECK-NEXT: bcr 0, 0
+; CHECK-NEXT: lg 7, 2072(4)
+; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: b 2(7)
entry:
%retval = call i32 (i32, i32) @pass_int(i32 32, i32 33)
ret i32 %retval
@@ -31,6 +74,22 @@ entry:
; CHECK: lghi 2,65
; CHECK: lghi 3,66
define i64 @call_long() {
+; CHECK-LABEL: call_long:
+; CHECK: stmg 6, 7, 1872(4)
+; CHECK-NEXT: @@stack_update3:
+; CHECK-NEXT: aghi 4, -192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue3:
+; CHECK-NEXT: lg 6, 56(5)
+; CHECK-NEXT: lg 5, 48(5)
+; CHECK-NEXT: lghi 1, 64
+; CHECK-NEXT: lghi 2, 65
+; CHECK-NEXT: lghi 3, 66
+; CHECK-NEXT: basr 7, 6
+; CHECK-NEXT: bcr 0, 0
+; CHECK-NEXT: lg 7, 2072(4)
+; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: b 2(7)
entry:
%retval = call i64 (i64, i64, i64) @pass_long(i64 64, i64 65, i64 66)
ret i64 %retval
@@ -39,6 +98,20 @@ entry:
; CHECK-LABEL: call_ptr DS 0H
; CHECK: lgr 1,2
define i32 @call_ptr(ptr %p1, ptr %p2) {
+; CHECK-LABEL: call_ptr:
+; CHECK: stmg 6, 7, 1872(4)
+; CHECK-NEXT: @@stack_update4:
+; CHECK-NEXT: aghi 4, -192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue4:
+; CHECK-NEXT: lg 6, 72(5)
+; CHECK-NEXT: lg 5, 64(5)
+; CHECK-NEXT: lgr 1, 2
+; CHECK-NEXT: basr 7, 6
+; CHECK-NEXT: bcr 0, 0
+; CHECK-NEXT: lg 7, 2072(4)
+; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: b 2(7)
entry:
%retval = call i32 (ptr) @pass_ptr(ptr %p2)
ret i32 %retval
@@ -49,6 +122,23 @@ entry:
; CHECK: lghi 2,32
; CHECK: lghi 3,16
define i64 @call_integrals() {
+; CHECK-LABEL: call_integrals:
+; CHECK: stmg 6, 7, 1872(4)
+; CHECK-NEXT: @@stack_update5:
+; CHECK-NEXT: aghi 4, -192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue5:
+; CHECK-NEXT: lg 6, 88(5)
+; CHECK-NEXT: lg 5, 80(5)
+; CHECK-NEXT: lghi 1, 64
+; CHECK-NEXT: lghi 2, 32
+; CHECK-NEXT: lghi 3, 16
+; CHECK-NEXT: mvghi 2200(4), 128
+; CHECK-NEXT: basr 7, 6
+; CHECK-NEXT: bcr 0, 0
+; CHECK-NEXT: lg 7, 2072(4)
+; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: b 2(7)
entry:
%retval = call i64 (i64, i32, i16, i64) @pass_integrals0(i64 64, i32 32, i16 16, i64 128)
ret i64 %retval
@@ -57,6 +147,9 @@ entry:
; CHECK-LABEL: pass_char DS 0H
; CHECK: lgr 3,1
define signext i8 @pass_char(i8 signext %arg) {
+; CHECK-LABEL: pass_char:
+; CHECK: lgr 3, 1
+; CHECK-NEXT: b 2(7)
entry:
ret i8 %arg
}
@@ -64,6 +157,9 @@ entry:
; CHECK-LABEL: pass_short DS 0H
; CHECK: lgr 3,1
define signext i16 @pass_short(i16 signext %arg) {
+; CHECK-LABEL: pass_short:
+; CHECK: lgr 3, 1
+; CHECK-NEXT: b 2(7)
entry:
ret i16 %arg
}
@@ -71,6 +167,9 @@ entry:
; CHECK-LABEL: pass_int DS 0H
; CHECK: lgr 3,2
define signext i32 @pass_int(i32 signext %arg0, i32 signext %arg1) {
+; CHECK-LABEL: pass_int:
+; CHECK: lgr 3, 2
+; CHECK-NEXT: b 2(7)
entry:
ret i32 %arg1
}
@@ -79,6 +178,10 @@ entry:
; CHECK: agr 1,2
; CHECK: agr 3,1
define signext i64 @pass_long(i64 signext %arg0, i64 signext %arg1, i64 signext %arg2) {
+; CHECK-LABEL: pass_long:
+; CHECK: agr 1, 2
+; CHECK-NEXT: agr 3, 1
+; CHECK-NEXT: b 2(7)
entry:
%N = add i64 %arg0, %arg1
%M = add i64 %N, %arg2
@@ -89,6 +192,10 @@ entry:
; CHECK: ag 2,2200(4)
; CHECK-NEXT: lgr 3,2
define signext i64 @pass_integrals0(i64 signext %arg0, i32 signext %arg1, i16 signext %arg2, i64 signext %arg3) {
+; CHECK-LABEL: pass_integrals0:
+; CHECK: ag 2, 2200(4)
+; CHECK-NEXT: lgr 3, 2
+; CHECK-NEXT: b 2(7)
entry:
%N = sext i32 %arg1 to i64
%M = add i64 %arg3, %N
@@ -98,6 +205,21 @@ entry:
; CHECK-LABEL: call_float DS 0H
; CHECK: le 0,0({{[0-9]}})
define float @call_float() {
+; CHECK-LABEL: call_float:
+; CHECK: stmg 6, 7, 1872(4)
+; CHECK-NEXT: @@stack_update6:
+; CHECK-NEXT: aghi 4, -192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue6:
+; CHECK-NEXT: lg 6, 104(5)
+; CHECK-NEXT: lg 5, 96(5)
+; CHECK-NEXT: larl 1, @CPI11_0
+; CHECK-NEXT: le 0, 0(1)
+; CHECK-NEXT: basr 7, 6
+; CHECK-NEXT: bcr 0, 0
+; CHECK-NEXT: lg 7, 2072(4)
+; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: b 2(7)
entry:
%ret = call float (float) @pass_float(float 0x400921FB60000000)
ret float %ret
@@ -107,6 +229,21 @@ entry:
; CHECK: larl [[GENREG:[0-9]+]],L#{{CPI[0-9]+_[0-9]+}}
; CHECK-NEXT: ld 0,0([[GENREG]])
define double @call_double() {
+; CHECK-LABEL: call_double:
+; CHECK: stmg 6, 7, 1872(4)
+; CHECK-NEXT: @@stack_update7:
+; CHECK-NEXT: aghi 4, -192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue7:
+; CHECK-NEXT: lg 6, 120(5)
+; CHECK-NEXT: lg 5, 112(5)
+; CHECK-NEXT: larl 1, @CPI12_0
+; CHECK-NEXT: ld 0, 0(1)
+; CHECK-NEXT: basr 7, 6
+; CHECK-NEXT: bcr 0, 0
+; CHECK-NEXT: lg 7, 2072(4)
+; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: b 2(7)
entry:
%ret = call double (double) @pass_double(double 3.141000e+00)
ret double %ret
@@ -117,6 +254,22 @@ entry:
; CHECK-NEXT: ld 0,0([[GENREG]])
; CHECK-NEXT: ld 2,8([[GENREG]])
define fp128 @call_longdouble() {
+; CHECK-LABEL: call_longdouble:
+; CHECK: stmg 6, 7, 1872(4)
+; CHECK-NEXT: @@stack_update8:
+; CHECK-NEXT: aghi 4, -192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue8:
+; CHECK-NEXT: lg 6, 136(5)
+; CHECK-NEXT: lg 5, 128(5)
+; CHECK-NEXT: larl 1, @CPI13_0
+; CHECK-NEXT: ld 0, 0(1)
+; CHECK-NEXT: ld 2, 8(1)
+; CHECK-NEXT: basr 7, 6
+; CHECK-NEXT: bcr 0, 0
+; CHECK-NEXT: lg 7, 2072(4)
+; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: b 2(7)
entry:
%ret = call fp128 (fp128) @pass_longdouble(fp128 0xLE0FC1518450562CD4000921FB5444261)
ret fp128 %ret
@@ -130,6 +283,26 @@ entry:
; CHECK: lxr 0,1
; CHECK: lxr 4,5
define i64 @call_floats0(fp128 %arg0, double %arg1) {
+; CHECK-LABEL: call_floats0:
+; CHECK: stmg 6, 7, 1872(4)
+; CHECK-NEXT: @@stack_update9:
+; CHECK-NEXT: aghi 4, -192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue9:
+; CHECK-NEXT: lg 6, 152(5)
+; CHECK-NEXT: lg 5, 144(5)
+; CHECK-NEXT: larl 1, @CPI14_0
+; CHECK-NEXT: ld 1, 0(1)
+; CHECK-NEXT: ld 3, 8(1)
+; CHECK-NEXT: lxr 5, 0
+; CHECK-NEXT: std 4, 2208(4)
+; CHECK-NEXT: lxr 0, 1
+; CHECK-NEXT: lxr 4, 5
+; CHECK-NEXT: basr 7, 6
+; CHECK-NEXT: bcr 0, 0
+; CHECK-NEXT: lg 7, 2072(4)
+; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: b 2(7)
entry:
%ret = call i64 (fp128, fp128, double) @pass_floats0(fp128 0xLE0FC1518450562CD4000921FB5444261, fp128 %arg0, double %arg1)
ret i64 %ret
@@ -140,6 +313,22 @@ entry:
; CHECK: ldr 0,4
; CHECK: lxr 4,1
define i64 @call_floats1(fp128 %arg0, double %arg1) {
+; CHECK-LABEL: call_floats1:
+; CHECK: stmg 6, 7, 1872(4)
+; CHECK-NEXT: @@stack_update10:
+; CHECK-NEXT: aghi 4, -192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue10:
+; CHECK-NEXT: lg 6, 168(5)
+; CHECK-NEXT: lg 5, 160(5)
+; CHECK-NEXT: lxr 1, 0
+; CHECK-NEXT: ldr 0, 4
+; CHECK-NEXT: lxr 4, 1
+; CHECK-NEXT: basr 7, 6
+; CHECK-NEXT: bcr 0, 0
+; CHECK-NEXT: lg 7, 2072(4)
+; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: b 2(7)
entry:
%ret = call i64 (double, fp128) @pass_floats1(double %arg1, fp128 %arg0)
ret i64 %ret
@@ -149,6 +338,10 @@ entry:
; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
; CHECK: aeb 0,0(1)
define float @pass_float(float %arg) {
+; CHECK-LABEL: pass_float:
+; CHECK: larl 1, @CPI16_0
+; CHECK-NEXT: aeb 0, 0(1)
+; CHECK-NEXT: b 2(7)
entry:
%X = fadd float %arg, 0x400821FB60000000
ret float %X
@@ -158,6 +351,10 @@ entry:
; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
; CHECK: adb 0,0(1)
define double @pass_double(double %arg) {
+; CHECK-LABEL: pass_double:
+; CHECK: larl 1, @CPI17_0
+; CHECK-NEXT: adb 0, 0(1)
+; CHECK-NEXT: b 2(7)
entry:
%X = fadd double %arg, 1.414213e+00
ret double %X
@@ -168,6 +365,11 @@ entry:
; CHECK: lxdb 1,0(1)
; CHECK: axbr 0,1
define fp128 @pass_longdouble(fp128 %arg) {
+; CHECK-LABEL: pass_longdouble:
+; CHECK: larl 1, @CPI18_0
+; CHECK-NEXT: lxdb 1, 0(1)
+; CHECK-NEXT: axbr 0, 1
+; CHECK-NEXT: b 2(7)
entry:
%X = fadd fp128 %arg, 0xL10000000000000004000921FB53C8D4F
ret fp128 %X
@@ -179,6 +381,19 @@ entry:
; CHECK: axbr 1,0
; CHECK: cxbr 1,5
define i64 @pass_floats0(fp128 %arg0, fp128 %arg1, double %arg2) {
+; CHECK-LABEL: pass_floats0:
+; CHECK: lxdb 1, 2208(4)
+; CHECK-NEXT: larl 1, @CPI19_0
+; CHECK-NEXT: ld 5, 0(1)
+; CHECK-NEXT: ld 7, 8(1)
+; CHECK-NEXT: axbr 0, 4
+; CHECK-NEXT: axbr 1, 0
+; CHECK-NEXT: cxbr 1, 5
+; CHECK-NEXT: ipm 0
+; CHECK-NEXT: afi 0, -268435456
+; CHECK-NEXT: sllg 0, 0, 34
+; CHECK-NEXT: srag 3, 0, 63
+; CHECK-NEXT: b 2(7)
%X = fadd fp128 %arg0, %arg1
%arg2_ext = fpext double %arg2 to fp128
%Y = fadd fp128 %X, %arg2_ext
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll b/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
index 147fbe63f5af4..669044d6548cf 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
@@ -3,7 +3,10 @@
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z14 | FileCheck %s -check-prefix=ARCH12
; CHECK-LABEL: call_vararg_double0 DS 0H
; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: @@stack_update0:
; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue0:
; CHECK-NEXT: lg 6,8(5)
; CHECK-NEXT: lg 5,0(5)
; CHECK-NEXT: llihf 3,1074118262
@@ -23,7 +26,10 @@ entry:
; CHECK-LABEL: call_vararg_double1 DS 0H
; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: @@stack_update1:
; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue1:
; CHECK-NEXT: llihf 0,1074118262
; CHECK-NEXT: oilf 0,3367254360
; CHECK-NEXT: lg 6,8(5)
@@ -46,7 +52,10 @@ entry:
; CHECK-LABEL: call_vararg_double2 DS 0H
; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: @@stack_update2:
; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue2:
; CHECK-NEXT: lg 6,24(5)
; CHECK-NEXT: lg 5,16(5)
; CHECK-NEXT: llihf 2,1074118262
@@ -65,7 +74,10 @@ entry:
; CHECK-LABEL: call_vararg_double3 DS 0H
; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: @@stack_update3:
; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue3:
; CHECK-NEXT: llihf 0,1072703839
; CHECK-NEXT: oilf 0,2861204133
; CHECK-NEXT: lg 6,40(5)
@@ -91,7 +103,10 @@ entry:
;; TODO: The extra COPY after LGDR is unnecessary (machine-scheduler introduces the overlap).
; CHECK-LABEL: call_vararg_both0 DS 0H
; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: @@stack_update4:
; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue4:
; CHECK-NEXT: lg 6,40(5)
; CHECK-NEXT: lg 5,32(5)
; CHECK-NEXT: lgdr 0,0
@@ -109,7 +124,10 @@ define i64 @call_vararg_both0(i64 %arg0, double %arg1) {
; CHECK-LABEL: call_vararg_long_double0 DS 0H
; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: @@stack_update5:
; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue5:
; CHECK-NEXT: larl 1,L#CPI5_0
; CHECK-NEXT: ld 0,0(1)
; CHECK-NEXT: ld 2,8(1)
@@ -133,7 +151,10 @@ entry:
; CHECK-LABEL: call_vararg_long_double1 DS 0H
; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: @@stack_update6:
; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue6:
; CHECK-NEXT: lg 6,8(5)
; CHECK-NEXT: lg 5,0(5)
; CHECK-NEXT: lgdr 3,0
@@ -154,7 +175,10 @@ entry:
; CHECK-LABEL: call_vararg_long_double2 DS 0H
; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: @@stack_update7:
; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue7:
; CHECK-NEXT: std 4,2208(4)
; CHECK-NEXT: std 6,2216(4)
; CHECK-NEXT: lg 6,8(5)
@@ -177,7 +201,10 @@ entry:
; CHECK-LABEL: call_vararg_long_double3 DS 0H
; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: @@stack_update8:
; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue8:
; CHECK-NEXT: lg 6,40(5)
; CHECK-NEXT: lg 5,32(5)
; CHECK-NEXT: lgdr 3,2
@@ -256,7 +283,10 @@ define void @call_vec_double_vararg_straddle(<2 x double> %v) {
; CHECK-LABEL: call_vararg_integral0 DS 0H
; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: @@stack_update15:
; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue15:
; CHECK-NEXT: lg 0,2392(4)
; CHECK-NEXT: lg 6,40(5)
; CHECK-NEXT: lg 5,32(5)
@@ -274,7 +304,10 @@ entry:
; CHECK-LABEL: call_vararg_float0 DS 0H
; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: @@stack_update16:
; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue16:
; CHECK-NEXT: lg 6,24(5)
; CHECK-NEXT: lg 5,16(5)
; CHECK-NEXT: lghi 1,1
@@ -292,7 +325,10 @@ entry:
; CHECK-LABEL: call_vararg_float1 DS 0H
; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: @@stack_update17:
; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue17:
; CHECK-NEXT: lg 6,72(5)
; CHECK-NEXT: lg 5,64(5)
; CHECK-NEXT: larl 1,L#CPI17_0
@@ -326,9 +362,12 @@ entry:
;
; CHECK-LABEL: pass_vararg DS 0H
; CHECK: stmg 6,7,1904(4)
+; CHECK-NEXT: @@stack_update18:
; CHECK-NEXT: aghi 4,-160
; CHECK-NEXT: stg 2,2344(4)
; CHECK-NEXT: stg 3,2352(4)
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue18:
; CHECK-NEXT: la 0,2352(4)
; CHECK-NEXT: stg 0,2200(4)
; CHECK-NEXT: lg 3,2344(4)
diff --git a/llvm/test/CodeGen/SystemZ/zos-ada.ll b/llvm/test/CodeGen/SystemZ/zos-ada.ll
index dcdcf2d6c6dc8..8c05c364464e8 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ada.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ada.ll
@@ -2,9 +2,13 @@
;
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z10 | FileCheck %s
+define i64 @caller() {
; CHECK-LABEL: caller DS 0H
; CHECK: stmg 6,8,1872(4)
+; CHECK-NEXT: @@stack_update0:
; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: @@end_of_prologue0:
; CHECK-NEXT: lgr 8,5
; CHECK-NEXT: brasl 7,callee_internal
; CHECK-NEXT: bcr 0,3
@@ -17,7 +21,6 @@
; CHECK-NEXT: lmg 7,8,2072(4)
; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
-define i64 @caller() {
%r1 = call i64 () @callee_internal()
%r2 = call i64 () @callee_external()
%r3 = add i64 %r1, %r2
@@ -25,6 +28,9 @@ define i64 @caller() {
}
define internal i64 @callee_internal() {
+; CHECK-LABEL: callee_internal:
+; CHECK: lghi 3, 10
+; CHECK-NEXT: b 2(7)
ret i64 10
}
diff --git a/llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll b/llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll
index ecf778a36755b..4b634d684cf87 100644
--- a/llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-prologue-epilog.ll
@@ -9,7 +9,10 @@
; CHECK64: stmg 6,7,1872(4)
; stmg instruction's displacement field must be 2064-dsa_size
; as per ABI
-; CHECK64: aghi 4,-192
+; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK64-NEXT: aghi 4,-192
+; CHECK64-NEXT: *FENCE
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK64: lg 7,2072(4)
; CHECK64: aghi 4,192
@@ -26,7 +29,10 @@ define void @func0() {
; Spill all GPR CSRs
; CHECK-LABEL: func1 DS 0H
; CHECK64: stmg 6,15,1904(4)
-; CHECK64: aghi 4,-160
+; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK64-NEXT: aghi 4,-160
+; CHECK64-NEXT: *FENCE
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK64: lmg 7,15,2072(4)
; CHECK64: aghi 4,160
@@ -88,7 +94,10 @@ define void @func1(ptr %ptr) {
; Spill all FPRs and VRs
; CHECK-LABEL: func2 DS 0H
; CHECK64: stmg 6,7,1744(4)
-; CHECK64: aghi 4,-320
+; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK64-NEXT: aghi 4,-320
+; CHECK64-NEXT: *FENCE
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK64: vst 16,{{[0-9]+}}(4),4
; CHECK64: vst 17,{{[0-9]+}}(4),4
; CHECK64: vst 18,{{[0-9]+}}(4),4
@@ -277,8 +286,12 @@ define void @func2(ptr %ptr, ptr %vec_ptr) {
; Big stack frame, force the use of agfi before stmg
; despite not requiring stack extension routine.
-; CHECK64: agfi 4,-1040768
-; CHECK64: stmg 6,7,2064(4)
+; CHECK-LABEL: func3
+; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK64-NEXT: agfi 4,-1040768
+; CHECK64-NEXT: stmg 6,7,2064(4)
+; CHECK64-NEXT: *FENCE
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK64: agfi 4,1040768
define void @func3() {
%arr = alloca [130070 x i64], align 8
@@ -288,14 +301,15 @@ define void @func3() {
; Requires the saving of r4 due to variable sized
; object in stack frame. (Eg: VLA) Sets up frame pointer in r8
+; CHECK-LABEL: func4
; CHECK64: stmg 4,10,1856(4)
-; CHECK64: aghi 4,-192
-; CHECK64: lg 6,40(5)
-; CHECK64: lg 5,32(5)
-; CHECK64: lgr 8,4
-; CHECK64: basr 7,6
-; CHECK64-NEXT: bcr 0,0
+; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK64-NEXT: aghi 4,-192
+; CHECK64-NEXT: lgr 8,4
+; CHECK64-NEXT: *FENCE
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK64: lmg 4,10,2048(4)
+; CHECK64-NEXT: b 2(7)
define i64 @func4(i64 %n) {
%vla = alloca i64, i64 %n, align 8
%call = call i64 @fun2(i64 %n, ptr nonnull %vla, ptr nonnull %vla)
@@ -304,12 +318,15 @@ define i64 @func4(i64 %n) {
; Require saving of r4 and in addition, a displacement large enough
; to force use of agfi before stmg.
+; CHECK-LABEL: func5
; CHECK64: lgr 0,4
-; CHECK64: agfi 4,-1040224
-; CHECK64: stmg 4,10,2048(4)
-; CHECK64: lgr 8,4
-; CHECK64: basr 7,6
-; CHECK64-NEXT: bcr 0,0
+; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK64-NEXT: agfi 4,-1040224
+; CHECK64-NEXT: stmg 4,10,2048(4)
+; CHECK64-NEXT: stg 0,2048(4)
+; CHECK64-NEXT: lgr 8,4
+; CHECK64-NEXT: *FENCE
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK64: lmg 4,10,2048(4)
define i64 @func5(i64 %n) {
%vla = alloca i64, i64 %n, align 8
@@ -320,7 +337,10 @@ define i64 @func5(i64 %n) {
; Require saving of r5, which is not restored.
; CHECK64: stmg 5,9,1864(4)
+; CHECK64: L#stack_update{{[0-9]+}} DS 0H
; CHECK64-NEXT: aghi 4,-192
+; CHECK64-NEXT: *FENCE
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK64: lmg 7,9,2072(4)
; CHECK64-NEXT: aghi 4,192
declare i32 @personality(...)
@@ -340,13 +360,18 @@ bb3:
}
; CHECK-LABEL: large_stack
-; CHECK64: agfi 4,-1048800
+; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK64-NEXT: agfi 4,-1048800
; CHECK64-NEXT: llgt 3,1208
; CHECK64-NEXT: cg 4,64(3)
-; CHECK64-NEXT: jhe
+; CHECK64-NEXT: jhe L#BB7_2
; CHECK64: lg 3,72(3)
-; CHECK64: basr 3,3
-; CHECK64: stmg 6,7,2064(4)
+; CHECK64-NEXT: basr 3,3
+; CHECK64-NEXT: bcr 0,7
+; CHECK64-NEXT: L#BB7_2 DS 0H
+; CHECK64-NEXT: stmg 6,7,2064(4)
+; CHECK64-NEXT: *FENCE
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
define void @large_stack0() {
%arr = alloca [131072 x i64], align 8
call i64 (ptr) @fun1(ptr %arr)
@@ -354,21 +379,21 @@ define void @large_stack0() {
}
; CHECK-LABEL: large_stack1 DS 0H
-; CHECK64: agfi 4,-1048800
-; CHECK64: lgr 0,3
-; CHECK64: llgt 3,1208
-; CHECK64: cg 4,64(3)
-; CHECK64: jhe L#BB8_2
+; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK64-NEXT: agfi 4,-1048800
+; CHECK64-NEXT: lgr 0,3
+; CHECK64-NEXT: llgt 3,1208
+; CHECK64-NEXT: cg 4,64(3)
+; CHECK64-NEXT: jhe L#BB8_2
; CHECK64: lg 3,72(3)
-; CHECK64: basr 3,3
-; CHECK64: bcr 0,7
-; CHECK64: L#BB8_2 DS 0H
-; CHECK64: stmg 6,7,2064(4)
-; CHECK64: lgr 3,0
+; CHECK64-NEXT: basr 3,3
+; CHECK64-NEXT: bcr 0,7
+; CHECK64-NEXT: L#BB8_2 DS 0H
+; CHECK64-NEXT: stmg 6,7,2064(4)
+; CHECK64-NEXT: lgr 3,0
+; CHECK64-NEXT: *FENCE
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
-; CHECK64: L#PPA1_large_stack1_0 DS 0H
-; CHECK64: * Length/4 of Parms
-; CHECK64: DC XL2'0006'
define void @large_stack1(i64 %n1, i64 %n2, i64 %n3) {
%arr = alloca [131072 x i64], align 8
call i64 (ptr, i64, i64, i64) @fun3(ptr %arr,
@@ -380,18 +405,22 @@ define void @large_stack1(i64 %n1, i64 %n2, i64 %n3) {
; CHECK-LABEL: large_stack2
; CHECK64: lgr 0,4
; CHECK64: stg 3,2192(4)
-; CHECK64: agfi 4,-1048800
-; CHECK64: llgt 3,1208
-; CHECK64: cg 4,64(3)
-; CHECK64: jhe L#BB9_2
+; CHECK64: L#stack_update{{[0-9]+}} DS 0H
+; CHECK64-NEXT: agfi 4,-1048800
+; CHECK64-NEXT: llgt 3,1208
+; CHECK64-NEXT: cg 4,64(3)
+; CHECK64-NEXT: jhe L#BB9_2
; CHECK64: lg 3,72(3)
-; CHECK64: basr 3,3
-; CHECK64: bcr 0,7
-; CHECK64: L#BB9_2 DS 0H
-; CHECK64: lgr 3,0
-; CHECK64: lg 3,2192(3)
-; CHECK64: stmg 4,12,2048(4)
-; CHECK64: lgr 8,4
+; CHECK64-NEXT: basr 3,3
+; CHECK64-NEXT: bcr 0,7
+; CHECK64-NEXT: L#BB9_2 DS 0H
+; CHECK64-NEXT: lgr 3,0
+; CHECK64-NEXT: lg 3,2192(3)
+; CHECK64-NEXT: stmg 4,12,2048(4)
+; CHECK64-NEXT: stg 0,2048(4)
+; CHECK64-NEXT: lgr 8,4
+; CHECK64-NEXT: *FENCE
+; CHECK64-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
define void @large_stack2(i64 %n1, i64 %n2, i64 %n3) {
%arr0 = alloca [131072 x i64], align 8
%arr1 = alloca i64, i64 %n1, align 8
>From 77df90b1a240a97ebf7b93446bbb865c2d785a48 Mon Sep 17 00:00:00 2001
From: Tony Tao <tonytao at ca.ibm.com>
Date: Fri, 20 Feb 2026 13:45:52 -0500
Subject: [PATCH 2/2] some test updates
---
.../MCTargetDesc/SystemZTargetStreamer.h | 2 +-
llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp | 17 +-
.../Target/SystemZ/SystemZFrameLowering.cpp | 10 +-
llvm/test/CodeGen/SystemZ/call-zos-01.ll | 430 ++++++++----------
llvm/test/CodeGen/SystemZ/call-zos-vararg.ll | 52 +--
llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll | 3 +
llvm/test/CodeGen/SystemZ/zos-ada.ll | 8 +-
llvm/test/CodeGen/SystemZ/zos-frameaddr.ll | 3 +
llvm/test/CodeGen/SystemZ/zos-ppa1.ll | 164 +++++--
llvm/test/CodeGen/SystemZ/zos-section-1.ll | 40 +-
llvm/test/CodeGen/SystemZ/zos-symbol-2.ll | 2 +-
11 files changed, 370 insertions(+), 361 deletions(-)
diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZTargetStreamer.h b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZTargetStreamer.h
index 4f9a4a0a97ed8..c8b73f3d88efa 100644
--- a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZTargetStreamer.h
+++ b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZTargetStreamer.h
@@ -60,7 +60,7 @@ class SystemZTargetStreamer : public MCTargetStreamer {
virtual const MCExpr *createWordDiffExpr(MCContext &Ctx, const MCSymbol *Hi,
const MCSymbol *Lo) {
- return nullptr;
+ return MCConstantExpr::create(0, Ctx);
}
};
diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
index f0afc5e49445b..18d9850a32b71 100644
--- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
@@ -1628,8 +1628,9 @@ void SystemZAsmPrinter::emitPPA1(MCSymbol *FnEndSym) {
OutStreamer->AddComment("Length/2 of Prolog ");
if (EndOfPrologSym)
- OutStreamer->emitValue(
- getTargetStreamer()->createWordDiffExpr(OutContext, EndOfPrologSym, CurrentFnSym), 1);
+ OutStreamer->emitValue(getTargetStreamer()->createWordDiffExpr(
+ OutContext, EndOfPrologSym, CurrentFnSym),
+ 1);
else
OutStreamer->emitInt8(0);
@@ -1641,9 +1642,9 @@ void SystemZAsmPrinter::emitPPA1(MCSymbol *FnEndSym) {
MCConstantExpr::create(AllocaReg << 4, OutContext);
if (StackUpdateSym)
OutStreamer->emitValue(
- MCBinaryExpr::createOr(
- getTargetStreamer()->createWordDiffExpr(OutContext, StackUpdateSym, CurrentFnSym),
- AllocaRegExpr, OutContext),
+ MCBinaryExpr::createOr(getTargetStreamer()->createWordDiffExpr(
+ OutContext, StackUpdateSym, CurrentFnSym),
+ AllocaRegExpr, OutContext),
1);
else
OutStreamer->emitValue(AllocaRegExpr, 1);
@@ -1901,8 +1902,7 @@ static void determinePrologueStackUpdateSym(MachineFunction *MF,
EndOfPrologSym = nullptr;
StackUpdateSym = nullptr;
-
- // Scan the basic block for the FENCE instruction which marks the end
+ // Scan the basic block for the FENCE instruction which marks the end
// of the prologue. We know
// the prologue is spread at most across the first 3 basic blocks. Also record
// the first instruction updating the stack pointer.
@@ -1953,7 +1953,8 @@ static void determinePrologueStackUpdateSym(MachineFunction *MF,
break;
}
if (Size > 128)
- report_fatal_error(Twine(MF->getName()).concat(": Prolog exceeds 128 bytes"));
+ report_fatal_error(
+ Twine(MF->getName()).concat(": Prolog exceeds 128 bytes"));
#endif
// Attach a temporary symbol to mark the end of the prolog.
diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
index 58d01388d8a9a..d468f3062f821 100644
--- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
@@ -1352,11 +1352,11 @@ void SystemZXPLINKFrameLowering::emitPrologue(MachineFunction &MF,
}
}
- // Check if any new instructions were inserted. If not, it means no there is no
- // prologue and thus no need for a fence.
- // The fence is required because moving instructions inside the prologue might
- // violate some of the rules required to hold for prologues, for example the
- // maximum lengths of the prologue code. See all rules at
+ // Check if any new instructions were inserted. If not, it means no there is
+ // no prologue and thus no need for a fence. The fence is required because
+ // moving instructions inside the prologue might violate some of the rules
+ // required to hold for prologues, for example the maximum lengths of the
+ // prologue code. See all rules at
// https://www.ibm.com/docs/en/zos/3.1.0?topic=SSLTBW_3.1.0/com.ibm.zos.v3r1.ceev100/cee1v2319.html
if (InstCount < MBB.size()) {
BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::FENCE));
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-01.ll b/llvm/test/CodeGen/SystemZ/call-zos-01.ll
index e4ff63764f653..f231f5a0cb8c8 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-01.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-01.ll
@@ -2,185 +2,159 @@
;
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z10 | FileCheck %s
-; CHECK-LABEL: call_char DS 0H
-; CHECK: lghi 1,8
define i8 @call_char(){
-; CHECK-LABEL: call_char:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: @@stack_update0:
-; CHECK-NEXT: aghi 4, -192
+; CHECK-LABEL: call_char DS 0H
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue0:
-; CHECK-NEXT: lg 6, 8(5)
-; CHECK-NEXT: lg 5, 0(5)
-; CHECK-NEXT: lghi 1, 8
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: lg 6,8(5)
+; CHECK-NEXT: lg 5,0(5)
+; CHECK-NEXT: lghi 1,8
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
%retval = call i8 (i8) @pass_char(i8 8)
ret i8 %retval
}
-; CHECK-LABEL: call_short DS 0H
-; CHECK: lghi 1,16
define i16 @call_short() {
-; CHECK-LABEL: call_short:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: @@stack_update1:
-; CHECK-NEXT: aghi 4, -192
+; CHECK-LABEL: call_short DS 0H
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue1:
-; CHECK-NEXT: lg 6, 24(5)
-; CHECK-NEXT: lg 5, 16(5)
-; CHECK-NEXT: lghi 1, 16
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: lg 6,24(5)
+; CHECK-NEXT: lg 5,16(5)
+; CHECK-NEXT: lghi 1,16
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
entry:
%retval = call i16 (i16) @pass_short(i16 16)
ret i16 %retval
}
-; CHECK-LABEL: call_int DS 0H
-; CHECK: lghi 1,32
-; CHECK: lghi 2,33
define i32 @call_int() {
-; CHECK-LABEL: call_int:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: @@stack_update2:
-; CHECK-NEXT: aghi 4, -192
+; CHECK-LABEL: call_int DS 0H
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue2:
-; CHECK-NEXT: lg 6, 40(5)
-; CHECK-NEXT: lg 5, 32(5)
-; CHECK-NEXT: lghi 1, 32
-; CHECK-NEXT: lghi 2, 33
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: lg 6,40(5)
+; CHECK-NEXT: lg 5,32(5)
+; CHECK-NEXT: lghi 1,32
+; CHECK-NEXT: lghi 2,33
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
entry:
%retval = call i32 (i32, i32) @pass_int(i32 32, i32 33)
ret i32 %retval
}
-; CHECK-LABEL: call_long DS 0H
-; CHECK: lghi 1,64
-; CHECK: lghi 2,65
-; CHECK: lghi 3,66
define i64 @call_long() {
-; CHECK-LABEL: call_long:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: @@stack_update3:
-; CHECK-NEXT: aghi 4, -192
+; CHECK-LABEL: call_long DS 0H
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue3:
-; CHECK-NEXT: lg 6, 56(5)
-; CHECK-NEXT: lg 5, 48(5)
-; CHECK-NEXT: lghi 1, 64
-; CHECK-NEXT: lghi 2, 65
-; CHECK-NEXT: lghi 3, 66
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: lg 6,56(5)
+; CHECK-NEXT: lg 5,48(5)
+; CHECK-NEXT: lghi 1,64
+; CHECK-NEXT: lghi 2,65
+; CHECK-NEXT: lghi 3,66
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
entry:
%retval = call i64 (i64, i64, i64) @pass_long(i64 64, i64 65, i64 66)
ret i64 %retval
}
-; CHECK-LABEL: call_ptr DS 0H
-; CHECK: lgr 1,2
define i32 @call_ptr(ptr %p1, ptr %p2) {
-; CHECK-LABEL: call_ptr:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: @@stack_update4:
-; CHECK-NEXT: aghi 4, -192
+; CHECK-LABEL: call_ptr DS 0H
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue4:
-; CHECK-NEXT: lg 6, 72(5)
-; CHECK-NEXT: lg 5, 64(5)
-; CHECK-NEXT: lgr 1, 2
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: lg 6,72(5)
+; CHECK-NEXT: lg 5,64(5)
+; CHECK-NEXT: lgr 1,2
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
entry:
%retval = call i32 (ptr) @pass_ptr(ptr %p2)
ret i32 %retval
}
-; CHECK-LABEL: call_integrals DS 0H
-; CHECK: lghi 1,64
-; CHECK: lghi 2,32
-; CHECK: lghi 3,16
define i64 @call_integrals() {
-; CHECK-LABEL: call_integrals:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: @@stack_update5:
-; CHECK-NEXT: aghi 4, -192
+; CHECK-LABEL: call_integrals DS 0H
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue5:
-; CHECK-NEXT: lg 6, 88(5)
-; CHECK-NEXT: lg 5, 80(5)
-; CHECK-NEXT: lghi 1, 64
-; CHECK-NEXT: lghi 2, 32
-; CHECK-NEXT: lghi 3, 16
-; CHECK-NEXT: mvghi 2200(4), 128
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: lg 6,88(5)
+; CHECK-NEXT: lg 5,80(5)
+; CHECK-NEXT: lghi 1,64
+; CHECK-NEXT: lghi 2,32
+; CHECK-NEXT: lghi 3,16
+; CHECK-NEXT: mvghi 2200(4),128
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
entry:
%retval = call i64 (i64, i32, i16, i64) @pass_integrals0(i64 64, i32 32, i16 16, i64 128)
ret i64 %retval
}
-; CHECK-LABEL: pass_char DS 0H
-; CHECK: lgr 3,1
define signext i8 @pass_char(i8 signext %arg) {
-; CHECK-LABEL: pass_char:
-; CHECK: lgr 3, 1
+; CHECK-LABEL: pass_char DS 0H
+; CHECK: lgr 3,1
; CHECK-NEXT: b 2(7)
entry:
ret i8 %arg
}
-; CHECK-LABEL: pass_short DS 0H
-; CHECK: lgr 3,1
define signext i16 @pass_short(i16 signext %arg) {
-; CHECK-LABEL: pass_short:
-; CHECK: lgr 3, 1
+; CHECK-LABEL: pass_short DS 0H
+; CHECK: lgr 3,1
; CHECK-NEXT: b 2(7)
entry:
ret i16 %arg
}
-; CHECK-LABEL: pass_int DS 0H
-; CHECK: lgr 3,2
define signext i32 @pass_int(i32 signext %arg0, i32 signext %arg1) {
-; CHECK-LABEL: pass_int:
-; CHECK: lgr 3, 2
+; CHECK-LABEL: pass_int DS 0H
+; CHECK: lgr 3,2
; CHECK-NEXT: b 2(7)
entry:
ret i32 %arg1
}
-; CHECK-LABEL: pass_long DS 0H
-; CHECK: agr 1,2
-; CHECK: agr 3,1
define signext i64 @pass_long(i64 signext %arg0, i64 signext %arg1, i64 signext %arg2) {
-; CHECK-LABEL: pass_long:
-; CHECK: agr 1, 2
-; CHECK-NEXT: agr 3, 1
+; CHECK-LABEL: pass_long DS 0H
+; CHECK: agr 1,2
+; CHECK-NEXT: agr 3,1
; CHECK-NEXT: b 2(7)
entry:
%N = add i64 %arg0, %arg1
@@ -188,13 +162,10 @@ entry:
ret i64 %M
}
-; CHECK-LABEL: pass_integrals0 DS 0H
-; CHECK: ag 2,2200(4)
-; CHECK-NEXT: lgr 3,2
define signext i64 @pass_integrals0(i64 signext %arg0, i32 signext %arg1, i16 signext %arg2, i64 signext %arg3) {
-; CHECK-LABEL: pass_integrals0:
-; CHECK: ag 2, 2200(4)
-; CHECK-NEXT: lgr 3, 2
+; CHECK-LABEL: pass_integrals0 DS 0H
+; CHECK: ag 2,2200(4)
+; CHECK-NEXT: lgr 3,2
; CHECK-NEXT: b 2(7)
entry:
%N = sext i32 %arg1 to i64
@@ -202,197 +173,162 @@ entry:
ret i64 %M
}
-; CHECK-LABEL: call_float DS 0H
-; CHECK: le 0,0({{[0-9]}})
define float @call_float() {
-; CHECK-LABEL: call_float:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: @@stack_update6:
-; CHECK-NEXT: aghi 4, -192
+; CHECK-LABEL: call_float DS 0H
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue6:
-; CHECK-NEXT: lg 6, 104(5)
-; CHECK-NEXT: lg 5, 96(5)
-; CHECK-NEXT: larl 1, @CPI11_0
-; CHECK-NEXT: le 0, 0(1)
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: lg 6,104(5)
+; CHECK-NEXT: lg 5,96(5)
+; CHECK-NEXT: larl 1,L#CPI11_0
+; CHECK-NEXT: le 0,0(1)
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
entry:
%ret = call float (float) @pass_float(float 0x400921FB60000000)
ret float %ret
}
-; CHECK-LABEL: call_double DS 0H
-; CHECK: larl [[GENREG:[0-9]+]],L#{{CPI[0-9]+_[0-9]+}}
-; CHECK-NEXT: ld 0,0([[GENREG]])
define double @call_double() {
-; CHECK-LABEL: call_double:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: @@stack_update7:
-; CHECK-NEXT: aghi 4, -192
+; CHECK-LABEL: call_double DS 0H
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue7:
-; CHECK-NEXT: lg 6, 120(5)
-; CHECK-NEXT: lg 5, 112(5)
-; CHECK-NEXT: larl 1, @CPI12_0
-; CHECK-NEXT: ld 0, 0(1)
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: lg 6,120(5)
+; CHECK-NEXT: lg 5,112(5)
+; CHECK-NEXT: larl 1,L#{{CPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: ld 0,0(1)
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
entry:
%ret = call double (double) @pass_double(double 3.141000e+00)
ret double %ret
}
-; CHECK-LABEL: call_longdouble DS 0H
-; CHECK: larl [[GENREG:[0-9]+]],L#{{CPI[0-9]+_[0-9]+}}
-; CHECK-NEXT: ld 0,0([[GENREG]])
-; CHECK-NEXT: ld 2,8([[GENREG]])
define fp128 @call_longdouble() {
-; CHECK-LABEL: call_longdouble:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: @@stack_update8:
-; CHECK-NEXT: aghi 4, -192
+; CHECK-LABEL: call_longdouble DS 0H
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue8:
-; CHECK-NEXT: lg 6, 136(5)
-; CHECK-NEXT: lg 5, 128(5)
-; CHECK-NEXT: larl 1, @CPI13_0
-; CHECK-NEXT: ld 0, 0(1)
-; CHECK-NEXT: ld 2, 8(1)
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: lg 6,136(5)
+; CHECK-NEXT: lg 5,128(5)
+; CHECK-NEXT: larl 1,L#{{CPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: ld 0,0(1)
+; CHECK-NEXT: ld 2,8(1)
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
entry:
%ret = call fp128 (fp128) @pass_longdouble(fp128 0xLE0FC1518450562CD4000921FB5444261)
ret fp128 %ret
}
-; CHECK-LABEL: call_floats0 DS 0H
-; CHECK: larl [[GENREG:[0-9]+]],L#{{CPI[0-9]+_[0-9]+}}
-; CHECK-NEXT: ld 1,0([[GENREG]])
-; CHECK-NEXT: ld 3,8([[GENREG]])
-; CHECK: lxr 5,0
-; CHECK: lxr 0,1
-; CHECK: lxr 4,5
define i64 @call_floats0(fp128 %arg0, double %arg1) {
-; CHECK-LABEL: call_floats0:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: @@stack_update9:
-; CHECK-NEXT: aghi 4, -192
+; CHECK-LABEL: call_floats0 DS 0H
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue9:
-; CHECK-NEXT: lg 6, 152(5)
-; CHECK-NEXT: lg 5, 144(5)
-; CHECK-NEXT: larl 1, @CPI14_0
-; CHECK-NEXT: ld 1, 0(1)
-; CHECK-NEXT: ld 3, 8(1)
-; CHECK-NEXT: lxr 5, 0
-; CHECK-NEXT: std 4, 2208(4)
-; CHECK-NEXT: lxr 0, 1
-; CHECK-NEXT: lxr 4, 5
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: lg 6,152(5)
+; CHECK-NEXT: lg 5,144(5)
+; CHECK-NEXT: larl 1,L#{{CPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: ld 1,0(1)
+; CHECK-NEXT: ld 3,8(1)
+; CHECK-NEXT: lxr 5,0
+; CHECK-NEXT: std 4,2208(4)
+; CHECK-NEXT: lxr 0,1
+; CHECK-NEXT: lxr 4,5
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
entry:
%ret = call i64 (fp128, fp128, double) @pass_floats0(fp128 0xLE0FC1518450562CD4000921FB5444261, fp128 %arg0, double %arg1)
ret i64 %ret
}
-; CHECK-LABEL: call_floats1 DS 0H
-; CHECK: lxr 1,0
-; CHECK: ldr 0,4
-; CHECK: lxr 4,1
define i64 @call_floats1(fp128 %arg0, double %arg1) {
-; CHECK-LABEL: call_floats1:
-; CHECK: stmg 6, 7, 1872(4)
-; CHECK-NEXT: @@stack_update10:
-; CHECK-NEXT: aghi 4, -192
+; CHECK-LABEL: call_floats1 DS 0H
+; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
+; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue10:
-; CHECK-NEXT: lg 6, 168(5)
-; CHECK-NEXT: lg 5, 160(5)
-; CHECK-NEXT: lxr 1, 0
-; CHECK-NEXT: ldr 0, 4
-; CHECK-NEXT: lxr 4, 1
-; CHECK-NEXT: basr 7, 6
-; CHECK-NEXT: bcr 0, 0
-; CHECK-NEXT: lg 7, 2072(4)
-; CHECK-NEXT: aghi 4, 192
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
+; CHECK-NEXT: lg 6,168(5)
+; CHECK-NEXT: lg 5,160(5)
+; CHECK-NEXT: lxr 1,0
+; CHECK-NEXT: ldr 0,4
+; CHECK-NEXT: lxr 4,1
+; CHECK-NEXT: basr 7,6
+; CHECK-NEXT: bcr 0,0
+; CHECK-NEXT: lg 7,2072(4)
+; CHECK-NEXT: aghi 4,192
; CHECK-NEXT: b 2(7)
entry:
%ret = call i64 (double, fp128) @pass_floats1(double %arg1, fp128 %arg0)
ret i64 %ret
}
-; CHECK-LABEL: pass_float DS 0H
-; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
-; CHECK: aeb 0,0(1)
define float @pass_float(float %arg) {
-; CHECK-LABEL: pass_float:
-; CHECK: larl 1, @CPI16_0
-; CHECK-NEXT: aeb 0, 0(1)
+; CHECK-LABEL: pass_float DS 0H
+; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: aeb 0,0(1)
; CHECK-NEXT: b 2(7)
entry:
%X = fadd float %arg, 0x400821FB60000000
ret float %X
}
-; CHECK-LABEL: pass_double DS 0H
-; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
-; CHECK: adb 0,0(1)
define double @pass_double(double %arg) {
-; CHECK-LABEL: pass_double:
-; CHECK: larl 1, @CPI17_0
-; CHECK-NEXT: adb 0, 0(1)
+; CHECK-LABEL: pass_double DS 0H
+; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: adb 0,0(1)
; CHECK-NEXT: b 2(7)
entry:
%X = fadd double %arg, 1.414213e+00
ret double %X
}
-; CHECK-LABEL: pass_longdouble DS 0H
-; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
-; CHECK: lxdb 1,0(1)
-; CHECK: axbr 0,1
define fp128 @pass_longdouble(fp128 %arg) {
-; CHECK-LABEL: pass_longdouble:
-; CHECK: larl 1, @CPI18_0
-; CHECK-NEXT: lxdb 1, 0(1)
-; CHECK-NEXT: axbr 0, 1
+; CHECK-LABEL: pass_longdouble DS 0H
+; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: lxdb 1,0(1)
+; CHECK-NEXT: axbr 0,1
; CHECK-NEXT: b 2(7)
entry:
%X = fadd fp128 %arg, 0xL10000000000000004000921FB53C8D4F
ret fp128 %X
}
-; CHECK-LABEL: pass_floats0 DS 0H
-; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
-; CHECK: axbr 0,4
-; CHECK: axbr 1,0
-; CHECK: cxbr 1,5
define i64 @pass_floats0(fp128 %arg0, fp128 %arg1, double %arg2) {
-; CHECK-LABEL: pass_floats0:
-; CHECK: lxdb 1, 2208(4)
-; CHECK-NEXT: larl 1, @CPI19_0
-; CHECK-NEXT: ld 5, 0(1)
-; CHECK-NEXT: ld 7, 8(1)
-; CHECK-NEXT: axbr 0, 4
-; CHECK-NEXT: axbr 1, 0
-; CHECK-NEXT: cxbr 1, 5
+; CHECK-LABEL: pass_floats0 DS 0H
+; CHECK: lxdb 1,2208(4)
+; CHECK: larl 1,L#{{CPI[0-9]+_[0-9]+}}
+; CHECK-NEXT: ld 5,0(1)
+; CHECK-NEXT: ld 7,8(1)
+; CHECK-NEXT: axbr 0,4
+; CHECK-NEXT: axbr 1,0
+; CHECK-NEXT: cxbr 1,5
; CHECK-NEXT: ipm 0
-; CHECK-NEXT: afi 0, -268435456
-; CHECK-NEXT: sllg 0, 0, 34
-; CHECK-NEXT: srag 3, 0, 63
+; CHECK-NEXT: afi 0,-268435456
+; CHECK-NEXT: sllg 0,0,34
+; CHECK-NEXT: srag 3,0,63
; CHECK-NEXT: b 2(7)
%X = fadd fp128 %arg0, %arg1
%arg2_ext = fpext double %arg2 to fp128
diff --git a/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll b/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
index 669044d6548cf..3bcc583adec7f 100644
--- a/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
+++ b/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
@@ -3,10 +3,10 @@
; RUN: llc < %s -mtriple=s390x-ibm-zos -mcpu=z14 | FileCheck %s -check-prefix=ARCH12
; CHECK-LABEL: call_vararg_double0 DS 0H
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: @@stack_update0:
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue0:
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK-NEXT: lg 6,8(5)
; CHECK-NEXT: lg 5,0(5)
; CHECK-NEXT: llihf 3,1074118262
@@ -26,10 +26,10 @@ entry:
; CHECK-LABEL: call_vararg_double1 DS 0H
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: @@stack_update1:
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue1:
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK-NEXT: llihf 0,1074118262
; CHECK-NEXT: oilf 0,3367254360
; CHECK-NEXT: lg 6,8(5)
@@ -52,10 +52,10 @@ entry:
; CHECK-LABEL: call_vararg_double2 DS 0H
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: @@stack_update2:
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue2:
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK-NEXT: lg 6,24(5)
; CHECK-NEXT: lg 5,16(5)
; CHECK-NEXT: llihf 2,1074118262
@@ -74,10 +74,10 @@ entry:
; CHECK-LABEL: call_vararg_double3 DS 0H
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: @@stack_update3:
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue3:
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK-NEXT: llihf 0,1072703839
; CHECK-NEXT: oilf 0,2861204133
; CHECK-NEXT: lg 6,40(5)
@@ -103,10 +103,10 @@ entry:
;; TODO: The extra COPY after LGDR is unnecessary (machine-scheduler introduces the overlap).
; CHECK-LABEL: call_vararg_both0 DS 0H
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: @@stack_update4:
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue4:
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK-NEXT: lg 6,40(5)
; CHECK-NEXT: lg 5,32(5)
; CHECK-NEXT: lgdr 0,0
@@ -124,10 +124,10 @@ define i64 @call_vararg_both0(i64 %arg0, double %arg1) {
; CHECK-LABEL: call_vararg_long_double0 DS 0H
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: @@stack_update5:
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue5:
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK-NEXT: larl 1,L#CPI5_0
; CHECK-NEXT: ld 0,0(1)
; CHECK-NEXT: ld 2,8(1)
@@ -151,10 +151,10 @@ entry:
; CHECK-LABEL: call_vararg_long_double1 DS 0H
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: @@stack_update6:
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue6:
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK-NEXT: lg 6,8(5)
; CHECK-NEXT: lg 5,0(5)
; CHECK-NEXT: lgdr 3,0
@@ -175,10 +175,10 @@ entry:
; CHECK-LABEL: call_vararg_long_double2 DS 0H
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: @@stack_update7:
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue7:
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK-NEXT: std 4,2208(4)
; CHECK-NEXT: std 6,2216(4)
; CHECK-NEXT: lg 6,8(5)
@@ -201,10 +201,10 @@ entry:
; CHECK-LABEL: call_vararg_long_double3 DS 0H
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: @@stack_update8:
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue8:
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK-NEXT: lg 6,40(5)
; CHECK-NEXT: lg 5,32(5)
; CHECK-NEXT: lgdr 3,2
@@ -283,10 +283,10 @@ define void @call_vec_double_vararg_straddle(<2 x double> %v) {
; CHECK-LABEL: call_vararg_integral0 DS 0H
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: @@stack_update15:
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue15:
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK-NEXT: lg 0,2392(4)
; CHECK-NEXT: lg 6,40(5)
; CHECK-NEXT: lg 5,32(5)
@@ -304,10 +304,10 @@ entry:
; CHECK-LABEL: call_vararg_float0 DS 0H
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: @@stack_update16:
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue16:
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK-NEXT: lg 6,24(5)
; CHECK-NEXT: lg 5,16(5)
; CHECK-NEXT: lghi 1,1
@@ -325,10 +325,10 @@ entry:
; CHECK-LABEL: call_vararg_float1 DS 0H
; CHECK: stmg 6,7,1872(4)
-; CHECK-NEXT: @@stack_update17:
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue17:
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK-NEXT: lg 6,72(5)
; CHECK-NEXT: lg 5,64(5)
; CHECK-NEXT: larl 1,L#CPI17_0
@@ -362,12 +362,12 @@ entry:
;
; CHECK-LABEL: pass_vararg DS 0H
; CHECK: stmg 6,7,1904(4)
-; CHECK-NEXT: @@stack_update18:
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
; CHECK-NEXT: aghi 4,-160
; CHECK-NEXT: stg 2,2344(4)
; CHECK-NEXT: stg 3,2352(4)
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue18:
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK-NEXT: la 0,2352(4)
; CHECK-NEXT: stg 0,2200(4)
; CHECK-NEXT: lg 3,2344(4)
diff --git a/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll b/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
index ddd6850e54406..cae54638c3191 100644
--- a/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
+++ b/llvm/test/CodeGen/SystemZ/mixed-ptr-sizes.ll
@@ -298,7 +298,10 @@ define void @spill_ptr32_args_to_registers(i8 addrspace(1)* %p) {
entry:
; CHECK-LABEL: spill_ptr32_args_to_registers DS 0H
; CHECK: stmg 6,7,1872(4)
+; CHECK-NEXT: L#stack_update7 DS 0H
; CHECK-NEXT: aghi 4,-192
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: L#end_of_prologue7 DS 0H
; CHECK-NEXT: lgr 2,1
; CHECK-NEXT: lg 6,24(5)
; CHECK-NEXT: lg 5,16(5)
diff --git a/llvm/test/CodeGen/SystemZ/zos-ada.ll b/llvm/test/CodeGen/SystemZ/zos-ada.ll
index 8c05c364464e8..fb99f318b57f9 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ada.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ada.ll
@@ -5,10 +5,10 @@
define i64 @caller() {
; CHECK-LABEL: caller DS 0H
; CHECK: stmg 6,8,1872(4)
-; CHECK-NEXT: @@stack_update0:
+; CHECK-NEXT: L#stack_update{{[0-9]+}} DS 0H
; CHECK-NEXT: aghi 4,-192
; CHECK-NEXT: *FENCE
-; CHECK-NEXT: @@end_of_prologue0:
+; CHECK-NEXT: L#end_of_prologue{{[0-9]+}} DS 0H
; CHECK-NEXT: lgr 8,5
; CHECK-NEXT: brasl 7,callee_internal
; CHECK-NEXT: bcr 0,3
@@ -28,8 +28,8 @@ define i64 @caller() {
}
define internal i64 @callee_internal() {
-; CHECK-LABEL: callee_internal:
-; CHECK: lghi 3, 10
+; CHECK-LABEL: callee_internal DS 0H
+; CHECK: lghi 3,10
; CHECK-NEXT: b 2(7)
ret i64 10
}
diff --git a/llvm/test/CodeGen/SystemZ/zos-frameaddr.ll b/llvm/test/CodeGen/SystemZ/zos-frameaddr.ll
index ae5f71e31fc50..66177d56eb6d5 100644
--- a/llvm/test/CodeGen/SystemZ/zos-frameaddr.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-frameaddr.ll
@@ -17,7 +17,10 @@ entry:
define ptr @fp0f() nounwind {
; CHECK-LABEL: fp0f DS 0H
; CHECK: stmg 6,7,1904(4)
+; CHECK-NEXT: L#stack_update0 DS 0H
; CHECK-NEXT: aghi 4,-160
+; CHECK-NEXT: *FENCE
+; CHECK-NEXT: L#end_of_prologue0 DS 0H
; CHECK-NEXT: la 3,2048(4)
; CHECK-NEXT: lg 7,2072(4)
; CHECK-NEXT: aghi 4,160
diff --git a/llvm/test/CodeGen/SystemZ/zos-ppa1.ll b/llvm/test/CodeGen/SystemZ/zos-ppa1.ll
index f73edfc6ba42e..34742bf9dc083 100644
--- a/llvm/test/CodeGen/SystemZ/zos-ppa1.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-ppa1.ll
@@ -1,54 +1,120 @@
; RUN: llc -mtriple s390x-ibm-zos < %s | FileCheck %s
+define i32 @leaf(i32 signext %arg) {
; CHECK: * XPLINK Routine Layout Entry
-; CHECK: L#EPM_void_test_0 DS 0H
-; CHECK: * Eyecatcher 0x00C300C500C500
-; CHECK: DC XL7'00C300C500C500'
-; CHECK: * Mark Type C'1'
-; CHECK: DC XL1'F1'
-; CHECK: * Offset to PPA1
-; CHECK: DC AD(L#PPA1_void_test_0-L#EPM_void_test_0)
-; CHECK: * DSA Size 0x0
-; CHECK: * Entry Flags
-; CHECK: * Bit 1: 1 = Leaf function
-; CHECK: * Bit 2: 0 = Does not use alloca
-; CHECK: DC XL4'00000008'
-; CHECK: ENTRY void_test
-; CHECK: L#func_end0 DS 0H
-; CHECK: stdin#C CSECT
-; CHECK: C_CODE64 CATTR
-; CHECK: * PPA1
-; CHECK: L#PPA1_void_test_0 DS 0H
-; CHECK: * Version
-; CHECK: DC XL1'02'
-; CHECK: * LE Signature X'CE'
-; CHECK: DC XL1'CE'
-; CHECK: * Saved GPR Mask
-; CHECK: DC XL2'0000'
-; CHECK: * Offset to PPA2
-; CHECK: DC AD(L#PPA2-L#PPA1_void_test_0)
-; CHECK: * PPA1 Flags 1
-; CHECK: * Bit 0: 1 = 64-bit DSA
-; CHECK: DC XL1'80'
-; CHECK: * PPA1 Flags 2
-; CHECK: * Bit 0: 1 = External procedure
-; CHECK: * Bit 3: 0 = STACKPROTECT is not enabled
-; CHECK: DC XL1'80'
-; CHECK: * PPA1 Flags 3
-; CHECK: DC XL1'00'
-; CHECK: * PPA1 Flags 4
-; CHECK: * Bit 7: 1 = Name Length and Name
-; CHECK: DC XL1'81'
-; CHECK: * Length/4 of Parms
-; CHECK: DC XL2'0000'
-; CHECK: * Length of Code
-; CHECK: DC AD(L#func_end0-L#EPM_void_test_0)
-; CHECK: * Length of Name
-; CHECK: DC XL2'0009'
-; CHECK: * Name of Function
-; CHECK: DC XL9'A59689846DA385A2A3'
-; CHECK: DC AD(L#EPM_void_test_0-L#PPA1_void_test_0)
-define void @void_test() {
+; CHECK-NEXT: L#EPM_leaf_0 DS 0H
+; CHECK-NEXT: * Eyecatcher 0x00C300C500C500
+; CHECK-NEXT: DC XL7'00C300C500C500'
+; CHECK-NEXT: * Mark Type C'1'
+; CHECK-NEXT: DC XL1'F1'
+; CHECK-NEXT: * Offset to PPA1
+; CHECK-NEXT: DC AD(L#PPA1_leaf_0-L#EPM_leaf_0)
+; CHECK-NEXT: * DSA Size 0x0
+; CHECK-NEXT: * Entry Flags
+; CHECK-NEXT: * Bit 1: 1 = Leaf function
+; CHECK-NEXT: * Bit 2: 0 = Does not use alloca
+; CHECK-NEXT: DC XL4'00000008'
+; --- Code ---
+; CHECK: stdin#C CSECT
+; CHECK-NEXT: C_CODE64 CATTR
+; CHECK-NEXT: * PPA1
+; CHECK-NEXT: L#PPA1_leaf_0 DS 0H
+; CHECK-NEXT: * Version
+; CHECK-NEXT: DC XL1'02'
+; CHECK-NEXT: * LE Signature X'CE'
+; CHECK-NEXT: DC XL1'CE'
+; CHECK-NEXT: * Saved GPR Mask
+; CHECK-NEXT: DC XL2'0000'
+; CHECK-NEXT: * Offset to PPA2
+; CHECK-NEXT: DC AD(L#PPA2-L#PPA1_leaf_0)
+; CHECK-NEXT: * PPA1 Flags 1
+; CHECK-NEXT: * Bit 0: 1 = 64-bit DSA
+; CHECK-NEXT: DC XL1'80'
+; CHECK-NEXT: * PPA1 Flags 2
+; CHECK-NEXT: * Bit 0: 1 = External procedure
+; CHECK-NEXT: * Bit 3: 0 = STACKPROTECT is not enabled
+; CHECK-NEXT: DC XL1'80'
+; CHECK-NEXT: * PPA1 Flags 3
+; CHECK-NEXT: DC XL1'00'
+; CHECK-NEXT: * PPA1 Flags 4
+; CHECK-NEXT: * Bit 7: 1 = Name Length and Name
+; CHECK-NEXT: DC XL1'81'
+; CHECK-NEXT: * Length/4 of Parms
+; CHECK-NEXT: DC XL2'0002'
+; CHECK-NEXT: * Length/2 of Prolog
+; CHECK-NEXT: DC XL1'00'
+; CHECK-NEXT: * Alloca Reg + Offset/2 to SP Update
+; CHECK-NEXT: * Bit 0-3: Register R0
+; CHECK-NEXT: * Bit 4-8: Offset
+; CHECK-NEXT: DC XL1'0'
+; CHECK-NEXT: * Length of Code
+; CHECK-NEXT: DC AD(L#func_end0-L#EPM_leaf_0)
+; CHECK-NEXT: * Length of Name
+; CHECK-NEXT: DC XL2'0004'
+; CHECK-NEXT: * Name of Function
+; CHECK-NEXT: DC XL4'93858186'
+; CHECK-NEXT: DC AD(L#EPM_leaf_0-L#PPA1_leaf_0)
entry:
- ret void
+ %sum = add i32 1, %arg
+ ret i32 %sum
+}
+
+define i32 @nonleaf(i32 signext %arg) {
+; CHECK: L#EPM_nonleaf_0 DS 0H
+; CHECK-NEXT: * Eyecatcher 0x00C300C500C500
+; CHECK-NEXT: DC XL7'00C300C500C500'
+; CHECK-NEXT: * Mark Type C'1'
+; CHECK-NEXT: DC XL1'F1'
+; CHECK-NEXT: * Offset to PPA1
+; CHECK-NEXT: DC AD(L#PPA1_nonleaf_0-L#EPM_nonleaf_0)
+; CHECK-NEXT: * DSA Size 0xc0
+; CHECK-NEXT: * Entry Flags
+; CHECK-NEXT: * Bit 1: 0 = Non-leaf function
+; CHECK-NEXT: * Bit 2: 0 = Does not use alloca
+; CHECK-NEXT: DC XL4'000000C0'
+; --- Code ---
+; CHECK: stdin#C CSECT
+; CHECK-NEXT: C_CODE64 CATTR
+; CHECK-NEXT: * PPA1
+; CHECK-NEXT: L#PPA1_nonleaf_0 DS 0H
+; CHECK-NEXT: * Version
+; CHECK-NEXT: DC XL1'02'
+; CHECK-NEXT: * LE Signature X'CE'
+; CHECK-NEXT: DC XL1'CE'
+; CHECK-NEXT: * Saved GPR Mask
+; CHECK-NEXT: DC XL2'0300'
+; CHECK-NEXT: * Offset to PPA2
+; CHECK-NEXT: DC AD(L#PPA2-L#PPA1_nonleaf_0)
+; CHECK-NEXT: * PPA1 Flags 1
+; CHECK-NEXT: * Bit 0: 1 = 64-bit DSA
+; CHECK-NEXT: DC XL1'80'
+; CHECK-NEXT: * PPA1 Flags 2
+; CHECK-NEXT: * Bit 0: 1 = External procedure
+; CHECK-NEXT: * Bit 3: 0 = STACKPROTECT is not enabled
+; CHECK-NEXT: DC XL1'80'
+; CHECK-NEXT: * PPA1 Flags 3
+; CHECK-NEXT: DC XL1'00'
+; CHECK-NEXT: * PPA1 Flags 4
+; CHECK-NEXT: * Bit 7: 1 = Name Length and Name
+; CHECK-NEXT: DC XL1'81'
+; CHECK-NEXT: * Length/4 of Parms
+; CHECK-NEXT: DC XL2'0002'
+; CHECK-NEXT: L#tmp0 EQU L#end_of_prologue0-nonleaf
+; CHECK-NEXT: * Length/2 of Prolog
+; CHECK-NEXT: DC AD(L#tmp0/2)
+; CHECK-NEXT: L#tmp1 EQU L#stack_update0-nonleaf
+; CHECK-NEXT: * Alloca Reg + Offset/2 to SP Update
+; CHECK-NEXT: * Bit 0-3: Register R0
+; CHECK-NEXT: * Bit 4-8: Offset
+; CHECK-NEXT: DC AD(L#tmp1/2),XL1'0'
+; CHECK-NEXT: * Length of Code
+; CHECK-NEXT: DC AD(L#func_end2-L#EPM_nonleaf_0)
+; CHECK-NEXT: * Length of Name
+; CHECK-NEXT: DC XL2'0007'
+; CHECK-NEXT: * Name of Function
+; CHECK-NEXT: DC XL7'95969593858186'
+; CHECK-NEXT: DC AD(L#EPM_nonleaf_0-L#PPA1_nonleaf_0)
+entry:
+ %res = call i32 @leaf(i32 %arg)
+ ret i32 %res
}
diff --git a/llvm/test/CodeGen/SystemZ/zos-section-1.ll b/llvm/test/CodeGen/SystemZ/zos-section-1.ll
index 0fe781c94b6f2..dc4d6b25eab3d 100644
--- a/llvm/test/CodeGen/SystemZ/zos-section-1.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-section-1.ll
@@ -134,33 +134,33 @@ entry:
; CHECK-NEXT: 000420 00 00 00 00 00 00 00 {{..}} 00 c3 00 c5 00 c5 00 f1
; Text record for the section .&ppa2.
-; CHECK: 0004b0 03 10 00 00 [[PPA2]] 00 00 00 00 00 00 00 00
-; CHECK-NEXT: 0004c0 00 00 00 00 00 00 00 {{..}} {{.*}}
+; CHECK: 000500 03 10 00 00 [[PPA2]] 00 00 00 00 00 00 00 00
+; CHECK-NEXT: 000510 00 00 00 00 00 00 00 {{..}} {{.*}}
; Text record for the ADA section test#S.
-; CHECK: 000500 03 10 00 00 [[TESTS]] 00 00 00 00 00 00 00 00
-; CHECK-NEXT: 000510 00 00 00 00 00 00 00 {{..}} {{.*}}
+; CHECK: 000550 03 10 00 00 [[TESTS]] 00 00 00 00 00 00 00 00
+; CHECK-NEXT: 000560 00 00 00 00 00 00 00 {{..}} {{.*}}
; Text record for the section B_IDRL.
-; CHECK: 000550 03 10 00 01 [[BIDRL]] 00 00 00 00 00 00 00 00
-; CHECK-NEXT: 000560 00 00 00 00 00 00 00 {{..}} {{.*}}
+; CHECK: 0005a0 03 10 00 01 [[BIDRL]] 00 00 00 00 00 00 00 00
+; CHECK-NEXT: 0005b0 00 00 00 00 00 00 00 {{..}} {{.*}}
; The relocation data directory.
-; CHECK: 0005a0 03 21 00 00 00 5c 00 00 02 00 04 00 00 00 00 00
-; CHECK-NEXT: 0005b0 00 08 00 00 00 02 00 00 00 5a 60 00 00 00 04 00
-; CHECK-NEXT: 0005c0 00 00 00 00 00 09 00 00 00 00 08 00 00 00 00 00
-; CHECK-NEXT: 0005d0 00 08 00 00 00 04 00 00 00 00 60 00 02 00 08 00
-; CHECK-NEXT: 0005e0 00 00 00 00 00 09 20 70 01 00 08 00 00 00 00 00
+; CHECK: 0005f0 03 21 00 00 00 5c 00 00 02 00 04 00 00 00 00 00
+; CHECK-NEXT: 000600 00 08 00 00 00 02 00 00 00 5c 60 00 00 00 04 00
+; CHECK-NEXT: 000610 00 00 00 00 00 09 00 00 00 00 08 00 00 00 00 00
+; CHECK-NEXT: 000620 00 08 00 00 00 04 00 00 00 00 60 00 02 00 08 00
+; CHECK-NEXT: 000630 00 00 00 00 00 09 20 70 01 00 08 00 00 00 00 00
; Continuation of the relocation data directory.
-; CHECK-NEXT: 0005f0 03 22 00 00 0b 00 00 00 06 c0 00 01 00 08 00 00
-; CHECK-NEXT: 000600 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00
-; CHECK-NEXT: 000610 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-; CHECK-NEXT: 000620 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-; CHECK-NEXT: 000630 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-
-; End record.
-; CHECK: 000640 03 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-; CHECK-NEXT: 000650 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+; CHECK-NEXT: 000640 03 22 00 00 0b 00 00 00 06 c0 00 01 00 08 00 00
+; CHECK-NEXT: 000650 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00
; CHECK-NEXT: 000660 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
; CHECK-NEXT: 000670 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
; CHECK-NEXT: 000680 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+; End record.
+; CHECK: 000690 03 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+; CHECK-NEXT: 0006a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+; CHECK-NEXT: 0006b0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+; CHECK-NEXT: 0006c0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+; CHECK-NEXT: 0006d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/llvm/test/CodeGen/SystemZ/zos-symbol-2.ll b/llvm/test/CodeGen/SystemZ/zos-symbol-2.ll
index 663c01ccd80dc..e0dec33d20cbb 100644
--- a/llvm/test/CodeGen/SystemZ/zos-symbol-2.ll
+++ b/llvm/test/CodeGen/SystemZ/zos-symbol-2.ll
@@ -37,7 +37,7 @@ entry:
; .1 is flag (record is continued)
; 00 is version
; CHECKREL: 000690 03 21 00 00 00 60 00 00 02 00 04 00 00 00 00 00
-; CHECKREL-NEXT: 0006a0 00 0b 00 00 00 02 00 00 00 4e 60 00 00 00 04 00
+; CHECKREL-NEXT: 0006a0 00 0b 00 00 00 02 00 00 00 50 60 00 00 00 04 00
; CHECKREL-NEXT: 0006b0 00 00 00 00 00 0c 00 00 00 00 08 00 00 00 00 00
; CHECKREL-NEXT: 0006c0 00 0b 00 00 00 04 00 00 00 00 60 00 02 00 08 00
; CHECKREL-NEXT: 0006d0 00 00 00 00 00 0c 20 00 00 00 08 00 00 00 00 00
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