[llvm] [GlobalISel] Add sub_one_from_sub from SelectionDAG (PR #181670)
Osman Yasar via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 20 09:16:23 PST 2026
https://github.com/osmanyasar05 updated https://github.com/llvm/llvm-project/pull/181670
>From 1fedc45b760525f3439591f7b8d697b4706f0960 Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05 at gmail.com>
Date: Mon, 16 Feb 2026 14:04:07 +0000
Subject: [PATCH 1/3] add sub_one_from_sub
---
.../include/llvm/Target/GlobalISel/Combine.td | 10 +++++++-
.../AArch64/GlobalISel/combine-sub.mir | 23 +++++++++++++++++++
2 files changed, 32 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index f5c940bffc8fb..5972bcffcd5ac 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -578,6 +578,14 @@ def right_identity_one_int: GICombineRule<
(apply (GIReplaceReg $dst, $x))
>;
+// fold (A - B) - 1 -> add (xor B, -1), A
+def sub_one_from_sub: GICombineRule<
+ (defs root:$dst),
+ (match (G_SUB $sub1, $a, $b),
+ (G_SUB $dst, $sub1, 1)),
+ (apply (G_XOR $xor1, $b, -1),
+ (G_ADD $dst, $xor1, $a))>;
+
def right_identity_one_fp: GICombineRule<
(defs root:$dst),
(match (G_FMUL $dst, $x, $y):$root,
@@ -2296,7 +2304,7 @@ def all_combines : GICombineGroup<[integer_reassoc_combines, trivial_combines,
simplify_neg_minmax, combine_concat_vector,
sext_trunc, zext_trunc, prefer_sign_combines, shuffle_combines,
combine_use_vector_truncate, merge_combines, overflow_combines,
- truncsat_combines, lshr_of_trunc_of_lshr, ctls_combines, add_shift]>;
+ truncsat_combines, lshr_of_trunc_of_lshr, ctls_combines, add_shift, sub_one_from_sub]>;
// A combine group used to for prelegalizer combiners at -O0. The combines in
// this group have been selected based on experiments to balance code size and
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir
new file mode 100644
index 0000000000000..47a74c465beb7
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir
@@ -0,0 +1,23 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
+---
+name: sub_one_from_sub
+body: |
+ bb.1:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: sub_one_from_sub
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY1]], [[C]]
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[XOR]], [[COPY]]
+ ; CHECK-NEXT: $w0 = COPY [[ADD]](s32)
+ %0:_(s32) = COPY $w0
+ %1:_(s32) = COPY $w1
+ %cst:_(s32) = G_CONSTANT i32 1
+ %2:_(s32) = G_SUB %0, %1
+ %3:_(s32) = G_SUB %2, %cst
+ $w0 = COPY %3(s32)
>From 6e3bb73da840500a7dd5f0276a6f0dfc0247e742 Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05 at gmail.com>
Date: Mon, 16 Feb 2026 15:02:46 +0000
Subject: [PATCH 2/3] one use check
---
.../include/llvm/Target/GlobalISel/Combine.td | 3 ++-
.../AArch64/GlobalISel/combine-sub.mir | 25 +++++++++++++++++++
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index 5972bcffcd5ac..7631f2fd6a647 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -582,7 +582,8 @@ def right_identity_one_int: GICombineRule<
def sub_one_from_sub: GICombineRule<
(defs root:$dst),
(match (G_SUB $sub1, $a, $b),
- (G_SUB $dst, $sub1, 1)),
+ (G_SUB $dst, $sub1, 1),
+ [{ return MRI.hasOneNonDBGUse(${sub1}.getReg()); }]),
(apply (G_XOR $xor1, $b, -1),
(G_ADD $dst, $xor1, $a))>;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir
index 47a74c465beb7..44d66702b8c22 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir
@@ -21,3 +21,28 @@ body: |
%2:_(s32) = G_SUB %0, %1
%3:_(s32) = G_SUB %2, %cst
$w0 = COPY %3(s32)
+...
+
+---
+name: sub_one_from_sub_one_use
+body: |
+ bb.1:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: sub_one_from_sub_one_use
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SUB]], [[C]]
+ ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SUB]], [[ADD]]
+ ; CHECK-NEXT: $w0 = COPY [[MUL]](s32)
+ %0:_(s32) = COPY $w0
+ %1:_(s32) = COPY $w1
+ %cst:_(s32) = G_CONSTANT i32 1
+ %2:_(s32) = G_SUB %0, %1
+ %3:_(s32) = G_SUB %2, %cst
+ %4:_(s32) = G_MUL %2, %3
+ $w0 = COPY %4(s32)
>From 4305e3fb3368ab3f955ae16d8135e15a73c39d72 Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05 at gmail.com>
Date: Fri, 20 Feb 2026 17:16:08 +0000
Subject: [PATCH 3/3] tests
---
.../CodeGen/AArch64/GlobalISel/combine-sub.ll | 29 +++++++++++++++++++
.../AArch64/GlobalISel/combine-sub.mir | 27 +++++++++++++++++
2 files changed, 56 insertions(+)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.ll
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.ll b/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.ll
new file mode 100644
index 0000000000000..6f50a9b190dcb
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel | FileCheck %s --check-prefixes=GISEL
+
+; fold (sub -1, a) -> (xor a, -1)
+define i64 @sub_minus_one(i64 %a) {
+; GISEL-LABEL: sub_minus_one:
+; GISEL: // %bb.0: // %entry
+; GISEL-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; GISEL-NEXT: sub x0, x8, x0
+; GISEL-NEXT: ret
+entry:
+; fold (A - (0 - B)) to (A + B)
+ %sub1 = sub i64 -1, %a
+ ret i64 %sub1
+}
+
+; fold (A - B) - 1 -> add (xor B, -1), A
+define i64 @sub_one_from_sub(i64 %a, i64 %b) {
+; GISEL-LABEL: sub_one_from_sub:
+; GISEL: // %bb.0: // %entry
+; GISEL-NEXT: neg x8, x1
+; GISEL-NEXT: sub x0, x0, x8
+; GISEL-NEXT: ret
+entry:
+; fold (A - (0 - B)) to (A + B)
+ %sub1 = sub i64 0, %b
+ %sub2 = sub i64 %a, %sub1
+ ret i64 %sub2
+}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir
index 44d66702b8c22..5a75e5d249e62 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-sub.mir
@@ -23,6 +23,33 @@ body: |
$w0 = COPY %3(s32)
...
+---
+name: sub_one_from_sub_vec
+body: |
+ bb.1:
+ liveins: $x0, $x1
+
+ ; CHECK-LABEL: name: sub_one_from_sub_vec
+ ; CHECK: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $x1
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16), [[C]](s16), [[C]](s16)
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s16>) = G_XOR [[COPY1]], [[BUILD_VECTOR]]
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<4 x s16>) = G_ADD [[XOR]], [[COPY]]
+ ; CHECK-NEXT: $x0 = COPY [[ADD]](<4 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+ %0:_(<4 x s16>) = COPY $x0
+ %1:_(<4 x s16>) = COPY $x1
+ %c1:_(s16) = G_CONSTANT i16 1
+ %cst:_(<4 x s16>) = G_BUILD_VECTOR %c1(s16), %c1(s16), %c1(s16), %c1(s16)
+ %2:_(<4 x s16>) = G_SUB %0, %1
+ %3:_(<4 x s16>) = G_SUB %2, %cst
+ $x0 = COPY %3
+ RET_ReallyLR implicit $x0
+...
+
---
name: sub_one_from_sub_one_use
body: |
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