[llvm] [AArch64] Wrap integer SCALAR_TO_VECTOR nodes in bitcasts (PR #172837)

[via llvm-commits]

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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16,+fprcvt | FileCheck %s
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CarolineConcatto wrote:

Can we remove +fullfp16 and from the other tests? I dont think it is needed.
At least not for these instructions:
https://developer.arm.com/documentation/ddi0602/2025-09/SIMD-FP-Instructions/FCVTZS--scalar-SIMD-FP---Floating-point-convert-to-signed-integer--rounding-toward-zero--scalar-SIMD-FP--?lang=en
It is only needed for 
FCVTZS  <Vd>.4h , <Vn>.4h  or FCVTZS  <Vt>.8h , <Vn>.8h or FCVTZS  Hd, Hn
And I could not find  them in any tests

https://github.com/llvm/llvm-project/pull/172837