[llvm] [GlobalISel] Add integer combines from SelectionDAG (PR #181126)
Osman Yasar via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 20 05:02:28 PST 2026
https://github.com/osmanyasar05 updated https://github.com/llvm/llvm-project/pull/181126
>From 695bd43a8fd1f19fc906e72ba70938c3b6d92a13 Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05 at gmail.com>
Date: Wed, 11 Feb 2026 21:24:07 +0000
Subject: [PATCH 1/4] first commit
---
.../include/llvm/Target/GlobalISel/Combine.td | 16 +++++++
.../AArch64/GlobalISel/combine-integer.mir | 43 +++++++++++++++++++
2 files changed, 59 insertions(+)
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index f5c940bffc8fb..a90790afa8dfb 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -1946,6 +1946,20 @@ def APlusBMinusCPlusA : GICombineRule<
(G_SUB $sub1, $B, $add1),
(G_ADD $root, $A, $sub1)),
(apply (G_SUB $root, $B, $C))>;
+
+// fold (A - (0 - B)) to (A + B)
+def AMinusZeroMinusB : GICombineRule<
+ (defs root:$root),
+ (match (G_SUB $sub1, 0, $B),
+ (G_SUB $root, $A, $sub1)),
+ (apply (G_ADD $root, $A, $B))>;
+
+// fold A - (A - B) -> B
+def AMinusBMinusA: GICombineRule<
+ (defs root:$root),
+ (match (G_SUB $add, $A, $B),
+ (G_SUB $root, $A, $add)),
+ (apply (GIReplaceReg $root, $B))>;
// fold (A+C1)-C2 -> A+(C1-C2)
def APlusC1MinusC2: GICombineRule<
@@ -2008,6 +2022,8 @@ def integer_reassoc_combines: GICombineGroup<[
AMinusBPlusBMinusC,
APlusBMinusAplusC,
APlusBMinusCPlusA,
+ AMinusZeroMinusB,
+ AMinusBMinusA,
APlusC1MinusC2,
C2MinusAPlusC1,
AMinusC1MinusC2,
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
index c9b24ad75ce27..0f7efc9df34bb 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
@@ -413,3 +413,46 @@ body: |
$x0 = COPY %add
RET_ReallyLR implicit $x0
+...
+---
+name: AMinusZeroMinusB
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+
+ ; CHECK-LABEL: name: AMinusZeroMinusB
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(s64) = COPY $x0
+ ; CHECK-NEXT: %b:_(s64) = COPY $x1
+ ; CHECK-NEXT: %sub2:_(s64) = G_ADD %a, %b
+ ; CHECK-NEXT: $x0 = COPY %sub2(s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+ %a:_(s64) = COPY $x0
+ %b:_(s64) = COPY $x1
+ %c1:_(s64) = G_CONSTANT i64 0
+ %sub1:_(s64) = G_SUB %c1, %b
+ %sub2:_(s64) = G_SUB %a, %sub1
+ $x0 = COPY %sub2
+ RET_ReallyLR implicit $x0
+
+...
+---
+name: AMinusBMinusA
+body: |
+ bb.0:
+ liveins: $w0, $w1
+
+ ; CHECK-LABEL: name: AMinusBMinusA
+ ; CHECK: liveins: $w0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %b:_(s64) = COPY $x1
+ ; CHECK-NEXT: $x0 = COPY %b(s64)
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+ %a:_(s64) = COPY $x0
+ %b:_(s64) = COPY $x1
+ %sub:_(s64) = G_SUB %a, %b
+ %add:_(s64) = G_SUB %a, %sub
+ $x0 = COPY %add
+ RET_ReallyLR implicit $x0
>From 82d53800751114ed96b3ee0f29f70c30e3b4ac25 Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05 at gmail.com>
Date: Thu, 12 Feb 2026 12:56:58 +0000
Subject: [PATCH 2/4] modify tests
---
llvm/test/CodeGen/AArch64/neg-selects.ll | 4 +---
.../test/CodeGen/AArch64/neon-bitwise-instructions.ll | 11 ++++-------
2 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/neg-selects.ll b/llvm/test/CodeGen/AArch64/neg-selects.ll
index b643ee7670e42..f656fc2e62040 100644
--- a/llvm/test/CodeGen/AArch64/neg-selects.ll
+++ b/llvm/test/CodeGen/AArch64/neg-selects.ll
@@ -35,9 +35,7 @@ define i32 @negneg_select_nega(i32 %a, i32 %b, i1 %bb) {
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: and w8, w2, #0x1
; CHECK-GI-NEXT: tst w8, #0x1
-; CHECK-GI-NEXT: csneg w8, w1, w0, eq
-; CHECK-GI-NEXT: neg w8, w8
-; CHECK-GI-NEXT: neg w0, w8
+; CHECK-GI-NEXT: csneg w0, w1, w0, eq
; CHECK-GI-NEXT: ret
%nega = sub i32 0, %a
%sel = select i1 %bb, i32 %nega, i32 %b
diff --git a/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll b/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
index 01aea72d77114..e8eb8e87f3b66 100644
--- a/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
@@ -2849,14 +2849,11 @@ define <8 x i16> @pr149380(<4 x i16> %u1, <1 x i64> %u2, <8 x i16> %vqshlu_n169)
; CHECK-GI-LABEL: pr149380:
; CHECK-GI: // %bb.0: // %entry
; CHECK-GI-NEXT: movi v0.2d, #0xffffffffffffffff
-; CHECK-GI-NEXT: neg v1.8h, v2.8h
-; CHECK-GI-NEXT: movi v3.8h, #1
-; CHECK-GI-NEXT: neg v1.8h, v1.8h
+; CHECK-GI-NEXT: movi v1.8h, #1
; CHECK-GI-NEXT: sub v0.8h, v0.8h, v2.8h
-; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-GI-NEXT: and v0.16b, v0.16b, v3.16b
-; CHECK-GI-NEXT: orr v0.16b, v1.16b, v0.16b
-; CHECK-GI-NEXT: sqadd v0.8h, v3.8h, v0.8h
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
+; CHECK-GI-NEXT: orr v0.16b, v2.16b, v0.16b
+; CHECK-GI-NEXT: sqadd v0.8h, v1.8h, v0.8h
; CHECK-GI-NEXT: ret
entry:
%mul.i = mul <8 x i16> %vqshlu_n169, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
>From ec57cc6b7ad1fb3809707089c1cf68c7655a413f Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05 at gmail.com>
Date: Fri, 20 Feb 2026 12:45:14 +0000
Subject: [PATCH 3/4] add ir tests
---
.../AArch64/GlobalISel/combine-integer-ll.ll | 25 +++++++++++++++++++
.../AArch64/GlobalISel/combine-integer.mir | 2 ++
2 files changed, 27 insertions(+)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer-ll.ll b/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer-ll.ll
index 44e3ca6330f53..0644ab9d8f000 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer-ll.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer-ll.ll
@@ -66,6 +66,31 @@ entry:
ret i64 %add1
}
+define i64 @AMinusZeroMinusB(i64 %a, i64 %b) {
+; CHECK-LABEL: AMinusZeroMinusB:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: add x0, x0, x1
+; CHECK-NEXT: ret
+
+entry:
+; fold (A - (0 - B)) to (A + B)
+ %sub1 = sub i64 0, %b
+ %sub2 = sub i64 %a, %sub1
+ ret i64 %sub2
+}
+
+define i64 @AMinusBMinusA(i64 %a, i64 %b) {
+; CHECK-LABEL: AMinusBMinusA:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: mov x0, x1
+; CHECK-NEXT: ret
+entry:
+; fold A - (A - B) -> B
+ %sub1 = sub i64 %a, %b
+ %sub2 = sub i64 %a, %sub1
+ ret i64 %sub2
+}
+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-GI: {{.*}}
; CHECK-SD: {{.*}}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
index 0f7efc9df34bb..02580e1371697 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
@@ -456,3 +456,5 @@ body: |
%add:_(s64) = G_SUB %a, %sub
$x0 = COPY %add
RET_ReallyLR implicit $x0
+
+...
>From ad8515b6ee9ffe11f019d94145a51fadb912f52a Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05 at gmail.com>
Date: Fri, 20 Feb 2026 13:02:16 +0000
Subject: [PATCH 4/4] vector tests
---
.../AArch64/GlobalISel/combine-integer.mir | 50 +++++++++++++++++--
1 file changed, 47 insertions(+), 3 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
index 02580e1371697..528cce0fc4c8d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-integer.mir
@@ -437,6 +437,30 @@ body: |
$x0 = COPY %sub2
RET_ReallyLR implicit $x0
+...
+---
+name: AMinusZeroMinusB_BV
+body: |
+ bb.0:
+ liveins: $q0, $q1
+
+ ; CHECK-LABEL: name: AMinusZeroMinusB_BV
+ ; CHECK: liveins: $q0, $q1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %a:_(<4 x s32>) = COPY $q0
+ ; CHECK-NEXT: %b:_(<4 x s32>) = COPY $q1
+ ; CHECK-NEXT: %sub2:_(<4 x s32>) = G_ADD %a, %b
+ ; CHECK-NEXT: $q0 = COPY %sub2(<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
+ %a:_(<4 x s32>) = COPY $q0
+ %b:_(<4 x s32>) = COPY $q1
+ %c:_(s32) = G_CONSTANT i32 0
+ %c1:_(<4 x s32>) = G_BUILD_VECTOR %c(s32), %c(s32), %c(s32), %c(s32)
+ %sub1:_(<4 x s32>) = G_SUB %c1, %b
+ %sub2:_(<4 x s32>) = G_SUB %a, %sub1
+ $q0 = COPY %sub2
+ RET_ReallyLR implicit $q0
+
...
---
name: AMinusBMinusA
@@ -452,9 +476,29 @@ body: |
; CHECK-NEXT: RET_ReallyLR implicit $x0
%a:_(s64) = COPY $x0
%b:_(s64) = COPY $x1
- %sub:_(s64) = G_SUB %a, %b
- %add:_(s64) = G_SUB %a, %sub
- $x0 = COPY %add
+ %sub1:_(s64) = G_SUB %a, %b
+ %sub2:_(s64) = G_SUB %a, %sub1
+ $x0 = COPY %sub2
RET_ReallyLR implicit $x0
...
+---
+name: AMinusBMinusA_BV
+body: |
+ bb.0:
+ liveins: $q0, $q1
+
+ ; CHECK-LABEL: name: AMinusBMinusA_BV
+ ; CHECK: liveins: $q0, $q1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %b:_(<4 x s32>) = COPY $q1
+ ; CHECK-NEXT: $q0 = COPY %b(<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
+ %a:_(<4 x s32>) = COPY $q0
+ %b:_(<4 x s32>) = COPY $q1
+ %sub1:_(<4 x s32>) = G_SUB %a, %b
+ %sub2:_(<4 x s32>) = G_SUB %a, %sub1
+ $q0 = COPY %sub2
+ RET_ReallyLR implicit $q0
+
+...
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