[llvm] [Mips] Add r5900 (PlayStation 2 Emotion Engine) FPU Support (PR #178942)

[Matt Arsenault via llvm-commits]

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@@ -554,11 +563,78 @@ SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
   case ISD::VECTOR_SHUFFLE:     return lowerVECTOR_SHUFFLE(Op, DAG);
   case ISD::SELECT:             return lowerSELECT(Op, DAG);
   case ISD::BITCAST:            return lowerBITCAST(Op, DAG);
+  case ISD::FADD:
+  case ISD::FSUB:
+  case ISD::FMUL:
+  case ISD::FDIV:
+  case ISD::FSQRT:
+    return lowerR5900FPOp(Op, DAG);
   }
 
   return MipsTargetLowering::LowerOperation(Op, DAG);
 }
 
+SDValue MipsSETargetLowering::lowerR5900FPOp(SDValue Op,
+                                             SelectionDAG &DAG) const {
+  assert(Subtarget.isR5900());
+  SDLoc DL(Op);
+  MVT VT = Op.getSimpleValueType();
+  SDNodeFlags Flags = Op->getFlags();
+
+  SmallVector<SDValue, 2> Ops(Op->op_begin(), Op->op_end());
+
+  if (Flags.hasNoNaNs() && Flags.hasNoInfs()) {
+    // Use the hardware FPU instruction if the operation is guaranteed per-
+    // instruction to have no NaN or infinity inputs/outputs (nnan+ninf flags).
+    unsigned HWOpc;
+    switch (Op.getOpcode()) {
+    case ISD::FADD:
+      HWOpc = MipsISD::R5900_FADD;
+      break;
+    case ISD::FSUB:
+      HWOpc = MipsISD::R5900_FSUB;
+      break;
+    case ISD::FMUL:
+      HWOpc = MipsISD::R5900_FMUL;
+      break;
+    case ISD::FDIV:
+      HWOpc = MipsISD::R5900_FDIV;
+      break;
+    case ISD::FSQRT:
+      HWOpc = MipsISD::R5900_FSQRT;
+      break;
+    default:
+      llvm_unreachable("Unexpected opcode");
+    }
+    return DAG.getNode(HWOpc, DL, VT, Ops);
+  } else {
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arsenm wrote:

No else after return 

https://github.com/llvm/llvm-project/pull/178942