[llvm] [AArch64] Add C1-Nano scheduling model (PR #182316)

[via llvm-commits]

walkerkd wrote:

> Did you consider adding SME instructions?

Actually I hadn't.    I had mainly used what was in the current Cortex-A510 scheduling model, with some additional improvements from the Cortex-A320 scheduling model with timings altered for the C1-Nano.    As neither of those models had SME instructions I had overlooked adding them,

Not having the SME instructions is no worse than the existing situation which is using the Cortex-A510 model which doesn't have them either.   I will look into what is required to add SME instructions for a follow up patch.

https://github.com/llvm/llvm-project/pull/182316