[llvm] AMDGPU coverity fixes (PR #182013)

[Rafał Rudnicki via llvm-commits]

https://github.com/bratpiorka updated https://github.com/llvm/llvm-project/pull/182013

>From 4119931b8e68f759be588797e85b6ebbf15e4064 Mon Sep 17 00:00:00 2001
From: Rafal Rudnicki <rafal.rudnicki at intel.com>
Date: Fri, 20 Feb 2026 10:09:02 +0100
Subject: [PATCH] AMDGPU coverity fixes

---
 llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp         |  1 +
 llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp |  3 ++-
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp            | 10 +++++-----
 3 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
index fc408aa30dd87..be7e1519a119c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
@@ -247,6 +247,7 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
     LLVMContext &C = MI->getMF()->getFunction().getContext();
     C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have "
                 "a target-specific version: " + Twine(MI->getOpcode()));
+    return;
   }
 
   OutMI.setOpcode(MCOpcode);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp b/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
index 7a5db42c7a89a..931a2854c54f9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURewriteAGPRCopyMFMA.cpp
@@ -205,7 +205,8 @@ bool AMDGPURewriteAGPRCopyMFMAImpl::recomputeRegClassExceptRewritable(
       if (!NewRC || NewRC == OldRC) {
         LLVM_DEBUG(dbgs() << "User of " << printReg(Reg, &TRI)
                           << " cannot be reassigned to "
-                          << TRI.getRegClassName(NewRC) << ": " << *MI);
+                          << (NewRC ? TRI.getRegClassName(NewRC) : "NULL")
+                          << ": " << *MI);
         return false;
       }
     }
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 5b83574dee0c3..22a8de8946d62 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -11971,10 +11971,10 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
   case Intrinsic::amdgcn_cooperative_atomic_store_8x16B: {
     MemIntrinsicSDNode *MII = cast<MemIntrinsicSDNode>(Op);
     SDValue Chain = Op->getOperand(0);
-    SDValue Ptr = Op->getOperand(2);
-    SDValue Val = Op->getOperand(3);
-    return DAG.getAtomic(ISD::ATOMIC_STORE, DL, MII->getMemoryVT(), Chain, Val,
-                         Ptr, MII->getMemOperand());
+    SDValue Val = Op->getOperand(2);
+    SDValue Ptr = Op->getOperand(3);
+    return DAG.getAtomic(ISD::ATOMIC_STORE, DL, MII->getMemoryVT(), Chain, Ptr,
+                         Val, MII->getMemOperand());
   }
   default: {
     if (const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr =
@@ -18253,7 +18253,7 @@ SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI_,
       // Check for lossy scalar/vector conversions.
       if (VT.isVector() && VT.getSizeInBits() != 32)
         return std::pair(0U, nullptr);
-      if (Idx < RC->getNumRegs())
+      if (RC && Idx < RC->getNumRegs())
         return std::pair(RC->getRegister(Idx), RC);
       return std::pair(0U, nullptr);
     }