[llvm] [AMDGPU] Remove alignment constraint from spill pseudos (PR #177317)

[via llvm-commits]

================
@@ -1536,12 +1536,39 @@ void SIRegisterInfo::buildSpillLoadStore(
   const bool IsAGPR = !ST.hasGFX90AInsts() && isAGPRClass(RC);
   const unsigned RegWidth = AMDGPU::getRegBitWidth(*RC) / 8;
 
+  // On targets with register tuple alignment requirements,
+  // for unaligned tuples, break the spill into 32-bit pieces.
+  // TODO: Optimize misaligned spills by using larger aligned chunks instead of
+  // 32-bit splits.
+  bool IsRegMisaligned = false;
+  if (!IsBlock && RegWidth > 4) {
+    unsigned SpillOpcode =
+        getFlatScratchSpillOpcode(TII, LoadStoreOp, std::min(RegWidth, 16u));
+    int VDataIdx =
+        IsStore ? AMDGPU::getNamedOperandIdx(SpillOpcode, AMDGPU::OpName::vdata)
+                : 0; // Restore Ops have data reg as the first (output) operand.
+    const TargetRegisterClass *ExpectedRC =
----------------
easyonaadit wrote:

Hmm.
Technically, the input reg tuple has some register class, and the real spill instruction 'expects' a certain register class, and we are checking if the input RC matches the 'expected' RC.
I can change it tho.



https://github.com/llvm/llvm-project/pull/177317