[llvm] [RISCV] Enhance RISCVMoveMerger for GPRPair Moves on RV32 #180831 (PR #182416)

[Sam Elliott via llvm-commits]

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@@ -211,8 +211,7 @@ define <8 x i8> @test_call_v8i8(<8 x i8> %a, <8 x i8> %b) {
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    mv a4, a1
 ; RV32-NEXT:    mv a5, a0
-; RV32-NEXT:    mv a0, a2
-; RV32-NEXT:    mv a1, a3
+; RV32-NEXT:    addd a0, a2, zero
 ; RV32-NEXT:    mv a2, a5
 ; RV32-NEXT:    mv a3, a4
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lenary wrote:

(No Action Needed) This code is better with the pair moves, but this is doing a GPR pair swap, so the remaining 4 `mv` should be able to be optimised, as well. I think this problem is coming from some bad register allocation, so we cannot fix it in this pass. I'll have a think about how this might be solved.

https://github.com/llvm/llvm-project/pull/182416