[llvm] [DAG] Propagate OrZero and DemandedElts for min/max in isKnownToBeAPowerOfTwo (PR #182369)

via llvm-commits llvm-commits at lists.llvm.org
Thu Feb 19 14:15:13 PST 2026


github-actions[bot] wrote:

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp --diff_from_common_commit
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
index d2b4e6159..a51f4e43e 100644
--- a/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
+++ b/llvm/unittests/Target/AArch64/AArch64SelectionDAGTest.cpp
@@ -978,8 +978,7 @@ TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_MinMaxOrZero) {
   SDValue Cst16 = DAG->getConstant(16, Loc, MVT::i32);
 
   SDValue Cond = DAG->getCopyFromReg(DAG->getEntryNode(), Loc, 1, MVT::i1);
-  SDValue Select40 =
-      DAG->getNode(ISD::SELECT, Loc, MVT::i32, Cond, Cst4, Cst0);
+  SDValue Select40 = DAG->getNode(ISD::SELECT, Loc, MVT::i32, Cond, Cst4, Cst0);
 
   SDValue UMinSelect16 =
       DAG->getNode(ISD::UMIN, Loc, MVT::i32, Select40, Cst16);

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https://github.com/llvm/llvm-project/pull/182369


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