[llvm] 92cc4ff - [PowerPC] Refactor immediate operand definitions (#179983)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 19 11:20:10 PST 2026
Author: Lei Huang
Date: 2026-02-19T14:20:04-05:00
New Revision: 92cc4ffb81f06413592d739c4e58071a9a4b7f70
URL: https://github.com/llvm/llvm-project/commit/92cc4ffb81f06413592d739c4e58071a9a4b7f70
DIFF: https://github.com/llvm/llvm-project/commit/92cc4ffb81f06413592d739c4e58071a9a4b7f70.diff
LOG: [PowerPC] Refactor immediate operand definitions (#179983)
Refactors PowerPC's immediate operand definitions using multiclasses
to reduce code duplication and improve maintainability.
Changes include:
- Established consistent naming: i32 versions without suffix, i64
versions with '64' suffix
- Predicate functions added to imm/timm nodes to verify immdiate values.
Assistance provided by AI.
Added:
llvm/lib/Target/PowerPC/PPCOperands.td
Modified:
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrAltivec.td
llvm/lib/Target/PowerPC/PPCInstrFuture.td
llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrP10.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/lib/Target/PowerPC/PPCRegisterInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index d4ce03c07663f..2b62654b08986 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -338,13 +338,15 @@ def LDAT_PSEUDO : PPCCustomInserterPseudo<
(outs g8rc:$dst),
(ins ptr_rc_nor0:$ptr, g8rc:$val, u5imm:$fc),
"#LDAT_PSEUDO",
- [(set i64:$dst, (int_ppc_amo_ldat ptr_rc_nor0:$ptr, g8rc:$val, timm:$fc))]>;
+ [(set i64:$dst, (int_ppc_amo_ldat ptr_rc_nor0:$ptr, g8rc:$val,
+ u5imm_timm:$fc))]>;
def LDAT_COND_PSEUDO : PPCCustomInserterPseudo <
(outs g8rc:$dst),
(ins ptr_rc_nor0:$ptr, u5imm:$fc),
"#LDAT_COND_PSEUDO",
- [(set i64:$dst, (int_ppc_amo_ldat_cond ptr_rc_nor0:$ptr, timm:$fc))]>;
+ [(set i64:$dst, (int_ppc_amo_ldat_cond ptr_rc_nor0:$ptr,
+ u5imm_timm:$fc))]>;
let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {
def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
@@ -412,9 +414,11 @@ def : Pat<(int_ppc_cmpxchg_i128 ForceXForm:$ptr,
g8rc:$new_hi))>;
let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
-def STDAT : XForm_base_r3xo_memOp<31, 742, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, u5imm:$RB),
+def STDAT : XForm_base_r3xo_memOp<31, 742, (outs),
+ (ins g8rc:$RST, ptr_rc_nor0:$RA, u5imm:$RB),
"stdat $RST, $RA, $RB", IIC_LdStStore,
- [(PPCstat i64:$RST, ptr_rc_nor0:$RA, timm:$RB)]>, isPPC64,
+ [(PPCstat i64:$RST, ptr_rc_nor0:$RA,
+ u5imm_timm:$RB)]>, isPPC64,
Requires<[IsISA3_0]>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
@@ -1823,7 +1827,7 @@ def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$RT),
(ins g8rc:$RA, g8rc:$RB, u2imm:$CY),
"addex $RT, $RA, $RB, $CY", IIC_IntGeneral,
[(set i64:$RT, (int_ppc_addex i64:$RA, i64:$RB,
- timm:$CY))]>;
+ u2imm_timm:$CY))]>;
//===----------------------------------------------------------------------===//
// Instruction Patterns
diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
index 461ab3a2851ab..156931a372136 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -343,7 +343,8 @@ class VXBX_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
: VXForm_CR<xo, (outs vrrc:$VD), (ins vrrc:$VA, u1imm:$ST, u4imm:$SIX),
!strconcat(opc, " $VD, $VA, $ST, $SIX"), IIC_VecFP,
- [(set Ty:$VD, (IntID Ty:$VA, timm:$ST, timm:$SIX))]>;
+ [(set Ty:$VD, (IntID Ty:$VA, u1imm_timm:$ST,
+ u4imm_timm:$SIX))]>;
//===----------------------------------------------------------------------===//
// Instruction Definitions.
@@ -533,19 +534,19 @@ def VANDC : VXForm_1<1092, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
def VCFSX : VXForm_1<842, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),
"vcfsx $VD, $VB, $VA", IIC_VecFP,
[(set v4f32:$VD,
- (int_ppc_altivec_vcfsx v4i32:$VB, timm:$VA))]>;
+ (int_ppc_altivec_vcfsx v4i32:$VB, u5imm_timm:$VA))]>;
def VCFUX : VXForm_1<778, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),
"vcfux $VD, $VB, $VA", IIC_VecFP,
[(set v4f32:$VD,
- (int_ppc_altivec_vcfux v4i32:$VB, timm:$VA))]>;
+ (int_ppc_altivec_vcfux v4i32:$VB, u5imm_timm:$VA))]>;
def VCTSXS : VXForm_1<970, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),
"vctsxs $VD, $VB, $VA", IIC_VecFP,
[(set v4i32:$VD,
- (int_ppc_altivec_vctsxs v4f32:$VB, timm:$VA))]>;
+ (int_ppc_altivec_vctsxs v4f32:$VB, u5imm_timm:$VA))]>;
def VCTUXS : VXForm_1<906, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),
"vctuxs $VD, $VB, $VA", IIC_VecFP,
[(set v4i32:$VD,
- (int_ppc_altivec_vctuxs v4f32:$VB, timm:$VA))]>;
+ (int_ppc_altivec_vctuxs v4f32:$VB, u5imm_timm:$VA))]>;
// Defines with the UIM field set to 0 for floating-point
// to integer (fp_to_sint/fp_to_uint) conversions and integer
@@ -1397,9 +1398,9 @@ def VUPKLSW : VX2_Int_Ty2<1742, "vupklsw", int_ppc_altivec_vupklsw,
def BCDADD_rec : VX_VT5_VA5_VB5_PS1_XO9_o<1, "bcdadd." , []>;
def BCDSUB_rec : VX_VT5_VA5_VB5_PS1_XO9_o<65, "bcdsub." , []>;
-def : Pat<(v16i8 (int_ppc_bcdadd v16i8:$vA, v16i8:$vB, timm:$PS)),
+def : Pat<(v16i8 (int_ppc_bcdadd v16i8:$vA, v16i8:$vB, u1imm_timm:$PS)),
(BCDADD_rec $vA, $vB, $PS)>;
-def : Pat<(v16i8 (int_ppc_bcdsub v16i8:$vA, v16i8:$vB, timm:$PS)),
+def : Pat<(v16i8 (int_ppc_bcdsub v16i8:$vA, v16i8:$vB, u1imm_timm:$PS)),
(BCDSUB_rec $vA, $vB, $PS)>;
// Shuffle patterns for unary and swapped (LE) vector pack modulo.
@@ -1635,13 +1636,13 @@ class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc,
// Decimal Convert From/to National/Zoned/Signed-QWord
def BCDCFN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." ,
- [(set v16i8:$VD, (int_ppc_national2packed v16i8:$VB, timm:$PS))]>;
+ [(set v16i8:$VD, (int_ppc_national2packed v16i8:$VB, u1imm_timm:$PS))]>;
def BCDCFZ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." ,
- [(set v16i8:$VD, (int_ppc_zoned2packed v16i8:$VB, timm:$PS))]>;
+ [(set v16i8:$VD, (int_ppc_zoned2packed v16i8:$VB, u1imm_timm:$PS))]>;
def BCDCTN_rec : VX_VT5_EO5_VB5_XO9_o <5, 385, "bcdctn." ,
[(set v16i8:$VD, (int_ppc_packed2national v16i8:$VB))]>;
def BCDCTZ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." ,
- [(set v16i8:$VD, (int_ppc_packed2zoned v16i8:$VB, timm:$PS))]>;
+ [(set v16i8:$VD, (int_ppc_packed2zoned v16i8:$VB, u1imm_timm:$PS))]>;
def BCDCFSQ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<2, 385, "bcdcfsq.", []>;
def BCDCTSQ_rec : VX_VT5_EO5_VB5_XO9_o <0, 385, "bcdctsq.", []>;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 39e6f4f139c11..eb56fea8c9888 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -380,13 +380,13 @@ let Predicates = [IsISAFuture] in {
let Predicates = [IsISAFuture, PrefixInstrs] in {
defm PADDIS : MLS_DForm_R_SI32_RTA5_p<15, (outs gprc:$RT),
- (ins gprc_nor0:$RA, s32imm:$SI),
- (ins immZero:$RA, s32imm_pcrel:$SI),
+ (ins gprc_nor0:$RA, s32imm64:$SI),
+ (ins immZero:$RA, s32imm64_pcrel:$SI),
"paddis $RT, $RA, $SI", IIC_LdStLFD>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm PADDIS8 : MLS_DForm_R_SI32_RTA5_p<15, (outs g8rc:$RT),
- (ins g8rc_nox0:$RA, s32imm:$SI),
- (ins immZero:$RA, s32imm_pcrel:$SI),
+ (ins g8rc_nox0:$RA, s32imm64:$SI),
+ (ins immZero:$RA, s32imm64_pcrel:$SI),
"paddis $RT, $RA, $SI", IIC_LdStLFD>;
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
index 076c7465994cf..1b4b58f724bc8 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
@@ -472,7 +472,7 @@ let Predicates = [MMA, IsISAFuture] in {
def DMXXINSTDMR256 : XX2Form_AT3_XBp5_P2<60, 485, (outs dmrrowp:$AT),
(ins vsrprc:$XBp, u2imm:$P),
"dmxxinstdmr256 $AT, $XBp, $P",
- [(set v256i1:$AT, (PPCInst256 v256i1:$XBp, timm:$P))]>;
+ [(set v256i1:$AT, (PPCInst256 v256i1:$XBp, u2imm_timm:$P))]>;
def DMMR
: XForm_ATB3<31, 6, 177, (outs dmr:$AT), (ins dmr:$AB), "dmmr $AT, $AB",
@@ -512,13 +512,14 @@ let Predicates = [MMA, IsISAFuture] in {
31, 14, 177, (outs dmr:$AT), (ins dmr:$ATi, dmr:$AB, u1imm:$T),
"dmsha2hash $AT, $AB, $T",
[(set v1024i1:$AT, (int_ppc_mma_dmsha2hash v1024i1:$ATi,
- v1024i1:$AB, timm:$T))]>,
+ v1024i1:$AB, u1imm_timm:$T))]>,
RegConstraint<"$ATi = $AT">;
def DMSHA3HASH
: XForm_ATp2_SR5<31, 15, 177, (outs dmrp:$ATp),
(ins dmrp:$ATpi, u5imm:$SR), "dmsha3hash $ATp, $SR",
[(set v2048i1:$ATp,
- (int_ppc_mma_dmsha3hash v2048i1:$ATpi, timm:$SR))]>,
+ (int_ppc_mma_dmsha3hash v2048i1:$ATpi,
+ u5imm_timm:$SR))]>,
RegConstraint<"$ATpi = $ATp">;
def DMXXSHAPAD
: XX2Form_AT3_XB6_ID2_E1_BL2<60, 421, (outs dmr:$AT),
@@ -592,8 +593,8 @@ let Predicates = [MMA, IsISAFuture] in {
(DMXVF16GERX2NN $ATi, $XAp, RCCp.BToVSRC)>;
// Cryptography Intrinsic
- def : Pat<(v1024i1 (int_ppc_mma_dmxxshapad v1024i1:$ATi, v16i8:$XB, timm:$ID,
- timm:$E, timm:$BL)),
+ def : Pat<(v1024i1 (int_ppc_mma_dmxxshapad v1024i1:$ATi, v16i8:$XB,
+ u2imm_timm:$ID, u1imm_timm:$E, u2imm_timm:$BL)),
(DMXXSHAPAD $ATi, RCCp.BToVSRC, $ID, $E, $BL)>;
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index eaf1628a0889b..fcbc1cec375ee 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -780,9 +780,6 @@ def getFPAs64BitIntLo : SDNodeXForm<fpimm, [{
return CurDAG->getTargetConstant(Lo, SDLoc(N), MVT::i32);
}]>;
-def imm34 : PatLeaf<(imm), [{
- return isInt<34>(N->getSExtValue());
-}]>;
def getImmAs64BitInt : SDNodeXForm<imm, [{
return getI64Imm(N->getSExtValue(), SDLoc(N));
@@ -2167,13 +2164,13 @@ def LWAT_PSEUDO : PPCCustomInserterPseudo<
(outs gprc:$dst),
(ins ptr_rc_nor0:$ptr, gprc:$val, u5imm:$fc),
"#LWAT_PSEUDO",
- [(set i32:$dst, (int_ppc_amo_lwat ptr_rc_nor0:$ptr, gprc:$val, timm:$fc))]>;
+ [(set i32:$dst, (int_ppc_amo_lwat ptr_rc_nor0:$ptr, gprc:$val, u5imm_timm:$fc))]>;
def LWAT_COND_PSEUDO : PPCCustomInserterPseudo <
(outs gprc:$dst),
(ins ptr_rc_nor0:$ptr, u5imm:$fc),
"#LWAT_COND_PSEUDO",
- [(set i32:$dst, (int_ppc_amo_lwat_cond ptr_rc_nor0:$ptr, timm:$fc))]>;
+ [(set i32:$dst, (int_ppc_amo_lwat_cond ptr_rc_nor0:$ptr, u5imm_timm:$fc))]>;
let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {
def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),
@@ -2191,7 +2188,7 @@ def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$RST, (memrr $RA, $RB):$add
let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
def STWAT : XForm_base_r3xo_memOp<31, 710, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, u5imm:$RB),
"stwat $RST, $RA, $RB", IIC_LdStStore,
- [(PPCstat i32:$RST, ptr_rc_nor0:$RA, timm:$RB)]>,
+ [(PPCstat i32:$RST, ptr_rc_nor0:$RA, u5imm_timm:$RB)]>,
Requires<[IsISA3_0]>;
let isTrap = 1, hasCtrlDep = 1 in
@@ -3093,11 +3090,11 @@ let Uses = [RM], mayRaiseFPException = 1 in {
let hasSideEffects = 1, Defs = [RM] in {
def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
"mtfsb0 $FM", IIC_IntMTFSB0,
- [(int_ppc_mtfsb0 timm:$FM)]>,
+ [(int_ppc_mtfsb0 u5imm_timm:$FM)]>,
PPC970_DGroup_Single, PPC970_Unit_FPU;
def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
"mtfsb1 $FM", IIC_IntMTFSB0,
- [(int_ppc_mtfsb1 timm:$FM)]>,
+ [(int_ppc_mtfsb1 u5imm_timm:$FM)]>,
PPC970_DGroup_Single, PPC970_Unit_FPU;
}
@@ -4584,7 +4581,7 @@ def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
let Predicates = [HasFPU] in {
let Defs = [RM], hasSideEffects = 1 in {
let isCodeGenOnly = 1,
- Pattern = [(int_ppc_mtfsfi timm:$BF, timm:$U)], W = 0 in
+ Pattern = [(int_ppc_mtfsfi u3imm_timm:$BF, u4imm_timm:$U)], W = 0 in
def MTFSFIb : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U),
"mtfsfi $BF, $U", IIC_IntMFFS>;
def MTFSFI : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, i32imm:$W),
diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td
index 1b03a3db7d112..fdea9c5a4e0ba 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrP10.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td
@@ -657,18 +657,18 @@ def RCCp {
let Predicates = [PrefixInstrs] in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm PADDI8 :
- MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc_nox0:$RA, s34imm:$SI),
- (ins immZero:$RA, s34imm_pcrel:$SI),
+ MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc_nox0:$RA, s34imm64:$SI),
+ (ins immZero:$RA, s34imm64_pcrel:$SI),
"paddi $RT, $RA, $SI", IIC_LdStLFD>;
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
- (ins s34imm:$SI),
+ (ins s34imm64:$SI),
"pli $RT, $SI", IIC_IntSimple, []>;
}
}
defm PADDI :
MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc_nor0:$RA, s34imm:$SI),
- (ins immZero:$RA, s34imm_pcrel:$SI),
+ (ins immZero:$RA, s34imm64_pcrel:$SI),
"paddi $RT, $RA, $SI", IIC_LdStLFD>;
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
@@ -681,59 +681,59 @@ let Predicates = [PrefixInstrs] in {
defm PLBZ8 :
MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D), "plbz $RST, $addr",
+ (ins s34imm64_pcrel:$D), "plbz $RST, $addr",
"plbz $RST, $D", IIC_LdStLFD>;
defm PLHZ8 :
MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D), "plhz $RST, $addr",
+ (ins s34imm64_pcrel:$D), "plhz $RST, $addr",
"plhz $RST, $D", IIC_LdStLFD>;
defm PLHA8 :
MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D), "plha $RST, $addr",
+ (ins s34imm64_pcrel:$D), "plha $RST, $addr",
"plha $RST, $D", IIC_LdStLFD>;
defm PLWA8 :
8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D),
+ (ins s34imm64_pcrel:$D),
"plwa $RST, $addr", "plwa $RST, $D", IIC_LdStLFD>;
defm PLWZ8 :
MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D), "plwz $RST, $addr",
+ (ins s34imm64_pcrel:$D), "plwz $RST, $addr",
"plwz $RST, $D", IIC_LdStLFD>;
}
defm PLBZ :
MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D), "plbz $RST, $addr",
+ (ins s34imm64_pcrel:$D), "plbz $RST, $addr",
"plbz $RST, $D", IIC_LdStLFD>;
defm PLHZ :
MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D), "plhz $RST, $addr",
+ (ins s34imm64_pcrel:$D), "plhz $RST, $addr",
"plhz $RST, $D", IIC_LdStLFD>;
defm PLHA :
MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D), "plha $RST, $addr",
+ (ins s34imm64_pcrel:$D), "plha $RST, $addr",
"plha $RST, $D", IIC_LdStLFD>;
defm PLWZ :
MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D), "plwz $RST, $addr",
+ (ins s34imm64_pcrel:$D), "plwz $RST, $addr",
"plwz $RST, $D", IIC_LdStLFD>;
defm PLWA :
8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D),
+ (ins s34imm64_pcrel:$D),
"plwa $RST, $addr", "plwa $RST, $D",
IIC_LdStLFD>;
defm PLD :
8LS_DForm_R_SI34_RTA5_MEM_p<57, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D),
+ (ins s34imm64_pcrel:$D),
"pld $RST, $addr", "pld $RST, $D",
IIC_LdStLFD>;
}
@@ -743,38 +743,38 @@ let Predicates = [PrefixInstrs] in {
defm PSTB8 :
MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
(ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),
- (ins g8rc:$RST, s34imm_pcrel:$D),
+ (ins g8rc:$RST, s34imm64_pcrel:$D),
"pstb $RST, $addr", "pstb $RST, $D", IIC_LdStLFD>;
defm PSTH8 :
MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
(ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),
- (ins g8rc:$RST, s34imm_pcrel:$D),
+ (ins g8rc:$RST, s34imm64_pcrel:$D),
"psth $RST, $addr", "psth $RST, $D", IIC_LdStLFD>;
defm PSTW8 :
MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
(ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),
- (ins g8rc:$RST, s34imm_pcrel:$D),
+ (ins g8rc:$RST, s34imm64_pcrel:$D),
"pstw $RST, $addr", "pstw $RST, $D", IIC_LdStLFD>;
}
defm PSTB :
MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr),
(ins gprc:$RST, (memri34_pcrel $D, $RA):$addr),
- (ins gprc:$RST, s34imm_pcrel:$D),
+ (ins gprc:$RST, s34imm64_pcrel:$D),
"pstb $RST, $addr", "pstb $RST, $D", IIC_LdStLFD>;
defm PSTH :
MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr),
(ins gprc:$RST, (memri34_pcrel $D, $RA):$addr),
- (ins gprc:$RST, s34imm_pcrel:$D),
+ (ins gprc:$RST, s34imm64_pcrel:$D),
"psth $RST, $addr", "psth $RST, $D", IIC_LdStLFD>;
defm PSTW :
MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins gprc:$RST, (memri34 $D, $RA):$addr),
(ins gprc:$RST, (memri34_pcrel $D, $RA):$addr),
- (ins gprc:$RST, s34imm_pcrel:$D),
+ (ins gprc:$RST, s34imm64_pcrel:$D),
"pstw $RST, $addr", "pstw $RST, $D", IIC_LdStLFD>;
defm PSTD :
8LS_DForm_R_SI34_RTA5_MEM_p<61, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
(ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),
- (ins g8rc:$RST, s34imm_pcrel:$D),
+ (ins g8rc:$RST, s34imm64_pcrel:$D),
"pstd $RST, $addr", "pstd $RST, $D", IIC_LdStLFD>;
}
}
@@ -784,24 +784,24 @@ let Predicates = [PrefixInstrs, HasFPU] in {
defm PLFS :
MLS_DForm_R_SI34_RTA5_MEM_p<48, (outs f4rc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D), "plfs $RST, $addr",
+ (ins s34imm64_pcrel:$D), "plfs $RST, $addr",
"plfs $RST, $D", IIC_LdStLFD>;
defm PLFD :
MLS_DForm_R_SI34_RTA5_MEM_p<50, (outs f8rc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D), "plfd $RST, $addr",
+ (ins s34imm64_pcrel:$D), "plfd $RST, $addr",
"plfd $RST, $D", IIC_LdStLFD>;
}
let mayStore = 1, mayLoad = 0 in {
defm PSTFS :
MLS_DForm_R_SI34_RTA5_MEM_p<52, (outs), (ins f4rc:$RST, (memri34 $D, $RA):$addr),
(ins f4rc:$RST, (memri34_pcrel $D, $RA):$addr),
- (ins f4rc:$RST, s34imm_pcrel:$D),
+ (ins f4rc:$RST, s34imm64_pcrel:$D),
"pstfs $RST, $addr", "pstfs $RST, $D", IIC_LdStLFD>;
defm PSTFD :
MLS_DForm_R_SI34_RTA5_MEM_p<54, (outs), (ins f8rc:$RST, (memri34 $D, $RA):$addr),
(ins f8rc:$RST, (memri34_pcrel $D, $RA):$addr),
- (ins f8rc:$RST, s34imm_pcrel:$D),
+ (ins f8rc:$RST, s34imm64_pcrel:$D),
"pstfd $RST, $addr", "pstfd $RST, $D", IIC_LdStLFD>;
}
}
@@ -811,18 +811,18 @@ let Predicates = [PrefixInstrs, HasP10Vector] in {
defm PLXV :
8LS_DForm_R_SI34_XT6_RA5_MEM_p<25, (outs vsrc:$XST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D),
+ (ins s34imm64_pcrel:$D),
"plxv $XST, $addr", "plxv $XST, $D", IIC_LdStLFD>;
defm PLXSSP :
8LS_DForm_R_SI34_RTA5_MEM_p<43, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D),
+ (ins s34imm64_pcrel:$D),
"plxssp $RST, $addr", "plxssp $RST, $D",
IIC_LdStLFD>;
defm PLXSD :
8LS_DForm_R_SI34_RTA5_MEM_p<42, (outs vfrc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D),
+ (ins s34imm64_pcrel:$D),
"plxsd $RST, $addr", "plxsd $RST, $D",
IIC_LdStLFD>;
}
@@ -830,17 +830,17 @@ let Predicates = [PrefixInstrs, HasP10Vector] in {
defm PSTXV :
8LS_DForm_R_SI34_XT6_RA5_MEM_p<27, (outs), (ins vsrc:$XST, (memri34 $D, $RA):$addr),
(ins vsrc:$XST, (memri34_pcrel $D, $RA):$addr),
- (ins vsrc:$XST, s34imm_pcrel:$D),
+ (ins vsrc:$XST, s34imm64_pcrel:$D),
"pstxv $XST, $addr", "pstxv $XST, $D", IIC_LdStLFD>;
defm PSTXSSP :
8LS_DForm_R_SI34_RTA5_MEM_p<47, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),
(ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),
- (ins vfrc:$RST, s34imm_pcrel:$D),
+ (ins vfrc:$RST, s34imm64_pcrel:$D),
"pstxssp $RST, $addr", "pstxssp $RST, $D", IIC_LdStLFD>;
defm PSTXSD :
8LS_DForm_R_SI34_RTA5_MEM_p<46, (outs), (ins vfrc:$RST, (memri34 $D, $RA):$addr),
(ins vfrc:$RST, (memri34_pcrel $D, $RA):$addr),
- (ins vfrc:$RST, s34imm_pcrel:$D),
+ (ins vfrc:$RST, s34imm64_pcrel:$D),
"pstxsd $RST, $addr", "pstxsd $RST, $D", IIC_LdStLFD>;
}
def XXPERMX :
@@ -1189,7 +1189,7 @@ let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs, H
defm PLXVP :
8LS_DForm_R_XTp5_SI34_MEM_p<58, (outs vsrprc:$XTp), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D),
+ (ins s34imm64_pcrel:$D),
"plxvp $XTp, $addr", "plxvp $XTp, $D",
IIC_LdStLFD>;
}
@@ -1198,7 +1198,7 @@ let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs, H
defm PSTXVP :
8LS_DForm_R_XTp5_SI34_MEM_p<62, (outs), (ins vsrprc:$XTp, (memri34 $D, $RA):$addr),
(ins vsrprc:$XTp, (memri34_pcrel $D, $RA):$addr),
- (ins vsrprc:$XTp, s34imm_pcrel:$D),
+ (ins vsrprc:$XTp, s34imm64_pcrel:$D),
"pstxvp $XTp, $addr", "pstxvp $XTp, $D", IIC_LdStLFD>;
}
@@ -1448,15 +1448,15 @@ let Predicates = [IsISA3_1] in {
[(set v16i8:$VRT,
(int_ppc_altivec_vsldbi v16i8:$VRA,
v16i8:$VRB,
- timm:$SD))]>;
+ u3imm_timm:$SD))]>;
def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT),
(ins vrrc:$VRA, vrrc:$VRB, u3imm:$SD),
"vsrdbi $VRT, $VRA, $VRB, $SD",
IIC_VecGeneral,
[(set v16i8:$VRT,
(int_ppc_altivec_vsrdbi v16i8:$VRA,
- v16i8:$VRB,
- timm:$SD))]>;
+ v16i8:$VRB,
+ u3imm_timm:$SD))]>;
defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$VT), (ins vrrc:$VB),
"vstribr", "$VT, $VB", IIC_VecGeneral,
[(set v16i8:$VT,
@@ -1477,13 +1477,13 @@ let Predicates = [IsISA3_1] in {
VXForm_1<207, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, gprc:$VB),
"vinsw $VD, $VB, $VA", IIC_VecGeneral,
[(set v4i32:$VD,
- (int_ppc_altivec_vinsw v4i32:$VDi, i32:$VB, timm:$VA))]>,
+ (int_ppc_altivec_vinsw v4i32:$VDi, i32:$VB, u4imm_timm:$VA))]>,
RegConstraint<"$VDi = $VD">;
def VINSD :
VXForm_1<463, (outs vrrc:$VD), (ins vrrc:$VDi, u4imm:$VA, g8rc:$VB),
"vinsd $VD, $VB, $VA", IIC_VecGeneral,
[(set v2i64:$VD,
- (int_ppc_altivec_vinsd v2i64:$VDi, i64:$VB, timm:$VA))]>,
+ (int_ppc_altivec_vinsd v2i64:$VDi, i64:$VB, u4imm_timm:$VA))]>,
RegConstraint<"$VDi = $VD">;
def VINSBVLX :
VXForm_VTB5_RA5_ins<15, "vinsbvlx",
@@ -1629,22 +1629,22 @@ let Predicates = [IsISA3_1] in {
(ins vrrc:$VB, u1imm:$MP),
"vcntmbb $RD, $VB, $MP", IIC_VecGeneral,
[(set i64:$RD, (int_ppc_altivec_vcntmbb
- v16i8:$VB, timm:$MP))]>;
+ v16i8:$VB, u1imm_timm:$MP))]>;
def VCNTMBH : VXForm_RD5_MP_VB5<1602, 13, (outs g8rc:$RD),
(ins vrrc:$VB, u1imm:$MP),
"vcntmbh $RD, $VB, $MP", IIC_VecGeneral,
[(set i64:$RD, (int_ppc_altivec_vcntmbh
- v8i16:$VB, timm:$MP))]>;
+ v8i16:$VB, u1imm_timm:$MP))]>;
def VCNTMBW : VXForm_RD5_MP_VB5<1602, 14, (outs g8rc:$RD),
(ins vrrc:$VB, u1imm:$MP),
"vcntmbw $RD, $VB, $MP", IIC_VecGeneral,
[(set i64:$RD, (int_ppc_altivec_vcntmbw
- v4i32:$VB, timm:$MP))]>;
+ v4i32:$VB, u1imm_timm:$MP))]>;
def VCNTMBD : VXForm_RD5_MP_VB5<1602, 15, (outs g8rc:$RD),
(ins vrrc:$VB, u1imm:$MP),
"vcntmbd $RD, $VB, $MP", IIC_VecGeneral,
[(set i64:$RD, (int_ppc_altivec_vcntmbd
- v2i64:$VB, timm:$MP))]>;
+ v2i64:$VB, u1imm_timm:$MP))]>;
def VEXTDUBVLX : VAForm_1a<24, (outs vrrc:$RT),
(ins vrrc:$RA, vrrc:$RB, gprc:$RC),
"vextdubvlx $RT, $RA, $RB, $RC",
@@ -1730,7 +1730,7 @@ let Predicates = [IsISA3_1] in {
def VGNB : VXForm_RD5_N3_VB5<1228, (outs g8rc:$RD), (ins vrrc:$VB, u3imm:$N),
"vgnb $RD, $VB, $N", IIC_VecGeneral,
[(set i64:$RD,
- (int_ppc_altivec_vgnb v1i128:$VB, timm:$N))]>;
+ (int_ppc_altivec_vgnb v1i128:$VB, u3imm_timm:$N))]>;
def CFUGED : XForm_6<31, 220, (outs g8rc:$RA), (ins g8rc:$RST, g8rc:$RB),
"cfuged $RA, $RST, $RB", IIC_IntGeneral,
[(set i64:$RA, (int_ppc_cfuged i64:$RST, i64:$RB))]>;
@@ -1739,7 +1739,7 @@ let Predicates = [IsISA3_1] in {
vsrc:$XC, u8imm:$IMM),
"xxeval $XT, $XA, $XB, $XC, $IMM", IIC_VecGeneral,
[(set v2i64:$XT, (int_ppc_vsx_xxeval v2i64:$XA,
- v2i64:$XB, v2i64:$XC, timm:$IMM))]>;
+ v2i64:$XB, v2i64:$XC, u8imm_timm:$IMM))]>;
def VCLZDM : VXForm_1<1924, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
"vclzdm $VD, $VA, $VB", IIC_VecGeneral,
[(set v2i64:$VD,
@@ -2760,9 +2760,9 @@ let Predicates = [PrefixInstrs, HasP10Vector] in {
}
- def : Pat<(i32 imm34:$imm), (PLI (getImmAs64BitInt imm:$imm))>;
- def : Pat<(i64 imm34:$imm), (PLI8 (getImmAs64BitInt imm:$imm))>;
- def : Pat<(v16i8 (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C, timm:$D)),
+ def : Pat<(i32 s34imm_pat:$imm), (PLI (getImmAs64BitInt imm:$imm))>;
+ def : Pat<(i64 s34imm64_pat:$imm), (PLI8 (getImmAs64BitInt imm:$imm))>;
+ def : Pat<(v16i8 (int_ppc_vsx_xxpermx v16i8:$A, v16i8:$B, v16i8:$C, u3imm_timm:$D)),
(COPY_TO_REGCLASS (XXPERMX (COPY_TO_REGCLASS $A, VSRC),
(COPY_TO_REGCLASS $B, VSRC),
(COPY_TO_REGCLASS $C, VSRC), $D), VSRC)>;
@@ -2964,26 +2964,26 @@ let Predicates = [IsISA3_1] in {
def : InstAlias<"stcisync", (SYNCP10 0, 2)>;
def : InstAlias<"stsync", (SYNCP10 0, 3)>;
- def : InstAlias<"paddi $RT, $RA, $SI", (PADDI8 g8rc:$RT, g8rc_nox0:$RA, s34imm:$SI)>;
+ def : InstAlias<"paddi $RT, $RA, $SI", (PADDI8 g8rc:$RT, g8rc_nox0:$RA, s34imm64:$SI)>;
}
let Predicates = [IsISA3_1, PrefixInstrs], isAsmParserOnly = 1, hasNoSchedulingInfo = 1 in {
let Interpretation64Bit = 1 in {
def PLA8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
- (ins g8rc_nox0:$RA, s34imm:$SI),
+ (ins g8rc_nox0:$RA, s34imm64:$SI),
"pla $RT, ${SI} ${RA}", IIC_IntSimple, []>, MemriOp;
def PLA8pc : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
- (ins s34imm_pcrel:$SI),
+ (ins s34imm64_pcrel:$SI),
"pla $RT, $SI", IIC_IntSimple, []>, isPCRel;
}
def PSUBI : PPCAsmPseudo<"psubi $RT, $RA, $SI",
- (ins g8rc:$RT, g8rc_nox0:$RA, s34imm:$SI)>;
+ (ins g8rc:$RT, g8rc_nox0:$RA, s34imm64:$SI)>;
def PLA : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
- (ins gprc_nor0:$RA, s34imm:$SI),
+ (ins gprc_nor0:$RA, s34imm64:$SI),
"pla $RT, ${SI} ${RA}", IIC_IntSimple, []>, MemriOp;
def PLApc : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
- (ins s34imm_pcrel:$SI),
+ (ins s34imm64_pcrel:$SI),
"pla $RT, $SI", IIC_IntSimple, []>, isPCRel;
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
index 01cc8059f6924..81ab59657c71e 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -1657,12 +1657,14 @@ let Predicates = [HasVSX, HasP9Vector] in {
(outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB),
"xvtstdcsp $XT, $XB, $DCMX", IIC_VecFP,
[(set v4i32: $XT,
- (int_ppc_vsx_xvtstdcsp v4f32:$XB, timm:$DCMX))]>;
+ (int_ppc_vsx_xvtstdcsp v4f32:$XB,
+ u7imm_timm:$DCMX))]>;
def XVTSTDCDP : XX2_RD6_DCMX7_RS6<60, 15, 5,
(outs vsrc:$XT), (ins u7imm:$DCMX, vsrc:$XB),
"xvtstdcdp $XT, $XB, $DCMX", IIC_VecFP,
[(set v2i64: $XT,
- (int_ppc_vsx_xvtstdcdp v2f64:$XB, timm:$DCMX))]>;
+ (int_ppc_vsx_xvtstdcdp v2f64:$XB,
+ u7imm_timm:$DCMX))]>;
// Maximum/Minimum Type-C/Type-J DP
let mayRaiseFPException = 1 in {
diff --git a/llvm/lib/Target/PowerPC/PPCOperands.td b/llvm/lib/Target/PowerPC/PPCOperands.td
new file mode 100644
index 0000000000000..824397c6d03d7
--- /dev/null
+++ b/llvm/lib/Target/PowerPC/PPCOperands.td
@@ -0,0 +1,215 @@
+//===-- PPCOperands.td - PowerPC instruction operands -------*- tablegen -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines PowerPC instruction operands, including immediate
+// operands and addressing modes.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Immediate operand base classes
+//===----------------------------------------------------------------------===//
+
+// Base class for immediate AsmOperandClass definitions.
+class ImmediateAsmOperand<string predicate, string render="addImmOperands">
+: AsmOperandClass {
+ let Name = NAME;
+ let PredicateMethod = predicate;
+ let RenderMethod = render;
+}
+
+// Base class for immediate operands with optional encoder.
+class ImmediateOp<ValueType vt, string asmop, int width, bit is_signed = 0,
+ string encoder = "", string decoder = ""> : Operand<vt> {
+ let PrintMethod = "print"#asmop#"Operand";
+ let ParserMatchClass = !cast<AsmOperandClass>(asmop);
+ let OperandType = "OPERAND_IMMEDIATE";
+
+ // Set decoder method based on signedness if not explicitly provided
+ let DecoderMethod = !if(!eq(decoder, ""),
+ !if(is_signed,
+ "decodeSImmOperand<"#width#">",
+ "decodeUImmOperand<"#width#">"),
+ decoder);
+
+ // Set encoder method if provided
+ let EncoderMethod = !if(!eq(encoder, ""),
+ "",
+ "getImmEncoding<" # encoder # ">");
+}
+
+//===----------------------------------------------------------------------===//
+// Multiclasses for complete immediate definitions
+// (AsmOperand + Operand + ImmLeaf).
+//===----------------------------------------------------------------------===//
+
+// Helper multiclass that generates operand + patterns together while keeping
+// them as separate definitions for GlobalISel compatibility.
+multiclass ImmOpWithPatterns<ValueType vt, string asmop, int width,
+ bit is_signed, code pred, SDNodeXForm xform,
+ string encoder = ""> {
+ // Operand definition (for instruction operands)
+ def "" : ImmediateOp<vt, asmop, width, is_signed, encoder>;
+
+ // ImmLeaf for imm nodes (for DAG pattern matching)
+ def _pat : ImmLeaf<vt, pred, xform>;
+
+ // TImmLeaf for timm nodes (for target-specific pattern matching, e.g., intrinsics)
+ def _timm : TImmLeaf<vt, pred, xform>;
+}
+
+// Creates Operand and separate ImmLeaf definitions for unsigned immediates.
+multiclass UnsignedImmediate<ValueType vt, code pred, SDNodeXForm xform,
+ string asmop, int width, string encoder = "">
+ : ImmOpWithPatterns<vt, asmop, width, 0, pred, xform, encoder>;
+
+// Creates Operand and separate ImmLeaf definitions for signed immediates.
+multiclass SignedImmediate<ValueType vt, code pred, SDNodeXForm xform,
+ string asmop, int width, string encoder = "">
+ : ImmOpWithPatterns<vt, asmop, width, 1, pred, xform, encoder>;
+
+// Multiclass for signed immediate operands with both regular and
+// PC-relative versions.
+multiclass SignedImmediateWithPCRel<ValueType vt, code pred,
+ SDNodeXForm xform, string asmop,
+ int width, string fixup_imm,
+ string fixup_pcrel>
+ : SignedImmediate<vt, pred, xform, asmop, width, fixup_imm> {
+ // PC-relative immediate: instantiate SignedImmediate with PC-relative fixup
+ defm _pcrel : SignedImmediate<vt, pred, xform, asmop, width, fixup_pcrel>;
+}
+
+//===----------------------------------------------------------------------===//
+// Immediate AsmOperand definitions
+//===----------------------------------------------------------------------===//
+def U1Imm : ImmediateAsmOperand<"isUImm<1>">;
+def U2Imm : ImmediateAsmOperand<"isUImm<2>">;
+def U3Imm : ImmediateAsmOperand<"isUImm<3>">;
+def U4Imm : ImmediateAsmOperand<"isUImm<4>">;
+def U5Imm : ImmediateAsmOperand<"isUImm<5>">;
+def U6Imm : ImmediateAsmOperand<"isUImm<6>">;
+def U7Imm : ImmediateAsmOperand<"isUImm<7>">;
+def U8Imm : ImmediateAsmOperand<"isUImm<8>">;
+def U10Imm : ImmediateAsmOperand<"isUImm<10>">;
+def U12Imm : ImmediateAsmOperand<"isUImm<12>">;
+def S5Imm : ImmediateAsmOperand<"isSImm<5>">;
+
+// Special cases that have custom predicat and/or render method.
+def ATBitsAsHint : ImmediateAsmOperand<"isATBitsAsHint">; //Predicate always fails.
+def ImmZero : ImmediateAsmOperand<"isImmZero">;
+def U16Imm : ImmediateAsmOperand<"isU16Imm","addU16ImmOperands">;
+def S16Imm : ImmediateAsmOperand<"isS16Imm","addS16ImmOperands">;
+def S17Imm : ImmediateAsmOperand<"isS17Imm","addS16ImmOperands">;
+def S32Imm : ImmediateAsmOperand<"isS32Imm">;
+def S34Imm : ImmediateAsmOperand<"isS34Imm">;
+
+//===----------------------------------------------------------------------===//
+// i32 immediate operands
+//===----------------------------------------------------------------------===//
+
+defm u1imm : UnsignedImmediate<i32,
+ [{ return isUInt<1>(Imm); }], NOOP_SDNodeXForm,
+ "U1Imm", 1>;
+defm u2imm : UnsignedImmediate<i32,
+ [{ return isUInt<2>(Imm); }], NOOP_SDNodeXForm,
+ "U2Imm", 2>;
+defm u3imm : UnsignedImmediate<i32,
+ [{ return isUInt<3>(Imm); }], NOOP_SDNodeXForm,
+ "U3Imm", 3>;
+defm u4imm : UnsignedImmediate<i32,
+ [{ return isUInt<4>(Imm); }], NOOP_SDNodeXForm,
+ "U4Imm", 4>;
+defm u5imm : UnsignedImmediate<i32,
+ [{ return isUInt<5>(Imm); }], NOOP_SDNodeXForm,
+ "U5Imm", 5>;
+defm u6imm : UnsignedImmediate<i32,
+ [{ return isUInt<6>(Imm); }], NOOP_SDNodeXForm,
+ "U6Imm", 6>;
+defm u7imm : UnsignedImmediate<i32,
+ [{ return isUInt<7>(Imm); }], NOOP_SDNodeXForm,
+ "U7Imm", 7>;
+defm u8imm : UnsignedImmediate<i32,
+ [{ return isUInt<8>(Imm); }], NOOP_SDNodeXForm,
+ "U8Imm", 8>;
+defm u10imm : UnsignedImmediate<i32,
+ [{ return isUInt<10>(Imm); }], NOOP_SDNodeXForm,
+ "U10Imm", 10>;
+defm u12imm : UnsignedImmediate<i32,
+ [{ return isUInt<12>(Imm); }], NOOP_SDNodeXForm,
+ "U12Imm", 12>;
+
+defm s5imm : SignedImmediate<i32,
+ [{ return isInt<5>(Imm); }], NOOP_SDNodeXForm,
+ "S5Imm", 5>;
+
+defm s34imm : SignedImmediate<i32,
+ [{ return isInt<34>(Imm); }], NOOP_SDNodeXForm,
+ "S34Imm", 34, "PPC::fixup_ppc_imm34">;
+
+//===----------------------------------------------------------------------===//
+// i64 immediate operands
+//===----------------------------------------------------------------------===//
+
+defm s32imm64 : SignedImmediateWithPCRel<i64,
+ [{ return isInt<32>(Imm); }], NOOP_SDNodeXForm,
+ "S32Imm", 32, "PPC::fixup_ppc_imm32", "PPC::fixup_ppc_pcrel32">;
+defm s34imm64 : SignedImmediateWithPCRel<i64,
+ [{ return isInt<34>(Imm); }], NOOP_SDNodeXForm,
+ "S34Imm", 34, "PPC::fixup_ppc_imm34", "PPC::fixup_ppc_pcrel34">;
+
+//===----------------------------------------------------------------------===//
+// Special case immediate operands
+//===----------------------------------------------------------------------===//
+
+// immZero represents a hardcoded zero register encoding, it is NOT used in DAG
+// patterns. It is only used as an instruction operand for assembly/disassembly,
+// specifically to represent a hardcoded zero register value in PC-relative
+// addressing modes.
+def immZero : Operand<i32> {
+ let PrintMethod = "printImmZeroOperand";
+ let ParserMatchClass = ImmZero;
+ let DecoderMethod = "decodeImmZeroOperand";
+ let OperandType = "OPERAND_IMMEDIATE";
+}
+
+// atimm is used to represent branch prediction hints, not a general immediate
+// value. It's a 2-bit AT (Address Translation) field in PPC branch instructions
+// and is an assembly-only operand that prints as `+` or `-` symbols, not
+// numeric values.
+def atimm : Operand<i32> {
+ let PrintMethod = "printATBitsAsHint";
+ let ParserMatchClass = ATBitsAsHint;
+ let OperandType = "OPERAND_IMMEDIATE";
+}
+
+// Special cases: s16imm and u16imm have custom encoder methods.
+defm s16imm : SignedImmediate<i32,
+ [{ return isInt<16>(Imm); }], NOOP_SDNodeXForm,
+ "S16Imm", 16, "PPC::fixup_ppc_half16">;
+defm u16imm : UnsignedImmediate<i32,
+ [{ return isUInt<16>(Imm); }], NOOP_SDNodeXForm,
+ "U16Imm", 16, "PPC::fixup_ppc_half16">;
+
+// s16imm64 uses imm64SExt16 pattern to match the operand type.
+def s16imm64 : ImmediateOp<i64, "S16Imm", 16, 1, "PPC::fixup_ppc_half16">;
+
+// u16imm64 uses two
diff erent patterns depending on the instruction context:
+// * immZExt16 - For low 16-bit immediates
+// * imm16ShiftedZExt - For high 16-bit immediates (shifted)
+def u16imm64 : ImmediateOp<i64, "U16Imm", 16, 0, "PPC::fixup_ppc_half16">;
+
+// Special case: s17imm uses S16Imm print method but accepts wider range.
+// This operand type is used for addis/lis to allow the assembler parser
+// to accept immediates in the range -65536..65535 for compatibility
+// with the GNU assembler. The operand is treated as 16-bit otherwise.
+def s17imm : ImmediateOp<i32, "S17Imm", 16, 1, "PPC::fixup_ppc_half16"> {
+ let PrintMethod = "printS16ImmOperand";
+}
+def s17imm64 : ImmediateOp<i64, "S17Imm", 16, 1, "PPC::fixup_ppc_half16"> {
+ let PrintMethod = "printS16ImmOperand";
+}
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 5b9ce2400c7cb..3b8116eb8f095 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -9,6 +9,8 @@
//
//===----------------------------------------------------------------------===//
+include "PPCOperands.td"
+
let Namespace = "PPC" in {
def sub_lt : SubRegIndex<1>;
def sub_gt : SubRegIndex<1, 1>;
@@ -614,250 +616,6 @@ def spe4rc : RegisterOperand<GPRC> {
let ParserMatchClass = PPCRegSPE4RCAsmOperand;
}
-def PPCU1ImmAsmOperand : AsmOperandClass {
- let Name = "U1Imm";
- let PredicateMethod = "isUImm<1>";
- let RenderMethod = "addImmOperands";
-}
-def u1imm : Operand<i32> {
- let PrintMethod = "printU1ImmOperand";
- let ParserMatchClass = PPCU1ImmAsmOperand;
- let DecoderMethod = "decodeUImmOperand<1>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-
-def PPCU2ImmAsmOperand : AsmOperandClass {
- let Name = "U2Imm";
- let PredicateMethod = "isUImm<2>";
- let RenderMethod = "addImmOperands";
-}
-def u2imm : Operand<i32> {
- let PrintMethod = "printU2ImmOperand";
- let ParserMatchClass = PPCU2ImmAsmOperand;
- let DecoderMethod = "decodeUImmOperand<2>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-
-def PPCATBitsAsHintAsmOperand : AsmOperandClass {
- let Name = "ATBitsAsHint"; let PredicateMethod = "isATBitsAsHint";
- let RenderMethod = "addImmOperands"; // Irrelevant, predicate always fails.
-}
-def atimm : Operand<i32> {
- let PrintMethod = "printATBitsAsHint";
- let ParserMatchClass = PPCATBitsAsHintAsmOperand;
- let OperandType = "OPERAND_IMMEDIATE";
-}
-
-def PPCU3ImmAsmOperand : AsmOperandClass {
- let Name = "U3Imm";
- let PredicateMethod = "isUImm<3>";
- let RenderMethod = "addImmOperands";
-}
-def u3imm : Operand<i32> {
- let PrintMethod = "printU3ImmOperand";
- let ParserMatchClass = PPCU3ImmAsmOperand;
- let DecoderMethod = "decodeUImmOperand<3>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-
-def PPCU4ImmAsmOperand : AsmOperandClass {
- let Name = "U4Imm";
- let PredicateMethod = "isUImm<4>";
- let RenderMethod = "addImmOperands";
-}
-def u4imm : Operand<i32> {
- let PrintMethod = "printU4ImmOperand";
- let ParserMatchClass = PPCU4ImmAsmOperand;
- let DecoderMethod = "decodeUImmOperand<4>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-def PPCS5ImmAsmOperand : AsmOperandClass {
- let Name = "S5Imm";
- let PredicateMethod = "isSImm<5>";
- let RenderMethod = "addImmOperands";
-}
-def s5imm : Operand<i32> {
- let PrintMethod = "printS5ImmOperand";
- let ParserMatchClass = PPCS5ImmAsmOperand;
- let DecoderMethod = "decodeSImmOperand<5>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-def PPCU5ImmAsmOperand : AsmOperandClass {
- let Name = "U5Imm";
- let PredicateMethod = "isUImm<5>";
- let RenderMethod = "addImmOperands";
-}
-def u5imm : Operand<i32> {
- let PrintMethod = "printU5ImmOperand";
- let ParserMatchClass = PPCU5ImmAsmOperand;
- let DecoderMethod = "decodeUImmOperand<5>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-def PPCU6ImmAsmOperand : AsmOperandClass {
- let Name = "U6Imm";
- let PredicateMethod = "isUImm<6>";
- let RenderMethod = "addImmOperands";
-}
-def u6imm : Operand<i32> {
- let PrintMethod = "printU6ImmOperand";
- let ParserMatchClass = PPCU6ImmAsmOperand;
- let DecoderMethod = "decodeUImmOperand<6>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-def PPCU7ImmAsmOperand : AsmOperandClass {
- let Name = "U7Imm";
- let PredicateMethod = "isUImm<7>";
- let RenderMethod = "addImmOperands";
-}
-def u7imm : Operand<i32> {
- let PrintMethod = "printU7ImmOperand";
- let ParserMatchClass = PPCU7ImmAsmOperand;
- let DecoderMethod = "decodeUImmOperand<7>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-def PPCU8ImmAsmOperand : AsmOperandClass {
- let Name = "U8Imm";
- let PredicateMethod = "isUImm<8>";
- let RenderMethod = "addImmOperands";
-}
-def u8imm : Operand<i32> {
- let PrintMethod = "printU8ImmOperand";
- let ParserMatchClass = PPCU8ImmAsmOperand;
- let DecoderMethod = "decodeUImmOperand<8>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-def PPCU10ImmAsmOperand : AsmOperandClass {
- let Name = "U10Imm";
- let PredicateMethod = "isUImm<10>";
- let RenderMethod = "addImmOperands";
-}
-def u10imm : Operand<i32> {
- let PrintMethod = "printU10ImmOperand";
- let ParserMatchClass = PPCU10ImmAsmOperand;
- let DecoderMethod = "decodeUImmOperand<10>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-def PPCU12ImmAsmOperand : AsmOperandClass {
- let Name = "U12Imm";
- let PredicateMethod = "isUImm<12>";
- let RenderMethod = "addImmOperands";
-}
-def u12imm : Operand<i32> {
- let PrintMethod = "printU12ImmOperand";
- let ParserMatchClass = PPCU12ImmAsmOperand;
- let DecoderMethod = "decodeUImmOperand<12>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-def PPCS16ImmAsmOperand : AsmOperandClass {
- let Name = "S16Imm"; let PredicateMethod = "isS16Imm";
- let RenderMethod = "addS16ImmOperands";
-}
-def s16imm : Operand<i32> {
- let PrintMethod = "printS16ImmOperand";
- let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_half16>";
- let ParserMatchClass = PPCS16ImmAsmOperand;
- let DecoderMethod = "decodeSImmOperand<16>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-def s16imm64 : Operand<i64> {
- let PrintMethod = "printS16ImmOperand";
- let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_half16>";
- let ParserMatchClass = PPCS16ImmAsmOperand;
- let DecoderMethod = "decodeSImmOperand<16>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-def PPCU16ImmAsmOperand : AsmOperandClass {
- let Name = "U16Imm"; let PredicateMethod = "isU16Imm";
- let RenderMethod = "addU16ImmOperands";
-}
-def u16imm : Operand<i32> {
- let PrintMethod = "printU16ImmOperand";
- let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_half16>";
- let ParserMatchClass = PPCU16ImmAsmOperand;
- let DecoderMethod = "decodeUImmOperand<16>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-def u16imm64 : Operand<i64> {
- let PrintMethod = "printU16ImmOperand";
- let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_half16>";
- let ParserMatchClass = PPCU16ImmAsmOperand;
- let DecoderMethod = "decodeUImmOperand<16>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-def PPCS17ImmAsmOperand : AsmOperandClass {
- let Name = "S17Imm"; let PredicateMethod = "isS17Imm";
- let RenderMethod = "addS16ImmOperands";
-}
-def s17imm : Operand<i32> {
- // This operand type is used for addis/lis to allow the assembler parser
- // to accept immediates in the range -65536..65535 for compatibility with
- // the GNU assembler. The operand is treated as 16-bit otherwise.
- let PrintMethod = "printS16ImmOperand";
- let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_half16>";
- let ParserMatchClass = PPCS17ImmAsmOperand;
- let DecoderMethod = "decodeSImmOperand<16>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-def s17imm64 : Operand<i64> {
- // This operand type is used for addis/lis to allow the assembler parser
- // to accept immediates in the range -65536..65535 for compatibility with
- // the GNU assembler. The operand is treated as 16-bit otherwise.
- let PrintMethod = "printS16ImmOperand";
- let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_half16>";
- let ParserMatchClass = PPCS17ImmAsmOperand;
- let DecoderMethod = "decodeSImmOperand<16>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-def PPCS32ImmAsmOperand : AsmOperandClass {
- let Name = "S32Imm";
- let PredicateMethod = "isS32Imm";
- let RenderMethod = "addImmOperands";
-}
-def s32imm : Operand<i64> {
- let PrintMethod = "printS32ImmOperand";
- let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_imm32>";
- let ParserMatchClass = PPCS32ImmAsmOperand;
- let DecoderMethod = "decodeSImmOperand<32>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-def s32imm_pcrel : Operand<i64> {
- let PrintMethod = "printS32ImmOperand";
- let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_pcrel32>";
- let ParserMatchClass = PPCS32ImmAsmOperand;
- let DecoderMethod = "decodeSImmOperand<32>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-def PPCS34ImmAsmOperand : AsmOperandClass {
- let Name = "S34Imm";
- let PredicateMethod = "isS34Imm";
- let RenderMethod = "addImmOperands";
-}
-def s34imm : Operand<i64> {
- let PrintMethod = "printS34ImmOperand";
- let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_imm34>";
- let ParserMatchClass = PPCS34ImmAsmOperand;
- let DecoderMethod = "decodeSImmOperand<34>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-def s34imm_pcrel : Operand<i64> {
- let PrintMethod = "printS34ImmOperand";
- let EncoderMethod = "getImmEncoding<PPC::fixup_ppc_pcrel34>";
- let ParserMatchClass = PPCS34ImmAsmOperand;
- let DecoderMethod = "decodeSImmOperand<34>";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-def PPCImmZeroAsmOperand : AsmOperandClass {
- let Name = "ImmZero";
- let PredicateMethod = "isImmZero";
- let RenderMethod = "addImmOperands";
-}
-def immZero : Operand<i32> {
- let PrintMethod = "printImmZeroOperand";
- let ParserMatchClass = PPCImmZeroAsmOperand;
- let DecoderMethod = "decodeImmZeroOperand";
- let OperandType = "OPERAND_IMMEDIATE";
-}
-
def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
def fpimm0neg : PatLeaf<(fpimm), [{return N->isExactlyValue(-0.0);}]>;
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