[llvm] [NFC][CodeGen] Rewrite comment for `getSubRegisterClass` (PR #182339)

[Rahul Joshi via llvm-commits]

https://github.com/jurahul created https://github.com/llvm/llvm-project/pull/182339

Change the description of `getSubRegisterClass` to be more accurate. Additionally, reformat some existing comments to use '\p` to denote function parameters.

>From 9c8a4c1e865da05556138c5c9ff51cc0db83725a Mon Sep 17 00:00:00 2001
From: Rahul Joshi <rjoshi at nvidia.com>
Date: Thu, 19 Feb 2026 10:40:29 -0800
Subject: [PATCH] [NFC][CodeGen] Rewrite comment for `getSubRegisterClass`

Change the description of `getSubRegisterClass` to be more accurate.
Additionally, reformat some existing comments to use '\p` to denote
function parameters.
---
 .../include/llvm/CodeGen/TargetRegisterInfo.h | 23 +++++++++++--------
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index b69a91651e300..359be52f9a076 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -667,16 +667,16 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
   /// remove pseudo-registers that should be ignored).
   virtual void adjustStackMapLiveOutMask(uint32_t *Mask) const {}
 
-  /// Return a super-register of the specified register
-  /// Reg so its sub-register of index SubIdx is Reg.
+  /// Return a super-register of register \p Reg such that its sub-register of
+  /// index \p SubIdx is \p Reg.
   MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
                                  const TargetRegisterClass *RC) const {
     return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
   }
 
-  /// Return a subclass of the specified register
-  /// class A so that each register in it has a sub-register of the
-  /// specified sub-register index which is in the specified register class B.
+  /// Return a subclass of the register class \p A so that each register in it
+  /// has a sub-register of sub-register index \p Idx which is in the register
+  /// class \p B.
   ///
   /// TableGen will synthesize missing A sub-classes.
   virtual const TargetRegisterClass *
@@ -709,8 +709,8 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
     return findCommonRegClass(DefRC, DefSubReg, SrcRC, SrcSubReg) != nullptr;
   }
 
-  /// Returns the largest legal sub-class of RC that
-  /// supports the sub-register index Idx.
+  /// Returns the largest legal sub-class of \p RC that supports the
+  /// sub-register index \p Idx.
   /// If no such sub-class exists, return NULL.
   /// If all registers in RC already have an Idx sub-register, return RC.
   ///
@@ -727,8 +727,13 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
     return RC;
   }
 
-  /// Return a register class that can be used for a subregister copy from/into
-  /// \p SuperRC at \p SubRegIdx.
+  /// Returns the register class of all sub-registers of \p SuperRC obtained by
+  /// applying the sub-register index \p SubRegIdx.
+  ///
+  /// TableGen *may not* synthesize the missing sub-register classes, so this
+  /// function may return null even if SubRegIdx can be applied to all registers
+  /// in SuperRC, i.e., even if
+  // isSubRegValidForRegClass(SuperRC, SubRegIdx) is true.
   virtual const TargetRegisterClass *
   getSubRegisterClass(const TargetRegisterClass *SuperRC,
                       unsigned SubRegIdx) const {