[llvm] [PowerPC] Refactor immediate operand definitions (PR #179983)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Feb 19 10:20:31 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-powerpc
Author: Lei Huang (lei137)
<details>
<summary>Changes</summary>
Refactors PowerPC's immediate operand definitions using multiclasses
to reduce code duplication and improve maintainability.
Changes include:
- Established consistent naming: i32 versions without suffix, i64 versions with '64' suffix
- Predicate functions added to imm/timm nodes to verify immdiate values.
Assistance provided by AI.
---
Patch is 54.75 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/179983.diff
9 Files Affected:
- (modified) llvm/lib/Target/PowerPC/PPCInstr64Bit.td (+9-5)
- (modified) llvm/lib/Target/PowerPC/PPCInstrAltivec.td (+11-10)
- (modified) llvm/lib/Target/PowerPC/PPCInstrFuture.td (+4-4)
- (modified) llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td (+6-5)
- (modified) llvm/lib/Target/PowerPC/PPCInstrInfo.td (+6-9)
- (modified) llvm/lib/Target/PowerPC/PPCInstrP10.td (+54-54)
- (modified) llvm/lib/Target/PowerPC/PPCInstrVSX.td (+4-2)
- (added) llvm/lib/Target/PowerPC/PPCOperands.td (+215)
- (modified) llvm/lib/Target/PowerPC/PPCRegisterInfo.td (+2-244)
``````````diff
diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
index d4ce03c07663f..2b62654b08986 100644
--- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -338,13 +338,15 @@ def LDAT_PSEUDO : PPCCustomInserterPseudo<
(outs g8rc:$dst),
(ins ptr_rc_nor0:$ptr, g8rc:$val, u5imm:$fc),
"#LDAT_PSEUDO",
- [(set i64:$dst, (int_ppc_amo_ldat ptr_rc_nor0:$ptr, g8rc:$val, timm:$fc))]>;
+ [(set i64:$dst, (int_ppc_amo_ldat ptr_rc_nor0:$ptr, g8rc:$val,
+ u5imm_timm:$fc))]>;
def LDAT_COND_PSEUDO : PPCCustomInserterPseudo <
(outs g8rc:$dst),
(ins ptr_rc_nor0:$ptr, u5imm:$fc),
"#LDAT_COND_PSEUDO",
- [(set i64:$dst, (int_ppc_amo_ldat_cond ptr_rc_nor0:$ptr, timm:$fc))]>;
+ [(set i64:$dst, (int_ppc_amo_ldat_cond ptr_rc_nor0:$ptr,
+ u5imm_timm:$fc))]>;
let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {
def STDCX : XForm_1_memOp<31, 214, (outs), (ins g8rc:$RST, (memrr $RA, $RB):$addr),
@@ -412,9 +414,11 @@ def : Pat<(int_ppc_cmpxchg_i128 ForceXForm:$ptr,
g8rc:$new_hi))>;
let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
-def STDAT : XForm_base_r3xo_memOp<31, 742, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, u5imm:$RB),
+def STDAT : XForm_base_r3xo_memOp<31, 742, (outs),
+ (ins g8rc:$RST, ptr_rc_nor0:$RA, u5imm:$RB),
"stdat $RST, $RA, $RB", IIC_LdStStore,
- [(PPCstat i64:$RST, ptr_rc_nor0:$RA, timm:$RB)]>, isPPC64,
+ [(PPCstat i64:$RST, ptr_rc_nor0:$RA,
+ u5imm_timm:$RB)]>, isPPC64,
Requires<[IsISA3_0]>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
@@ -1823,7 +1827,7 @@ def ADDEX8 : Z23Form_RTAB5_CY2<31, 170, (outs g8rc:$RT),
(ins g8rc:$RA, g8rc:$RB, u2imm:$CY),
"addex $RT, $RA, $RB, $CY", IIC_IntGeneral,
[(set i64:$RT, (int_ppc_addex i64:$RA, i64:$RB,
- timm:$CY))]>;
+ u2imm_timm:$CY))]>;
//===----------------------------------------------------------------------===//
// Instruction Patterns
diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
index 461ab3a2851ab..156931a372136 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -343,7 +343,8 @@ class VXBX_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
class VXCR_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
: VXForm_CR<xo, (outs vrrc:$VD), (ins vrrc:$VA, u1imm:$ST, u4imm:$SIX),
!strconcat(opc, " $VD, $VA, $ST, $SIX"), IIC_VecFP,
- [(set Ty:$VD, (IntID Ty:$VA, timm:$ST, timm:$SIX))]>;
+ [(set Ty:$VD, (IntID Ty:$VA, u1imm_timm:$ST,
+ u4imm_timm:$SIX))]>;
//===----------------------------------------------------------------------===//
// Instruction Definitions.
@@ -533,19 +534,19 @@ def VANDC : VXForm_1<1092, (outs vrrc:$VD), (ins vrrc:$VA, vrrc:$VB),
def VCFSX : VXForm_1<842, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),
"vcfsx $VD, $VB, $VA", IIC_VecFP,
[(set v4f32:$VD,
- (int_ppc_altivec_vcfsx v4i32:$VB, timm:$VA))]>;
+ (int_ppc_altivec_vcfsx v4i32:$VB, u5imm_timm:$VA))]>;
def VCFUX : VXForm_1<778, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),
"vcfux $VD, $VB, $VA", IIC_VecFP,
[(set v4f32:$VD,
- (int_ppc_altivec_vcfux v4i32:$VB, timm:$VA))]>;
+ (int_ppc_altivec_vcfux v4i32:$VB, u5imm_timm:$VA))]>;
def VCTSXS : VXForm_1<970, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),
"vctsxs $VD, $VB, $VA", IIC_VecFP,
[(set v4i32:$VD,
- (int_ppc_altivec_vctsxs v4f32:$VB, timm:$VA))]>;
+ (int_ppc_altivec_vctsxs v4f32:$VB, u5imm_timm:$VA))]>;
def VCTUXS : VXForm_1<906, (outs vrrc:$VD), (ins u5imm:$VA, vrrc:$VB),
"vctuxs $VD, $VB, $VA", IIC_VecFP,
[(set v4i32:$VD,
- (int_ppc_altivec_vctuxs v4f32:$VB, timm:$VA))]>;
+ (int_ppc_altivec_vctuxs v4f32:$VB, u5imm_timm:$VA))]>;
// Defines with the UIM field set to 0 for floating-point
// to integer (fp_to_sint/fp_to_uint) conversions and integer
@@ -1397,9 +1398,9 @@ def VUPKLSW : VX2_Int_Ty2<1742, "vupklsw", int_ppc_altivec_vupklsw,
def BCDADD_rec : VX_VT5_VA5_VB5_PS1_XO9_o<1, "bcdadd." , []>;
def BCDSUB_rec : VX_VT5_VA5_VB5_PS1_XO9_o<65, "bcdsub." , []>;
-def : Pat<(v16i8 (int_ppc_bcdadd v16i8:$vA, v16i8:$vB, timm:$PS)),
+def : Pat<(v16i8 (int_ppc_bcdadd v16i8:$vA, v16i8:$vB, u1imm_timm:$PS)),
(BCDADD_rec $vA, $vB, $PS)>;
-def : Pat<(v16i8 (int_ppc_bcdsub v16i8:$vA, v16i8:$vB, timm:$PS)),
+def : Pat<(v16i8 (int_ppc_bcdsub v16i8:$vA, v16i8:$vB, u1imm_timm:$PS)),
(BCDSUB_rec $vA, $vB, $PS)>;
// Shuffle patterns for unary and swapped (LE) vector pack modulo.
@@ -1635,13 +1636,13 @@ class VX_VT5_EO5_VB5_XO9_o<bits<5> eo, bits<9> xo, string opc,
// Decimal Convert From/to National/Zoned/Signed-QWord
def BCDCFN_rec : VX_VT5_EO5_VB5_PS1_XO9_o<7, 385, "bcdcfn." ,
- [(set v16i8:$VD, (int_ppc_national2packed v16i8:$VB, timm:$PS))]>;
+ [(set v16i8:$VD, (int_ppc_national2packed v16i8:$VB, u1imm_timm:$PS))]>;
def BCDCFZ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<6, 385, "bcdcfz." ,
- [(set v16i8:$VD, (int_ppc_zoned2packed v16i8:$VB, timm:$PS))]>;
+ [(set v16i8:$VD, (int_ppc_zoned2packed v16i8:$VB, u1imm_timm:$PS))]>;
def BCDCTN_rec : VX_VT5_EO5_VB5_XO9_o <5, 385, "bcdctn." ,
[(set v16i8:$VD, (int_ppc_packed2national v16i8:$VB))]>;
def BCDCTZ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<4, 385, "bcdctz." ,
- [(set v16i8:$VD, (int_ppc_packed2zoned v16i8:$VB, timm:$PS))]>;
+ [(set v16i8:$VD, (int_ppc_packed2zoned v16i8:$VB, u1imm_timm:$PS))]>;
def BCDCFSQ_rec : VX_VT5_EO5_VB5_PS1_XO9_o<2, 385, "bcdcfsq.", []>;
def BCDCTSQ_rec : VX_VT5_EO5_VB5_XO9_o <0, 385, "bcdctsq.", []>;
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
index 39e6f4f139c11..eb56fea8c9888 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -380,13 +380,13 @@ let Predicates = [IsISAFuture] in {
let Predicates = [IsISAFuture, PrefixInstrs] in {
defm PADDIS : MLS_DForm_R_SI32_RTA5_p<15, (outs gprc:$RT),
- (ins gprc_nor0:$RA, s32imm:$SI),
- (ins immZero:$RA, s32imm_pcrel:$SI),
+ (ins gprc_nor0:$RA, s32imm64:$SI),
+ (ins immZero:$RA, s32imm64_pcrel:$SI),
"paddis $RT, $RA, $SI", IIC_LdStLFD>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in
defm PADDIS8 : MLS_DForm_R_SI32_RTA5_p<15, (outs g8rc:$RT),
- (ins g8rc_nox0:$RA, s32imm:$SI),
- (ins immZero:$RA, s32imm_pcrel:$SI),
+ (ins g8rc_nox0:$RA, s32imm64:$SI),
+ (ins immZero:$RA, s32imm64_pcrel:$SI),
"paddis $RT, $RA, $SI", IIC_LdStLFD>;
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
index 076c7465994cf..1b4b58f724bc8 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
@@ -472,7 +472,7 @@ let Predicates = [MMA, IsISAFuture] in {
def DMXXINSTDMR256 : XX2Form_AT3_XBp5_P2<60, 485, (outs dmrrowp:$AT),
(ins vsrprc:$XBp, u2imm:$P),
"dmxxinstdmr256 $AT, $XBp, $P",
- [(set v256i1:$AT, (PPCInst256 v256i1:$XBp, timm:$P))]>;
+ [(set v256i1:$AT, (PPCInst256 v256i1:$XBp, u2imm_timm:$P))]>;
def DMMR
: XForm_ATB3<31, 6, 177, (outs dmr:$AT), (ins dmr:$AB), "dmmr $AT, $AB",
@@ -512,13 +512,14 @@ let Predicates = [MMA, IsISAFuture] in {
31, 14, 177, (outs dmr:$AT), (ins dmr:$ATi, dmr:$AB, u1imm:$T),
"dmsha2hash $AT, $AB, $T",
[(set v1024i1:$AT, (int_ppc_mma_dmsha2hash v1024i1:$ATi,
- v1024i1:$AB, timm:$T))]>,
+ v1024i1:$AB, u1imm_timm:$T))]>,
RegConstraint<"$ATi = $AT">;
def DMSHA3HASH
: XForm_ATp2_SR5<31, 15, 177, (outs dmrp:$ATp),
(ins dmrp:$ATpi, u5imm:$SR), "dmsha3hash $ATp, $SR",
[(set v2048i1:$ATp,
- (int_ppc_mma_dmsha3hash v2048i1:$ATpi, timm:$SR))]>,
+ (int_ppc_mma_dmsha3hash v2048i1:$ATpi,
+ u5imm_timm:$SR))]>,
RegConstraint<"$ATpi = $ATp">;
def DMXXSHAPAD
: XX2Form_AT3_XB6_ID2_E1_BL2<60, 421, (outs dmr:$AT),
@@ -592,8 +593,8 @@ let Predicates = [MMA, IsISAFuture] in {
(DMXVF16GERX2NN $ATi, $XAp, RCCp.BToVSRC)>;
// Cryptography Intrinsic
- def : Pat<(v1024i1 (int_ppc_mma_dmxxshapad v1024i1:$ATi, v16i8:$XB, timm:$ID,
- timm:$E, timm:$BL)),
+ def : Pat<(v1024i1 (int_ppc_mma_dmxxshapad v1024i1:$ATi, v16i8:$XB,
+ u2imm_timm:$ID, u1imm_timm:$E, u2imm_timm:$BL)),
(DMXXSHAPAD $ATi, RCCp.BToVSRC, $ID, $E, $BL)>;
}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index eaf1628a0889b..fcbc1cec375ee 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -780,9 +780,6 @@ def getFPAs64BitIntLo : SDNodeXForm<fpimm, [{
return CurDAG->getTargetConstant(Lo, SDLoc(N), MVT::i32);
}]>;
-def imm34 : PatLeaf<(imm), [{
- return isInt<34>(N->getSExtValue());
-}]>;
def getImmAs64BitInt : SDNodeXForm<imm, [{
return getI64Imm(N->getSExtValue(), SDLoc(N));
@@ -2167,13 +2164,13 @@ def LWAT_PSEUDO : PPCCustomInserterPseudo<
(outs gprc:$dst),
(ins ptr_rc_nor0:$ptr, gprc:$val, u5imm:$fc),
"#LWAT_PSEUDO",
- [(set i32:$dst, (int_ppc_amo_lwat ptr_rc_nor0:$ptr, gprc:$val, timm:$fc))]>;
+ [(set i32:$dst, (int_ppc_amo_lwat ptr_rc_nor0:$ptr, gprc:$val, u5imm_timm:$fc))]>;
def LWAT_COND_PSEUDO : PPCCustomInserterPseudo <
(outs gprc:$dst),
(ins ptr_rc_nor0:$ptr, u5imm:$fc),
"#LWAT_COND_PSEUDO",
- [(set i32:$dst, (int_ppc_amo_lwat_cond ptr_rc_nor0:$ptr, timm:$fc))]>;
+ [(set i32:$dst, (int_ppc_amo_lwat_cond ptr_rc_nor0:$ptr, u5imm_timm:$fc))]>;
let Defs = [CR0], mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {
def STBCX : XForm_1_memOp<31, 694, (outs), (ins gprc:$RST, (memrr $RA, $RB):$addr),
@@ -2191,7 +2188,7 @@ def STWCX : XForm_1_memOp<31, 150, (outs), (ins gprc:$RST, (memrr $RA, $RB):$add
let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
def STWAT : XForm_base_r3xo_memOp<31, 710, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, u5imm:$RB),
"stwat $RST, $RA, $RB", IIC_LdStStore,
- [(PPCstat i32:$RST, ptr_rc_nor0:$RA, timm:$RB)]>,
+ [(PPCstat i32:$RST, ptr_rc_nor0:$RA, u5imm_timm:$RB)]>,
Requires<[IsISA3_0]>;
let isTrap = 1, hasCtrlDep = 1 in
@@ -3093,11 +3090,11 @@ let Uses = [RM], mayRaiseFPException = 1 in {
let hasSideEffects = 1, Defs = [RM] in {
def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
"mtfsb0 $FM", IIC_IntMTFSB0,
- [(int_ppc_mtfsb0 timm:$FM)]>,
+ [(int_ppc_mtfsb0 u5imm_timm:$FM)]>,
PPC970_DGroup_Single, PPC970_Unit_FPU;
def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
"mtfsb1 $FM", IIC_IntMTFSB0,
- [(int_ppc_mtfsb1 timm:$FM)]>,
+ [(int_ppc_mtfsb1 u5imm_timm:$FM)]>,
PPC970_DGroup_Single, PPC970_Unit_FPU;
}
@@ -4584,7 +4581,7 @@ def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
let Predicates = [HasFPU] in {
let Defs = [RM], hasSideEffects = 1 in {
let isCodeGenOnly = 1,
- Pattern = [(int_ppc_mtfsfi timm:$BF, timm:$U)], W = 0 in
+ Pattern = [(int_ppc_mtfsfi u3imm_timm:$BF, u4imm_timm:$U)], W = 0 in
def MTFSFIb : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U),
"mtfsfi $BF, $U", IIC_IntMFFS>;
def MTFSFI : XLForm_4<63, 134, (outs), (ins u3imm:$BF, u4imm:$U, i32imm:$W),
diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td
index 1b03a3db7d112..fdea9c5a4e0ba 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrP10.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td
@@ -657,18 +657,18 @@ def RCCp {
let Predicates = [PrefixInstrs] in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
defm PADDI8 :
- MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc_nox0:$RA, s34imm:$SI),
- (ins immZero:$RA, s34imm_pcrel:$SI),
+ MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc_nox0:$RA, s34imm64:$SI),
+ (ins immZero:$RA, s34imm64_pcrel:$SI),
"paddi $RT, $RA, $SI", IIC_LdStLFD>;
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
- (ins s34imm:$SI),
+ (ins s34imm64:$SI),
"pli $RT, $SI", IIC_IntSimple, []>;
}
}
defm PADDI :
MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc_nor0:$RA, s34imm:$SI),
- (ins immZero:$RA, s34imm_pcrel:$SI),
+ (ins immZero:$RA, s34imm64_pcrel:$SI),
"paddi $RT, $RA, $SI", IIC_LdStLFD>;
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
@@ -681,59 +681,59 @@ let Predicates = [PrefixInstrs] in {
defm PLBZ8 :
MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D), "plbz $RST, $addr",
+ (ins s34imm64_pcrel:$D), "plbz $RST, $addr",
"plbz $RST, $D", IIC_LdStLFD>;
defm PLHZ8 :
MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D), "plhz $RST, $addr",
+ (ins s34imm64_pcrel:$D), "plhz $RST, $addr",
"plhz $RST, $D", IIC_LdStLFD>;
defm PLHA8 :
MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D), "plha $RST, $addr",
+ (ins s34imm64_pcrel:$D), "plha $RST, $addr",
"plha $RST, $D", IIC_LdStLFD>;
defm PLWA8 :
8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D),
+ (ins s34imm64_pcrel:$D),
"plwa $RST, $addr", "plwa $RST, $D", IIC_LdStLFD>;
defm PLWZ8 :
MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D), "plwz $RST, $addr",
+ (ins s34imm64_pcrel:$D), "plwz $RST, $addr",
"plwz $RST, $D", IIC_LdStLFD>;
}
defm PLBZ :
MLS_DForm_R_SI34_RTA5_MEM_p<34, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D), "plbz $RST, $addr",
+ (ins s34imm64_pcrel:$D), "plbz $RST, $addr",
"plbz $RST, $D", IIC_LdStLFD>;
defm PLHZ :
MLS_DForm_R_SI34_RTA5_MEM_p<40, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D), "plhz $RST, $addr",
+ (ins s34imm64_pcrel:$D), "plhz $RST, $addr",
"plhz $RST, $D", IIC_LdStLFD>;
defm PLHA :
MLS_DForm_R_SI34_RTA5_MEM_p<42, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D), "plha $RST, $addr",
+ (ins s34imm64_pcrel:$D), "plha $RST, $addr",
"plha $RST, $D", IIC_LdStLFD>;
defm PLWZ :
MLS_DForm_R_SI34_RTA5_MEM_p<32, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D), "plwz $RST, $addr",
+ (ins s34imm64_pcrel:$D), "plwz $RST, $addr",
"plwz $RST, $D", IIC_LdStLFD>;
defm PLWA :
8LS_DForm_R_SI34_RTA5_MEM_p<41, (outs gprc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D),
+ (ins s34imm64_pcrel:$D),
"plwa $RST, $addr", "plwa $RST, $D",
IIC_LdStLFD>;
defm PLD :
8LS_DForm_R_SI34_RTA5_MEM_p<57, (outs g8rc:$RST), (ins (memri34 $D, $RA):$addr),
(ins (memri34_pcrel $D, $RA):$addr),
- (ins s34imm_pcrel:$D),
+ (ins s34imm64_pcrel:$D),
"pld $RST, $addr", "pld $RST, $D",
IIC_LdStLFD>;
}
@@ -743,38 +743,38 @@ let Predicates = [PrefixInstrs] in {
defm PSTB8 :
MLS_DForm_R_SI34_RTA5_MEM_p<38, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
(ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),
- (ins g8rc:$RST, s34imm_pcrel:$D),
+ (ins g8rc:$RST, s34imm64_pcrel:$D),
"pstb $RST, $addr", "pstb $RST, $D", IIC_LdStLFD>;
defm PSTH8 :
MLS_DForm_R_SI34_RTA5_MEM_p<44, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
(ins g8rc:$RST, (memri34_pcrel $D, $RA):$addr),
- (ins g8rc:$RST, s34imm_pcrel:$D),
+ (ins g8rc:$RST, s34imm64_pcrel:$D),
"psth $RST, $addr", "psth $RST, $D", IIC_LdStLFD>;
defm PSTW8 :
MLS_DForm_R_SI34_RTA5_MEM_p<36, (outs), (ins g8rc:$RST, (memri34 $D, $RA):$addr),
(ins g8rc:$RST, (memri34_...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/179983
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