[llvm] [WebAssembly][FastISel] Omit redundant AND for zext of i8/i16 loads (PR #182240)

[Demetrius Kanios via llvm-commits]

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@@ -465,6 +465,8 @@ unsigned WebAssemblyFastISel::zeroExtendToI32(unsigned Reg, const Value *V,
     break;
   case MVT::i8:
   case MVT::i16:
+    if (isa<LoadInst>(V))
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QuantumSegfault wrote:

Better yet: `isa_and_present`

https://github.com/llvm/llvm-project/pull/182240