[llvm] [DAG] SimplifyDemandedBits - fold FSHR(X, Y, Amt) -> SRL(Y, Amt) (PR #182294)

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Thu Feb 19 09:56:20 PST 2026

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https://github.com/RKSimon auto_merge_enabled https://github.com/llvm/llvm-project/pull/182294

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