[llvm] [DAG] SimplifyDemandedBits - fold FSHR(X, Y, Amt) -> SRL(Y, Amt) (PR #182294)

[Craig Topper via llvm-commits]

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@@ -2256,11 +2256,32 @@ bool TargetLowering::SimplifyDemandedBits(
       }
     }
 
-    // For pow-2 bitwidths we only demand the bottom modulo amt bits.
     if (isPowerOf2_32(BitWidth)) {
+      // Fold FSHR(Op0,Op1,Op2) -> SRL(Op1,Op2)
+      // iff we're guaranteed not to use Op0.
+      // TODO: Add FSHL equivalent?
+      if (!IsFSHL && !DemandedBits.isAllOnes() &&
+          (!TLO.LegalOperations() || isOperationLegal(ISD::SRL, VT))) {
+        unsigned MaxShiftAmt = BitWidth - 1; // urem(Op2, BitWidth)
+        KnownBits KnownAmt =
+            TLO.DAG.computeKnownBits(Op2, DemandedElts, Depth + 1);
+        if (KnownAmt.getMaxValue().ult(BitWidth))
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topperc wrote:

Are we not able to use getLimitedValue() here?

https://github.com/llvm/llvm-project/pull/182294