[llvm] [SelectionDAG] Optimize 32-bit udiv with 33-bit magic constants on 64-bit targets (PR #181288)

[MITSUNARI Shigeo via llvm-commits]

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@@ -6812,23 +6817,49 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
           UnsignedDivisionByConstantInfo::get(
               Divisor, std::min(KnownLeadingZeros, Divisor.countl_zero()));
 
-      MagicFactor = DAG.getConstant(magics.Magic.zext(SVTBits), dl, SVT);
-
-      assert(magics.PreShift < Divisor.getBitWidth() &&
-             "We shouldn't generate an undefined shift!");
-      assert(magics.PostShift < Divisor.getBitWidth() &&
-             "We shouldn't generate an undefined shift!");
-      assert((!magics.IsAdd || magics.PreShift == 0) &&
-             "Unexpected pre-shift");
-      PreShift = DAG.getConstant(magics.PreShift, dl, ShSVT);
-      PostShift = DAG.getConstant(magics.PostShift, dl, ShSVT);
-      NPQFactor = DAG.getConstant(
-          magics.IsAdd ? APInt::getOneBitSet(SVTBits, EltBits - 1)
-                       : APInt::getZero(SVTBits),
-          dl, SVT);
-      UseNPQ |= magics.IsAdd;
-      UsePreShift |= magics.PreShift != 0;
-      UsePostShift |= magics.PostShift != 0;
+      // For 32-bit division with IsAdd (33-bit magic case), use optimized
+      // method: preshift c by (64-a) bits to eliminate runtime shift. This
+      // requires 64x64->128 bit multiplication. Only apply to scalar types
+      // since SIMD lacks 64x64->128 high multiply. Note: IsAdd=true implies
+      // PreShift=0 by algorithm design. Check if 64-bit MULHU is available
+      // before applying this optimization.
+      if (EltBits == 32 && !VT.isVector() &&
+          (HasWideVT64MULHU || HasWideVT64UMUL_LOHI) && magics.IsAdd) {
+        // For IsAdd case, actual magic constant is 2^32 + Magic (33-bit)
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herumi wrote:

I moved the computation according to your idea and refactored them.
https://github.com/llvm/llvm-project/pull/181288/changes/1e2ca5eba2c578589f3d335482d20895c4828bd9

https://github.com/llvm/llvm-project/pull/181288