[llvm] [DAG] Improved ISD::SHL handling in isKnownToBeAPowerOfTwo (PR #181882)

[Matt Arsenault via llvm-commits]

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@@ -914,6 +918,56 @@ TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_Constants) {
   EXPECT_TRUE(DAG->isKnownToBeAPowerOfTwo(SplatBig, /*OrZero=*/true));
 }
 
+TEST_F(AArch64SelectionDAGTest, KnownToBeAPowerOfTwo_SHL) {
+  SDLoc Loc;
+  auto Cst0 = DAG->getConstant(0, Loc, MVT::i32);
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arsenm wrote:

No auto 

https://github.com/llvm/llvm-project/pull/181882