[llvm] [AMDGPU] Align loop headers to prevent instruction fetch split on GFX950 (PR #181999)

[via llvm-commits]

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@@ -286,6 +286,11 @@ class SITargetLowering final : public AMDGPUTargetLowering {
                                        EVT PtrVT) const override;
 
 private:
+  /// Returns true if the first real instruction in MBB is 8 bytes and could
+  /// be split by a 32-byte fetch window boundary. Used on GFX950 to avoid
+  /// instruction fetch delays.
+  bool needsFetchWindowAlignment(const MachineBasicBlock *MBB) const;
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michaelselehov wrote:

Done

https://github.com/llvm/llvm-project/pull/181999