[llvm] [AMDGPU] Align loop headers to prevent instruction fetch split on GFX950 (PR #181999)

[Matt Arsenault via llvm-commits]

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@@ -18811,6 +18825,30 @@ Align SITargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
   return CacheLineAlign;
 }
 
+unsigned SITargetLowering::getMaxPermittedBytesForAlignment(
+    MachineBasicBlock *MBB) const {
+  // GFX950: Limit padding to 4 bytes (one s_nop) for blocks where an 8-byte
+  // instruction could be split by the 32-byte fetch window boundary.
+  // See getPrefLoopAlignment() for context.
+  if (needsFetchWindowAlignment(MBB))
+    return 4;
+  return TargetLowering::getMaxPermittedBytesForAlignment(MBB);
+}
+
+bool SITargetLowering::needsFetchWindowAlignment(
+    const MachineBasicBlock *MBB) const {
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arsenm wrote:

```suggestion
    const MachineBasicBlock &MBB) const {
```

https://github.com/llvm/llvm-project/pull/181999