[llvm] c94e6c0 - [NFC][AArch64] Extract helper functions in AArch64ConditionOptimizer (#182197)

[via llvm-commits]

Author: Hussam A.
Date: 2026-02-19T09:53:14Z
New Revision: c94e6c0a0cb7143d2872dad7c13decb7664d2d2a

URL: https://github.com/llvm/llvm-project/commit/c94e6c0a0cb7143d2872dad7c13decb7664d2d2a
DIFF: https://github.com/llvm/llvm-project/commit/c94e6c0a0cb7143d2872dad7c13decb7664d2d2a.diff

LOG: [NFC][AArch64] Extract helper functions in AArch64ConditionOptimizer (#182197)

Extract shared logic between the cross- and intra-block paths into new
helper functions

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
index f428252e143ba..311cb1800cc39 100644
--- a/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
@@ -115,6 +115,8 @@ class AArch64ConditionOptimizer : public MachineFunctionPass {
   AArch64ConditionOptimizer() : MachineFunctionPass(ID) {}
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
+  bool registersMatch(MachineInstr *FirstMI, MachineInstr *SecondMI);
+  bool nzcvLivesOut(MachineBasicBlock *MBB);
   MachineInstr *findSuitableCompare(MachineBasicBlock *MBB);
   CmpInfo adjustCmp(MachineInstr *CmpMI, AArch64CC::CondCode Cmp);
   void modifyCmp(MachineInstr *CmpMI, const CmpInfo &Info);
@@ -150,6 +152,36 @@ void AArch64ConditionOptimizer::getAnalysisUsage(AnalysisUsage &AU) const {
   MachineFunctionPass::getAnalysisUsage(AU);
 }
 
+// Ensure both compare MIs use the same register, tracing through copies.
+bool AArch64ConditionOptimizer::registersMatch(MachineInstr *FirstMI,
+                                               MachineInstr *SecondMI) {
+  Register FirstReg = FirstMI->getOperand(1).getReg();
+  Register SecondReg = SecondMI->getOperand(1).getReg();
+  Register FirstCmpReg =
+      FirstReg.isVirtual() ? TRI->lookThruCopyLike(FirstReg, MRI) : FirstReg;
+  Register SecondCmpReg =
+      SecondReg.isVirtual() ? TRI->lookThruCopyLike(SecondReg, MRI) : SecondReg;
+  if (FirstCmpReg != SecondCmpReg) {
+    LLVM_DEBUG(dbgs() << "CMPs compare 
diff erent registers\n");
+    return false;
+  }
+
+  return true;
+}
+
+// Check if NZCV lives out to any successor block.
+bool AArch64ConditionOptimizer::nzcvLivesOut(MachineBasicBlock *MBB) {
+  for (auto *SuccBB : MBB->successors()) {
+    if (SuccBB->isLiveIn(AArch64::NZCV)) {
+      LLVM_DEBUG(dbgs() << "NZCV live into successor "
+                        << printMBBReference(*SuccBB) << " from "
+                        << printMBBReference(*MBB) << '\n');
+      return true;
+    }
+  }
+  return false;
+}
+
 // Finds compare instruction that corresponds to supported types of branching.
 // Returns the instruction or nullptr on failures or detecting unsupported
 // instructions.
@@ -163,9 +195,8 @@ MachineInstr *AArch64ConditionOptimizer::findSuitableCompare(
     return nullptr;
 
   // Since we may modify cmp of this MBB, make sure NZCV does not live out.
-  for (auto *SuccBB : MBB->successors())
-    if (SuccBB->isLiveIn(AArch64::NZCV))
-      return nullptr;
+  if (nzcvLivesOut(MBB))
+    return nullptr;
 
   // Now find the instruction controlling the terminator.
   for (MachineBasicBlock::iterator B = MBB->begin(), It = Term; It != B;) {
@@ -394,10 +425,12 @@ bool AArch64ConditionOptimizer::optimizeIntraBlock(MachineBasicBlock &MBB) {
     return false;
   }
 
-  if (FirstCmp->getOperand(1).getReg() != SecondCmp->getOperand(1).getReg()) {
-    LLVM_DEBUG(dbgs() << "CMPs compare 
diff erent registers\n");
+  // Since we may modify cmps in this MBB, make sure NZCV does not live out.
+  if (nzcvLivesOut(&MBB))
+    return false;
+
+  if (!registersMatch(FirstCmp, SecondCmp))
     return false;
-  }
 
   if (!isPureCmp(*FirstCmp) || !isPureCmp(*SecondCmp)) {
     LLVM_DEBUG(dbgs() << "One or both CMPs are not pure\n");
@@ -424,11 +457,6 @@ bool AArch64ConditionOptimizer::optimizeIntraBlock(MachineBasicBlock &MBB) {
     }
   }
 
-  // Since we may modify a cmp in this MBB, make sure NZCV does not live out.
-  for (auto *SuccBB : MBB.successors())
-    if (SuccBB->isLiveIn(AArch64::NZCV))
-      return false;
-
   // Extract condition codes from both CSINCs (operand 3)
   AArch64CC::CondCode FirstCond =
       (AArch64CC::CondCode)(int)FirstCSINC->getOperand(3).getImm();
@@ -508,15 +536,7 @@ bool AArch64ConditionOptimizer::optimizeCrossBlock(MachineBasicBlock &HBB) {
     return false;
   }
 
-  // Ensure both compares use the same register, tracing through copies.
-  Register HeadReg = HeadCmpMI->getOperand(1).getReg();
-  Register TrueReg = TrueCmpMI->getOperand(1).getReg();
-  Register HeadCmpReg =
-      HeadReg.isVirtual() ? TRI->lookThruCopyLike(HeadReg, MRI) : HeadReg;
-  Register TrueCmpReg =
-      TrueReg.isVirtual() ? TRI->lookThruCopyLike(TrueReg, MRI) : TrueReg;
-  if (HeadCmpReg != TrueCmpReg) {
-    LLVM_DEBUG(dbgs() << "CMPs compare 
diff erent registers\n");
+  if (!registersMatch(HeadCmpMI, TrueCmpMI)) {
     return false;
   }