[llvm] [AArch64] Optimize constant v2i32/v2f32 vector builds (PR #177076)

[Karthika Devi C via llvm-commits]

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@@ -16193,6 +16193,43 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
     return Val;
   }
 
+  // Handle 64-bit constant BUILD_VECTORs by packing them into an i64 immediate.
+  // This is cheaper than a load if the immediate can be materialized in a few
+  // mov instructions. This optimization is disabled for big-endian targets for
+  // now.
+  if (BVN->isConstant() && VT.isFixedLengthVector() &&
+      VT.getSizeInBits() == 64 && !DAG.getDataLayout().isBigEndian()) {
+    const SDLoc DL(Op);
+    APInt PackedVal(64, 0);
+    unsigned BitPos = 0;
+
+    unsigned EltSizeInBits = VT.getScalarSizeInBits();
+    for (unsigned i = 0, e = BVN->getNumOperands(); i != e; ++i) {
+      const SDValue &LaneOp = BVN->getOperand(i);
+      APInt LaneBits;
+      if (auto *C = dyn_cast<ConstantSDNode>(LaneOp)) {
+        LaneBits = C->getAPIntValue();
+      } else if (auto *CFP = dyn_cast<ConstantFPSDNode>(LaneOp)) {
+        LaneBits = CFP->getValueAPF().bitcastToAPInt();
+      }
+
+      PackedVal |= LaneBits.zext(64) << BitPos;
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kartcq wrote:

Done

https://github.com/llvm/llvm-project/pull/177076