[llvm] [AArch64] Enable MaxInterleaveFactor4 for cortex-x series CPUs. (PR #181851)

[David Green via llvm-commits]

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@@ -272,6 +272,7 @@ def TuneX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
                                   FeatureALULSLFast,
                                   FeaturePostRAScheduler,
                                   FeatureEnableSelectOptimize,
+                                  FeatureMaxInterleaveFactor4,
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davemgreen wrote:

Yeah. We don't have a max interleave 6 yet, or a very good way of splitting out different throughput kinds. As with many unrollings in llvm the heuristics leave a lot to be desired, but this allows them to scale higher for cores where that makes sense.

https://github.com/llvm/llvm-project/pull/181851