[llvm] [X86][APX] Fix assembly printing for NF+ND shift-by-1 instructions (PR #181565)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 18 13:03:32 PST 2026
https://github.com/moleium updated https://github.com/llvm/llvm-project/pull/181565
>From d4cacf75539043239d427fbfe5772948794a12b4 Mon Sep 17 00:00:00 2001
From: moleium <molenoch at protonmail.com>
Date: Wed, 18 Feb 2026 19:48:03 +0300
Subject: [PATCH] Clang with -mapxf -no-integrated-as generated shift-by-1
NF+ND instructions without the explicit $1 immediate which causes binutils to
reject the assembly with 'operand type mismatch'.
Added custom printer in X86ATTInstPrinter.cpp to emit the $1 immediate for
these instructions. Removed DisassembleOnly markers from *r1_NF_ND variants
in X86InstrShiftRotate.td.
Fixes #181553
---
llvm/lib/Target/X86/X86InstrShiftRotate.td | 32 ++++-----
llvm/lib/Target/X86/X86InstrUtils.td | 32 +++++++++
llvm/test/CodeGen/X86/apx/rol.ll | 32 ++++-----
llvm/test/CodeGen/X86/apx/ror.ll | 16 ++---
llvm/test/CodeGen/X86/apx/sar.ll | 16 ++---
llvm/test/CodeGen/X86/apx/shift-eflags.ll | 4 +-
llvm/test/CodeGen/X86/apx/shr.ll | 32 ++++-----
llvm/test/CodeGen/X86/popcnt.ll | 32 ++++-----
llvm/test/MC/Disassembler/X86/apx/rol.txt | 8 +--
llvm/test/MC/Disassembler/X86/apx/ror.txt | 8 +--
llvm/test/MC/Disassembler/X86/apx/sar.txt | 8 +--
llvm/test/MC/Disassembler/X86/apx/shl.txt | 8 +--
llvm/test/MC/Disassembler/X86/apx/shr.txt | 8 +--
llvm/test/MC/X86/apx/rol-att.s | 12 ++--
llvm/test/MC/X86/apx/rol-encopt.s | 8 +--
llvm/test/MC/X86/apx/ror-att.s | 12 ++--
llvm/test/MC/X86/apx/ror-encopt.s | 8 +--
llvm/test/MC/X86/apx/sar-att.s | 12 ++--
llvm/test/MC/X86/apx/sar-encopt.s | 8 +--
llvm/test/MC/X86/apx/shift-one-att.s | 81 ++++++++++++++++++++++
llvm/test/MC/X86/apx/shl-att.s | 12 ++--
llvm/test/MC/X86/apx/shl-encopt.s | 8 +--
llvm/test/MC/X86/apx/shr-att.s | 12 ++--
llvm/test/MC/X86/apx/shr-encopt.s | 8 +--
24 files changed, 265 insertions(+), 152 deletions(-)
create mode 100644 llvm/test/MC/X86/apx/shift-one-att.s
diff --git a/llvm/lib/Target/X86/X86InstrShiftRotate.td b/llvm/lib/Target/X86/X86InstrShiftRotate.td
index 2a5488847e648..f7705a43908a1 100644
--- a/llvm/lib/Target/X86/X86InstrShiftRotate.td
+++ b/llvm/lib/Target/X86/X86InstrShiftRotate.td
@@ -70,10 +70,10 @@ multiclass ShiftRotate<string m, Format RegMRM, Format MemMRM, SDPatternOperator
// GNU binutils distinguish them by adding an explicit $1 to asm string of 8r1_ND. But we haven't support
// constant immediate in asm string for X86 in TD. So we add DisassembleOnly for 8r1_ND for the time being.
let Predicates = [In64BitMode] in {
- def 8r1_ND : UnaryOpR_RF<0xD1, RegMRM, m, Xi8, null_frag, 1>, DisassembleOnly;
- def 16r1_ND : UnaryOpR_RF<0xD1, RegMRM, m, Xi16, null_frag, 1>, PD;
- def 32r1_ND : UnaryOpR_RF<0xD1, RegMRM, m, Xi32, null_frag, 1>;
- def 64r1_ND : UnaryOpR_RF<0xD1, RegMRM, m, Xi64, null_frag, 1>;
+ def 8r1_ND : UnaryOpR_RF_1<0xD1, RegMRM, m, Xi8, null_frag, 1>;
+ def 16r1_ND : UnaryOpR_RF_1<0xD1, RegMRM, m, Xi16, null_frag, 1>, PD;
+ def 32r1_ND : UnaryOpR_RF_1<0xD1, RegMRM, m, Xi32, null_frag, 1>;
+ def 64r1_ND : UnaryOpR_RF_1<0xD1, RegMRM, m, Xi64, null_frag, 1>;
def 8r1_EVEX : UnaryOpR_RF<0xD1, RegMRM, m, Xi8>, PL;
def 16r1_EVEX : UnaryOpR_RF<0xD1, RegMRM, m, Xi16>, PL, PD;
@@ -96,10 +96,10 @@ multiclass ShiftRotate<string m, Format RegMRM, Format MemMRM, SDPatternOperator
}
}
let SchedRW = [mi, ri], Predicates = [In64BitMode] in {
- def 8m1_ND : UnaryOpM_RF<0xD1, MemMRM, m, Xi8>;
- def 16m1_ND : UnaryOpM_RF<0xD1, MemMRM, m, Xi16>, PD;
- def 32m1_ND : UnaryOpM_RF<0xD1, MemMRM, m, Xi32>;
- def 64m1_ND : UnaryOpM_RF<0xD1, MemMRM, m, Xi64>;
+ def 8m1_ND : UnaryOpM_RF_1<0xD1, MemMRM, m, Xi8>;
+ def 16m1_ND : UnaryOpM_RF_1<0xD1, MemMRM, m, Xi16>, PD;
+ def 32m1_ND : UnaryOpM_RF_1<0xD1, MemMRM, m, Xi32>;
+ def 64m1_ND : UnaryOpM_RF_1<0xD1, MemMRM, m, Xi64>;
}
}
@@ -181,10 +181,10 @@ multiclass ShiftRotate_NF<string m, Format RegMRM, Format MemMRM, SchedReadWrite
def 32r1_NF : UnaryOpR_R<0xD1, RegMRM, m, Xi32>, NF;
def 64r1_NF : UnaryOpR_R<0xD1, RegMRM, m, Xi64>, NF;
- def 8r1_NF_ND : UnaryOpR_R<0xD1, RegMRM, m, Xi8, null_frag, 1>, EVEX_NF, DisassembleOnly;
- def 16r1_NF_ND : UnaryOpR_R<0xD1, RegMRM, m, Xi16, null_frag, 1>, EVEX_NF, PD;
- def 32r1_NF_ND : UnaryOpR_R<0xD1, RegMRM, m, Xi32, null_frag, 1>, EVEX_NF;
- def 64r1_NF_ND : UnaryOpR_R<0xD1, RegMRM, m, Xi64, null_frag, 1>, EVEX_NF;
+ def 8r1_NF_ND : UnaryOpR_R_1<0xD1, RegMRM, m, Xi8, null_frag, 1>, EVEX_NF;
+ def 16r1_NF_ND : UnaryOpR_R_1<0xD1, RegMRM, m, Xi16, null_frag, 1>, EVEX_NF, PD;
+ def 32r1_NF_ND : UnaryOpR_R_1<0xD1, RegMRM, m, Xi32, null_frag, 1>, EVEX_NF;
+ def 64r1_NF_ND : UnaryOpR_R_1<0xD1, RegMRM, m, Xi64, null_frag, 1>, EVEX_NF;
}
let SchedRW = [mi, WriteRMW] in {
@@ -194,10 +194,10 @@ multiclass ShiftRotate_NF<string m, Format RegMRM, Format MemMRM, SchedReadWrite
def 64m1_NF : UnaryOpM_M<0xD1, MemMRM, m, Xi64>, NF;
}
let SchedRW = [mi, ri] in {
- def 8m1_NF_ND : UnaryOpM_R<0xD1, MemMRM, m, Xi8>, EVEX_NF;
- def 16m1_NF_ND : UnaryOpM_R<0xD1, MemMRM, m, Xi16>, EVEX_NF, PD;
- def 32m1_NF_ND : UnaryOpM_R<0xD1, MemMRM, m, Xi32>, EVEX_NF;
- def 64m1_NF_ND : UnaryOpM_R<0xD1, MemMRM, m, Xi64>, EVEX_NF;
+ def 8m1_NF_ND : UnaryOpM_R_1<0xD1, MemMRM, m, Xi8>, EVEX_NF;
+ def 16m1_NF_ND : UnaryOpM_R_1<0xD1, MemMRM, m, Xi16>, EVEX_NF, PD;
+ def 32m1_NF_ND : UnaryOpM_R_1<0xD1, MemMRM, m, Xi32>, EVEX_NF;
+ def 64m1_NF_ND : UnaryOpM_R_1<0xD1, MemMRM, m, Xi64>, EVEX_NF;
}
let Uses = [CL] in {
diff --git a/llvm/lib/Target/X86/X86InstrUtils.td b/llvm/lib/Target/X86/X86InstrUtils.td
index 6aae90b77fbad..c8c0f12628b8a 100644
--- a/llvm/lib/Target/X86/X86InstrUtils.td
+++ b/llvm/lib/Target/X86/X86InstrUtils.td
@@ -1340,6 +1340,16 @@ class UnaryOpR_R<bits<8> o, Format f, string m, X86TypeInfo t,
: UnaryOpR<o, f, m, !if(!eq(ndd, 0), unaryop_args, unaryop_ndd_args), t,
(outs t.RegClass:$dst),
[(set t.RegClass:$dst, (node t.RegClass:$src1))]>, NDD<ndd>;
+
+// UnaryOpR_R_1 - Instructions that read "reg" and write "reg" with explicit $1.
+class UnaryOpR_R_1<bits<8> o, Format f, string m, X86TypeInfo t,
+ SDPatternOperator node = null_frag, bit ndd = 0>
+ : UnaryOpR<o, f, m, !if(!eq(ndd, 0), unaryop_args, "{$$1, $src1, $dst|$dst, $src1, 1}"), t,
+ (outs t.RegClass:$dst),
+ [(set t.RegClass:$dst, (node t.RegClass:$src1))]>, NDD<ndd>;
+
+
+
// UnaryOpR_RF - Instructions that read "reg" and write "reg"/EFLAGS.
class UnaryOpR_RF<bits<8> o, Format f, string m, X86TypeInfo t,
SDPatternOperator node = null_frag, bit ndd = 0>
@@ -1348,6 +1358,14 @@ class UnaryOpR_RF<bits<8> o, Format f, string m, X86TypeInfo t,
[(set t.RegClass:$dst, (node t.RegClass:$src1))]>,
DefEFLAGS, NDD<ndd>;
+// UnaryOpR_RF_1 - Instructions that read "reg" and write "reg"/EFLAGS with explicit $1.
+class UnaryOpR_RF_1<bits<8> o, Format f, string m, X86TypeInfo t,
+ SDPatternOperator node = null_frag, bit ndd = 0>
+ : UnaryOpR<o, f, m, !if(!eq(ndd, 0), unaryop_args, "{$$1, $src1, $dst|$dst, $src1, 1}"), t,
+ (outs t.RegClass:$dst),
+ [(set t.RegClass:$dst, (node t.RegClass:$src1))]>,
+ DefEFLAGS, NDD<ndd>;
+
// UnaryOpM - Instructions that read "[mem]".
class UnaryOpM<bits<8> o, Format f, string m, string args, X86TypeInfo t,
dag out, list<dag> p>
@@ -1366,6 +1384,20 @@ class UnaryOpM_RF<bits<8> o, Format f, string m, X86TypeInfo t,
: UnaryOpM<o, f, m, unaryop_ndd_args, t, (outs t.RegClass:$dst),
[(set t.RegClass:$dst, EFLAGS, (node (t.LoadNode addr:$src1)))]>,
Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, DefEFLAGS, NDD<1>;
+
+// UnaryOpM_R_1 - Instructions that read "[mem]" and writes "reg" with explicit $1.
+class UnaryOpM_R_1<bits<8> o, Format f, string m, X86TypeInfo t,
+ SDPatternOperator node = null_frag>
+ : UnaryOpM<o, f, m, "{$$1, $src1, $dst|$dst, $src1, 1}", t, (outs t.RegClass:$dst),
+ [(set t.RegClass:$dst, (node (t.LoadNode addr:$src1)))]>,
+ Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, NDD<1>;
+
+// UnaryOpM_RF_1 - Instructions that read "[mem]" and writes "reg"/EFLAGS with explicit $1.
+class UnaryOpM_RF_1<bits<8> o, Format f, string m, X86TypeInfo t,
+ SDPatternOperator node = null_frag>
+ : UnaryOpM<o, f, m, "{$$1, $src1, $dst|$dst, $src1, 1}", t, (outs t.RegClass:$dst),
+ [(set t.RegClass:$dst, EFLAGS, (node (t.LoadNode addr:$src1)))]>,
+ Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>, DefEFLAGS, NDD<1>;
// UnaryOpM_M - Instructions that read "[mem]" and writes "[mem]".
class UnaryOpM_M<bits<8> o, Format f, string m, X86TypeInfo t,
SDPatternOperator node = null_frag>
diff --git a/llvm/test/CodeGen/X86/apx/rol.ll b/llvm/test/CodeGen/X86/apx/rol.ll
index 58ddc55ab6aba..40b8e519a0932 100644
--- a/llvm/test/CodeGen/X86/apx/rol.ll
+++ b/llvm/test/CodeGen/X86/apx/rol.ll
@@ -4,7 +4,7 @@
define i8 @rol8m1(ptr %ptr) {
; CHECK-LABEL: rol8m1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: rolb (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0x07]
+; CHECK-NEXT: rolb $1, (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0x07]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%a = load i8, ptr %ptr
@@ -17,7 +17,7 @@ entry:
define i8 @rol8m1_intrinsic(ptr %ptr) {
; CHECK-LABEL: rol8m1_intrinsic:
; CHECK: # %bb.0:
-; CHECK-NEXT: rolb (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0x07]
+; CHECK-NEXT: rolb $1, (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0x07]
; CHECK-NEXT: retq # encoding: [0xc3]
%a = load i8, ptr %ptr
%f = call i8 @llvm.fshr.i8(i8 %a, i8 %a, i8 7)
@@ -27,7 +27,7 @@ define i8 @rol8m1_intrinsic(ptr %ptr) {
define i16 @rol16m1(ptr %ptr) {
; CHECK-LABEL: rol16m1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: rolw (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0x07]
+; CHECK-NEXT: rolw $1, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0x07]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%a = load i16, ptr %ptr
@@ -40,7 +40,7 @@ entry:
define i16 @rol16m1_intrinsic(ptr %ptr) {
; CHECK-LABEL: rol16m1_intrinsic:
; CHECK: # %bb.0:
-; CHECK-NEXT: rolw (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0x07]
+; CHECK-NEXT: rolw $1, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0x07]
; CHECK-NEXT: retq # encoding: [0xc3]
%a = load i16, ptr %ptr
%f = call i16 @llvm.fshr.i16(i16 %a, i16 %a, i16 15)
@@ -50,7 +50,7 @@ define i16 @rol16m1_intrinsic(ptr %ptr) {
define i32 @rol32m1(ptr %ptr) {
; CHECK-LABEL: rol32m1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: roll (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0x07]
+; CHECK-NEXT: roll $1, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0x07]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%a = load i32, ptr %ptr
@@ -63,7 +63,7 @@ entry:
define i32 @rol32m1_intrinsic(ptr %ptr) {
; CHECK-LABEL: rol32m1_intrinsic:
; CHECK: # %bb.0:
-; CHECK-NEXT: roll (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0x07]
+; CHECK-NEXT: roll $1, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0x07]
; CHECK-NEXT: retq # encoding: [0xc3]
%a = load i32, ptr %ptr
%f = call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 31)
@@ -73,7 +73,7 @@ define i32 @rol32m1_intrinsic(ptr %ptr) {
define i64 @rol64m1(ptr %ptr) {
; CHECK-LABEL: rol64m1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: rolq (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0x07]
+; CHECK-NEXT: rolq $1, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0x07]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%a = load i64, ptr %ptr
@@ -86,7 +86,7 @@ entry:
define i64 @rol64m1_intrinsic(ptr %ptr) {
; CHECK-LABEL: rol64m1_intrinsic:
; CHECK: # %bb.0:
-; CHECK-NEXT: rolq (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0x07]
+; CHECK-NEXT: rolq $1, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0x07]
; CHECK-NEXT: retq # encoding: [0xc3]
%a = load i64, ptr %ptr
%f = call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 63)
@@ -212,7 +212,7 @@ entry:
define i8 @rol8r1(i8 noundef %a) {
; CHECK-LABEL: rol8r1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: rolb %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0xc7]
+; CHECK-NEXT: rolb $1, %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0xc7]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%0 = shl i8 %a, 1
@@ -224,7 +224,7 @@ entry:
define i8 @rol8r1_intrinsic(i8 noundef %a) {
; CHECK-LABEL: rol8r1_intrinsic:
; CHECK: # %bb.0:
-; CHECK-NEXT: rolb %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0xc7]
+; CHECK-NEXT: rolb $1, %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0xc7]
; CHECK-NEXT: retq # encoding: [0xc3]
%f = call i8 @llvm.fshr.i8(i8 %a, i8 %a, i8 7)
ret i8 %f
@@ -233,7 +233,7 @@ define i8 @rol8r1_intrinsic(i8 noundef %a) {
define i16 @rol16r1(i16 noundef %a) {
; CHECK-LABEL: rol16r1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: rolw %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0xc7]
+; CHECK-NEXT: rolw $1, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0xc7]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%0 = shl i16 %a, 1
@@ -245,7 +245,7 @@ entry:
define i16 @rol16r1_intrinsic(i16 noundef %a) {
; CHECK-LABEL: rol16r1_intrinsic:
; CHECK: # %bb.0:
-; CHECK-NEXT: rolw %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0xc7]
+; CHECK-NEXT: rolw $1, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0xc7]
; CHECK-NEXT: retq # encoding: [0xc3]
%f = call i16 @llvm.fshr.i16(i16 %a, i16 %a, i16 15)
ret i16 %f
@@ -254,7 +254,7 @@ define i16 @rol16r1_intrinsic(i16 noundef %a) {
define i32 @rol32r1(i32 noundef %a) {
; CHECK-LABEL: rol32r1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: roll %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0xc7]
+; CHECK-NEXT: roll $1, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0xc7]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%0 = shl i32 %a, 1
@@ -266,7 +266,7 @@ entry:
define i32 @rol32r1_intrinsic(i32 noundef %a) {
; CHECK-LABEL: rol32r1_intrinsic:
; CHECK: # %bb.0:
-; CHECK-NEXT: roll %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0xc7]
+; CHECK-NEXT: roll $1, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0xc7]
; CHECK-NEXT: retq # encoding: [0xc3]
%f = call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 31)
ret i32 %f
@@ -275,7 +275,7 @@ define i32 @rol32r1_intrinsic(i32 noundef %a) {
define i64 @rol64r1(i64 noundef %a) {
; CHECK-LABEL: rol64r1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: rolq %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0xc7]
+; CHECK-NEXT: rolq $1, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0xc7]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%0 = shl i64 %a, 1
@@ -287,7 +287,7 @@ entry:
define i64 @rol64r1_intrinsic(i64 noundef %a) {
; CHECK-LABEL: rol64r1_intrinsic:
; CHECK: # %bb.0:
-; CHECK-NEXT: rolq %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0xc7]
+; CHECK-NEXT: rolq $1, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0xc7]
; CHECK-NEXT: retq # encoding: [0xc3]
%f = call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 63)
ret i64 %f
diff --git a/llvm/test/CodeGen/X86/apx/ror.ll b/llvm/test/CodeGen/X86/apx/ror.ll
index e2b65e776ed57..55abe7ee0f9ca 100644
--- a/llvm/test/CodeGen/X86/apx/ror.ll
+++ b/llvm/test/CodeGen/X86/apx/ror.ll
@@ -4,7 +4,7 @@
define i8 @ror8m1(ptr %ptr) {
; CHECK-LABEL: ror8m1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: rorb (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0x0f]
+; CHECK-NEXT: rorb $1, (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0x0f]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%a = load i8, ptr %ptr
@@ -17,7 +17,7 @@ entry:
define i16 @ror16m1(ptr %ptr) {
; CHECK-LABEL: ror16m1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: rorw (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0x0f]
+; CHECK-NEXT: rorw $1, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0x0f]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%a = load i16, ptr %ptr
@@ -30,7 +30,7 @@ entry:
define i32 @ror32m1(ptr %ptr) {
; CHECK-LABEL: ror32m1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: rorl (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0x0f]
+; CHECK-NEXT: rorl $1, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0x0f]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%a = load i32, ptr %ptr
@@ -43,7 +43,7 @@ entry:
define i64 @ror64m1(ptr %ptr) {
; CHECK-LABEL: ror64m1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: rorq (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0x0f]
+; CHECK-NEXT: rorq $1, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0x0f]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%a = load i64, ptr %ptr
@@ -240,7 +240,7 @@ entry:
define i8 @ror8r1(i8 noundef %a) {
; CHECK-LABEL: ror8r1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: rorb %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0xcf]
+; CHECK-NEXT: rorb $1, %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0xcf]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%0 = lshr i8 %a, 1
@@ -252,7 +252,7 @@ entry:
define i16 @ror16r1(i16 noundef %a) {
; CHECK-LABEL: ror16r1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: rorw %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0xcf]
+; CHECK-NEXT: rorw $1, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0xcf]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%0 = lshr i16 %a, 1
@@ -264,7 +264,7 @@ entry:
define i32 @ror32r1(i32 noundef %a) {
; CHECK-LABEL: ror32r1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: rorl %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0xcf]
+; CHECK-NEXT: rorl $1, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0xcf]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%0 = lshr i32 %a, 1
@@ -276,7 +276,7 @@ entry:
define i64 @ror64r1(i64 noundef %a) {
; CHECK-LABEL: ror64r1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: rorq %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0xcf]
+; CHECK-NEXT: rorq $1, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0xcf]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%0 = lshr i64 %a, 1
diff --git a/llvm/test/CodeGen/X86/apx/sar.ll b/llvm/test/CodeGen/X86/apx/sar.ll
index 25c067b46b9ce..b92d2032aa6b0 100644
--- a/llvm/test/CodeGen/X86/apx/sar.ll
+++ b/llvm/test/CodeGen/X86/apx/sar.ll
@@ -4,7 +4,7 @@
define i8 @sar8m1(ptr %ptr) {
; CHECK-LABEL: sar8m1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sarb (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0x3f]
+; CHECK-NEXT: sarb $1, (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0x3f]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%a = load i8, ptr %ptr
@@ -15,7 +15,7 @@ entry:
define i16 @sar16m1(ptr %ptr) {
; CHECK-LABEL: sar16m1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sarw (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0x3f]
+; CHECK-NEXT: sarw $1, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0x3f]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%a = load i16, ptr %ptr
@@ -26,7 +26,7 @@ entry:
define i32 @sar32m1(ptr %ptr) {
; CHECK-LABEL: sar32m1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sarl (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0x3f]
+; CHECK-NEXT: sarl $1, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0x3f]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%a = load i32, ptr %ptr
@@ -37,7 +37,7 @@ entry:
define i64 @sar64m1(ptr %ptr) {
; CHECK-LABEL: sar64m1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sarq (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0x3f]
+; CHECK-NEXT: sarq $1, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0x3f]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%a = load i64, ptr %ptr
@@ -200,7 +200,7 @@ entry:
define i8 @sar8r1(i8 noundef %a) {
; CHECK-LABEL: sar8r1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sarb %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0xff]
+; CHECK-NEXT: sarb $1, %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0xff]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%sar = ashr i8 %a, 1
@@ -210,7 +210,7 @@ entry:
define i16 @sar16r1(i16 noundef %a) {
; CHECK-LABEL: sar16r1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sarw %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0xff]
+; CHECK-NEXT: sarw $1, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0xff]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%sar = ashr i16 %a, 1
@@ -220,7 +220,7 @@ entry:
define i32 @sar32r1(i32 noundef %a) {
; CHECK-LABEL: sar32r1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sarl %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0xff]
+; CHECK-NEXT: sarl $1, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0xff]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%sar = ashr i32 %a, 1
@@ -230,7 +230,7 @@ entry:
define i64 @sar64r1(i64 noundef %a) {
; CHECK-LABEL: sar64r1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: sarq %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0xff]
+; CHECK-NEXT: sarq $1, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0xff]
; CHECK-NEXT: retq # encoding: [0xc3]
entry:
%sar = ashr i64 %a, 1
diff --git a/llvm/test/CodeGen/X86/apx/shift-eflags.ll b/llvm/test/CodeGen/X86/apx/shift-eflags.ll
index 2659f8031ef77..4acfff49ad2fe 100644
--- a/llvm/test/CodeGen/X86/apx/shift-eflags.ll
+++ b/llvm/test/CodeGen/X86/apx/shift-eflags.ll
@@ -124,7 +124,7 @@ define i32 @shl_const1(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
define i32 @ashr_const1_self_select(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
; CHECK-LABEL: ashr_const1_self_select:
; CHECK: # %bb.0:
-; CHECK-NEXT: sarl %edi, %eax
+; CHECK-NEXT: sarl $1, %edi, %eax
; CHECK-NEXT: cmovnel %edx, %eax
; CHECK-NEXT: retq
%s = ashr i32 %a0, 1
@@ -137,7 +137,7 @@ define i32 @ashr_const1_self_select(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
define i32 @lshr_const1_self_select(i32 %a0, i32 %a1, i32 %a2, i32 %a3) {
; CHECK-LABEL: lshr_const1_self_select:
; CHECK: # %bb.0:
-; CHECK-NEXT: shrl %edi, %eax
+; CHECK-NEXT: shrl $1, %edi, %eax
; CHECK-NEXT: cmovnel %edx, %eax
; CHECK-NEXT: retq
%s = lshr i32 %a0, 1
diff --git a/llvm/test/CodeGen/X86/apx/shr.ll b/llvm/test/CodeGen/X86/apx/shr.ll
index b82000bd950dc..bde2c7b2325d8 100644
--- a/llvm/test/CodeGen/X86/apx/shr.ll
+++ b/llvm/test/CodeGen/X86/apx/shr.ll
@@ -6,12 +6,12 @@
define i8 @shr8m1(ptr %ptr) {
; CHECK-LABEL: shr8m1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: shrb (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0x2f]
+; CHECK-NEXT: shrb $1, (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0x2f]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: shr8m1:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} shrb (%rdi), %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xd0,0x2f]
+; NF-NEXT: {nf} shrb $1, (%rdi), %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xd0,0x2f]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%a = load i8, ptr %ptr
@@ -22,12 +22,12 @@ entry:
define i16 @shr16m1(ptr %ptr) {
; CHECK-LABEL: shr16m1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: shrw (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0x2f]
+; CHECK-NEXT: shrw $1, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0x2f]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: shr16m1:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} shrw (%rdi), %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0xd1,0x2f]
+; NF-NEXT: {nf} shrw $1, (%rdi), %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0xd1,0x2f]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%a = load i16, ptr %ptr
@@ -38,12 +38,12 @@ entry:
define i32 @shr32m1(ptr %ptr) {
; CHECK-LABEL: shr32m1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: shrl (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0x2f]
+; CHECK-NEXT: shrl $1, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0x2f]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: shr32m1:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} shrl (%rdi), %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xd1,0x2f]
+; NF-NEXT: {nf} shrl $1, (%rdi), %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xd1,0x2f]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%a = load i32, ptr %ptr
@@ -54,12 +54,12 @@ entry:
define i64 @shr64m1(ptr %ptr) {
; CHECK-LABEL: shr64m1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: shrq (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0x2f]
+; CHECK-NEXT: shrq $1, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0x2f]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: shr64m1:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} shrq (%rdi), %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0xd1,0x2f]
+; NF-NEXT: {nf} shrq $1, (%rdi), %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0xd1,0x2f]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%a = load i64, ptr %ptr
@@ -298,12 +298,12 @@ entry:
define i8 @shr8r1(i8 noundef %a) {
; CHECK-LABEL: shr8r1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: shrb %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0xef]
+; CHECK-NEXT: shrb $1, %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0xd0,0xef]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: shr8r1:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} shrb %dil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xd0,0xef]
+; NF-NEXT: {nf} shrb $1, %dil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xd0,0xef]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%shr = lshr i8 %a, 1
@@ -313,12 +313,12 @@ entry:
define i16 @shr16r1(i16 noundef %a) {
; CHECK-LABEL: shr16r1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: shrw %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0xef]
+; CHECK-NEXT: shrw $1, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0xd1,0xef]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: shr16r1:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} shrw %di, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0xd1,0xef]
+; NF-NEXT: {nf} shrw $1, %di, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0xd1,0xef]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%shr = lshr i16 %a, 1
@@ -328,12 +328,12 @@ entry:
define i32 @shr32r1(i32 noundef %a) {
; CHECK-LABEL: shr32r1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: shrl %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0xef]
+; CHECK-NEXT: shrl $1, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0xd1,0xef]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: shr32r1:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} shrl %edi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xd1,0xef]
+; NF-NEXT: {nf} shrl $1, %edi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0xd1,0xef]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%shr = lshr i32 %a, 1
@@ -343,12 +343,12 @@ entry:
define i64 @shr64r1(i64 noundef %a) {
; CHECK-LABEL: shr64r1:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: shrq %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0xef]
+; CHECK-NEXT: shrq $1, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0xd1,0xef]
; CHECK-NEXT: retq # encoding: [0xc3]
;
; NF-LABEL: shr64r1:
; NF: # %bb.0: # %entry
-; NF-NEXT: {nf} shrq %rdi, %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0xd1,0xef]
+; NF-NEXT: {nf} shrq $1, %rdi, %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0xd1,0xef]
; NF-NEXT: retq # encoding: [0xc3]
entry:
%shr = lshr i64 %a, 1
diff --git a/llvm/test/CodeGen/X86/popcnt.ll b/llvm/test/CodeGen/X86/popcnt.ll
index 3004b8b72fcc5..b7a9d18cdc767 100644
--- a/llvm/test/CodeGen/X86/popcnt.ll
+++ b/llvm/test/CodeGen/X86/popcnt.ll
@@ -109,7 +109,7 @@ define i16 @cnt16(i16 %x) nounwind readnone {
;
; X64-NDD-LABEL: cnt16:
; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: shrw %di, %ax
+; X64-NDD-NEXT: shrw $1, %di, %ax
; X64-NDD-NEXT: andw $21845, %ax # imm = 0x5555
; X64-NDD-NEXT: subw %ax, %di, %ax
; X64-NDD-NEXT: andw $13107, %ax, %cx # imm = 0x3333
@@ -180,7 +180,7 @@ define i32 @cnt32(i32 %x) nounwind readnone {
;
; X64-NDD-LABEL: cnt32:
; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: shrl %edi, %eax
+; X64-NDD-NEXT: shrl $1, %edi, %eax
; X64-NDD-NEXT: andl $1431655765, %eax # imm = 0x55555555
; X64-NDD-NEXT: subl %eax, %edi
; X64-NDD-NEXT: andl $858993459, %edi, %eax # imm = 0x33333333
@@ -274,7 +274,7 @@ define i64 @cnt64(i64 %x) nounwind readnone {
;
; X64-NDD-LABEL: cnt64:
; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: shrq %rdi, %rax
+; X64-NDD-NEXT: shrq $1, %rdi, %rax
; X64-NDD-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555
; X64-NDD-NEXT: andq %rcx, %rax
; X64-NDD-NEXT: subq %rax, %rdi
@@ -497,7 +497,7 @@ define i128 @cnt128(i128 %x) nounwind readnone {
;
; X64-NDD-LABEL: cnt128:
; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: shrq %rsi, %rax
+; X64-NDD-NEXT: shrq $1, %rsi, %rax
; X64-NDD-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555
; X64-NDD-NEXT: andq %rcx, %rax
; X64-NDD-NEXT: subq %rax, %rsi
@@ -513,7 +513,7 @@ define i128 @cnt128(i128 %x) nounwind readnone {
; X64-NDD-NEXT: movabsq $72340172838076673, %r8 # imm = 0x101010101010101
; X64-NDD-NEXT: imulq %r8, %rdx
; X64-NDD-NEXT: shrq $56, %rdx
-; X64-NDD-NEXT: shrq %rdi, %r9
+; X64-NDD-NEXT: shrq $1, %rdi, %r9
; X64-NDD-NEXT: andq %r9, %rcx
; X64-NDD-NEXT: subq %rcx, %rdi
; X64-NDD-NEXT: andq %rax, %rdi, %rcx
@@ -703,7 +703,7 @@ define i64 @cnt64_noimplicitfloat(i64 %x) nounwind readnone noimplicitfloat {
;
; X64-NDD-LABEL: cnt64_noimplicitfloat:
; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: shrq %rdi, %rax
+; X64-NDD-NEXT: shrq $1, %rdi, %rax
; X64-NDD-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555
; X64-NDD-NEXT: andq %rcx, %rax
; X64-NDD-NEXT: subq %rax, %rdi
@@ -778,7 +778,7 @@ define i32 @cnt32_optsize(i32 %x) nounwind readnone optsize {
;
; X64-NDD-LABEL: cnt32_optsize:
; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: shrl %edi, %eax
+; X64-NDD-NEXT: shrl $1, %edi, %eax
; X64-NDD-NEXT: andl $1431655765, %eax # imm = 0x55555555
; X64-NDD-NEXT: subl %eax, %edi
; X64-NDD-NEXT: movl $858993459, %eax # imm = 0x33333333
@@ -882,7 +882,7 @@ define i64 @cnt64_optsize(i64 %x) nounwind readnone optsize {
;
; X64-NDD-LABEL: cnt64_optsize:
; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: shrq %rdi, %rax
+; X64-NDD-NEXT: shrq $1, %rdi, %rax
; X64-NDD-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555
; X64-NDD-NEXT: andq %rcx, %rax
; X64-NDD-NEXT: subq %rax, %rdi
@@ -1116,7 +1116,7 @@ define i128 @cnt128_optsize(i128 %x) nounwind readnone optsize {
;
; X64-NDD-LABEL: cnt128_optsize:
; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: shrq %rsi, %rax
+; X64-NDD-NEXT: shrq $1, %rsi, %rax
; X64-NDD-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555
; X64-NDD-NEXT: andq %rcx, %rax
; X64-NDD-NEXT: subq %rax, %rsi
@@ -1132,7 +1132,7 @@ define i128 @cnt128_optsize(i128 %x) nounwind readnone optsize {
; X64-NDD-NEXT: movabsq $72340172838076673, %r8 # imm = 0x101010101010101
; X64-NDD-NEXT: imulq %r8, %rdx
; X64-NDD-NEXT: shrq $56, %rdx
-; X64-NDD-NEXT: shrq %rdi, %r9
+; X64-NDD-NEXT: shrq $1, %rdi, %r9
; X64-NDD-NEXT: andq %r9, %rcx
; X64-NDD-NEXT: subq %rcx, %rdi
; X64-NDD-NEXT: andq %rax, %rdi, %rcx
@@ -1299,7 +1299,7 @@ define i32 @cnt32_pgso(i32 %x) nounwind readnone !prof !14 {
;
; X64-NDD-LABEL: cnt32_pgso:
; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: shrl %edi, %eax
+; X64-NDD-NEXT: shrl $1, %edi, %eax
; X64-NDD-NEXT: andl $1431655765, %eax # imm = 0x55555555
; X64-NDD-NEXT: subl %eax, %edi
; X64-NDD-NEXT: andl $858993459, %edi, %eax # imm = 0x33333333
@@ -1393,7 +1393,7 @@ define i64 @cnt64_pgso(i64 %x) nounwind readnone !prof !14 {
;
; X64-NDD-LABEL: cnt64_pgso:
; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: shrq %rdi, %rax
+; X64-NDD-NEXT: shrq $1, %rdi, %rax
; X64-NDD-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555
; X64-NDD-NEXT: andq %rcx, %rax
; X64-NDD-NEXT: subq %rax, %rdi
@@ -1618,7 +1618,7 @@ define i128 @cnt128_pgso(i128 %x) nounwind readnone !prof !14 {
;
; X64-NDD-LABEL: cnt128_pgso:
; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: shrq %rsi, %rax
+; X64-NDD-NEXT: shrq $1, %rsi, %rax
; X64-NDD-NEXT: movabsq $6148914691236517205, %rcx # imm = 0x5555555555555555
; X64-NDD-NEXT: andq %rcx, %rax
; X64-NDD-NEXT: subq %rax, %rsi
@@ -1634,7 +1634,7 @@ define i128 @cnt128_pgso(i128 %x) nounwind readnone !prof !14 {
; X64-NDD-NEXT: movabsq $72340172838076673, %r8 # imm = 0x101010101010101
; X64-NDD-NEXT: imulq %r8, %rdx
; X64-NDD-NEXT: shrq $56, %rdx
-; X64-NDD-NEXT: shrq %rdi, %r9
+; X64-NDD-NEXT: shrq $1, %rdi, %r9
; X64-NDD-NEXT: andq %r9, %rcx
; X64-NDD-NEXT: subq %rcx, %rdi
; X64-NDD-NEXT: andq %rax, %rdi, %rcx
@@ -1802,7 +1802,7 @@ define i32 @popcount_zext_i32(i16 zeroext %x) {
;
; X64-NDD-LABEL: popcount_zext_i32:
; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: shrl %edi, %eax
+; X64-NDD-NEXT: shrl $1, %edi, %eax
; X64-NDD-NEXT: andl $21845, %eax # imm = 0x5555
; X64-NDD-NEXT: subl %eax, %edi
; X64-NDD-NEXT: andl $858993459, %edi, %eax # imm = 0x33333333
@@ -1877,7 +1877,7 @@ define i32 @popcount_i16_zext(i16 zeroext %x) {
;
; X64-NDD-LABEL: popcount_i16_zext:
; X64-NDD: # %bb.0:
-; X64-NDD-NEXT: shrw %di, %ax
+; X64-NDD-NEXT: shrw $1, %di, %ax
; X64-NDD-NEXT: andw $21845, %ax # imm = 0x5555
; X64-NDD-NEXT: subw %ax, %di, %ax
; X64-NDD-NEXT: andw $13107, %ax, %cx # imm = 0x3333
diff --git a/llvm/test/MC/Disassembler/X86/apx/rol.txt b/llvm/test/MC/Disassembler/X86/apx/rol.txt
index bb713d1c88566..92298c36c49a9 100644
--- a/llvm/test/MC/Disassembler/X86/apx/rol.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/rol.txt
@@ -141,7 +141,7 @@
# INTEL: rol bl, bl
0x62,0xf4,0x64,0x18,0xd0,0xc3
-# ATT: {nf} rolb %bl, %bl
+# ATT: {nf} rolb $1, %bl, %bl
# INTEL: {nf} rol bl, bl
0x62,0xf4,0x64,0x1c,0xd0,0xc3
@@ -285,7 +285,7 @@
# INTEL: rol dx, dx
0x62,0xf4,0x6d,0x18,0xd1,0xc2
-# ATT: {nf} rolw %dx, %dx
+# ATT: {nf} rolw $1, %dx, %dx
# INTEL: {nf} rol dx, dx
0x62,0xf4,0x6d,0x1c,0xd1,0xc2
@@ -301,7 +301,7 @@
# INTEL: rol ecx, ecx
0x62,0xf4,0x74,0x18,0xd1,0xc1
-# ATT: {nf} roll %ecx, %ecx
+# ATT: {nf} roll $1, %ecx, %ecx
# INTEL: {nf} rol ecx, ecx
0x62,0xf4,0x74,0x1c,0xd1,0xc1
@@ -317,7 +317,7 @@
# INTEL: rol r9, r9
0x62,0xd4,0xb4,0x18,0xd1,0xc1
-# ATT: {nf} rolq %r9, %r9
+# ATT: {nf} rolq $1, %r9, %r9
# INTEL: {nf} rol r9, r9
0x62,0xd4,0xb4,0x1c,0xd1,0xc1
diff --git a/llvm/test/MC/Disassembler/X86/apx/ror.txt b/llvm/test/MC/Disassembler/X86/apx/ror.txt
index 484a3e143fdac..2a954f82d48a2 100644
--- a/llvm/test/MC/Disassembler/X86/apx/ror.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/ror.txt
@@ -141,7 +141,7 @@
# INTEL: ror bl, bl
0x62,0xf4,0x64,0x18,0xd0,0xcb
-# ATT: {nf} rorb %bl, %bl
+# ATT: {nf} rorb $1, %bl, %bl
# INTEL: {nf} ror bl, bl
0x62,0xf4,0x64,0x1c,0xd0,0xcb
@@ -285,7 +285,7 @@
# INTEL: ror dx, dx
0x62,0xf4,0x6d,0x18,0xd1,0xca
-# ATT: {nf} rorw %dx, %dx
+# ATT: {nf} rorw $1, %dx, %dx
# INTEL: {nf} ror dx, dx
0x62,0xf4,0x6d,0x1c,0xd1,0xca
@@ -301,7 +301,7 @@
# INTEL: ror ecx, ecx
0x62,0xf4,0x74,0x18,0xd1,0xc9
-# ATT: {nf} rorl %ecx, %ecx
+# ATT: {nf} rorl $1, %ecx, %ecx
# INTEL: {nf} ror ecx, ecx
0x62,0xf4,0x74,0x1c,0xd1,0xc9
@@ -317,7 +317,7 @@
# INTEL: ror r9, r9
0x62,0xd4,0xb4,0x18,0xd1,0xc9
-# ATT: {nf} rorq %r9, %r9
+# ATT: {nf} rorq $1, %r9, %r9
# INTEL: {nf} ror r9, r9
0x62,0xd4,0xb4,0x1c,0xd1,0xc9
diff --git a/llvm/test/MC/Disassembler/X86/apx/sar.txt b/llvm/test/MC/Disassembler/X86/apx/sar.txt
index b5e41ee956ccd..fca8b2ccec3ce 100644
--- a/llvm/test/MC/Disassembler/X86/apx/sar.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/sar.txt
@@ -141,7 +141,7 @@
# INTEL: sar bl, bl
0x62,0xf4,0x64,0x18,0xd0,0xfb
-# ATT: {nf} sarb %bl, %bl
+# ATT: {nf} sarb $1, %bl, %bl
# INTEL: {nf} sar bl, bl
0x62,0xf4,0x64,0x1c,0xd0,0xfb
@@ -285,7 +285,7 @@
# INTEL: sar dx, dx
0x62,0xf4,0x6d,0x18,0xd1,0xfa
-# ATT: {nf} sarw %dx, %dx
+# ATT: {nf} sarw $1, %dx, %dx
# INTEL: {nf} sar dx, dx
0x62,0xf4,0x6d,0x1c,0xd1,0xfa
@@ -301,7 +301,7 @@
# INTEL: sar ecx, ecx
0x62,0xf4,0x74,0x18,0xd1,0xf9
-# ATT: {nf} sarl %ecx, %ecx
+# ATT: {nf} sarl $1, %ecx, %ecx
# INTEL: {nf} sar ecx, ecx
0x62,0xf4,0x74,0x1c,0xd1,0xf9
@@ -317,7 +317,7 @@
# INTEL: sar r9, r9
0x62,0xd4,0xb4,0x18,0xd1,0xf9
-# ATT: {nf} sarq %r9, %r9
+# ATT: {nf} sarq $1, %r9, %r9
# INTEL: {nf} sar r9, r9
0x62,0xd4,0xb4,0x1c,0xd1,0xf9
diff --git a/llvm/test/MC/Disassembler/X86/apx/shl.txt b/llvm/test/MC/Disassembler/X86/apx/shl.txt
index 6f0b1b9a2af2e..3f2bb99526361 100644
--- a/llvm/test/MC/Disassembler/X86/apx/shl.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/shl.txt
@@ -141,7 +141,7 @@
# INTEL: shl bl, bl
0x62,0xf4,0x64,0x18,0xd0,0xe3
-# ATT: {nf} shlb %bl, %bl
+# ATT: {nf} shlb $1, %bl, %bl
# INTEL: {nf} shl bl, bl
0x62,0xf4,0x64,0x1c,0xd0,0xe3
@@ -285,7 +285,7 @@
# INTEL: shl dx, dx
0x62,0xf4,0x6d,0x18,0xd1,0xe2
-# ATT: {nf} shlw %dx, %dx
+# ATT: {nf} shlw $1, %dx, %dx
# INTEL: {nf} shl dx, dx
0x62,0xf4,0x6d,0x1c,0xd1,0xe2
@@ -301,7 +301,7 @@
# INTEL: shl ecx, ecx
0x62,0xf4,0x74,0x18,0xd1,0xe1
-# ATT: {nf} shll %ecx, %ecx
+# ATT: {nf} shll $1, %ecx, %ecx
# INTEL: {nf} shl ecx, ecx
0x62,0xf4,0x74,0x1c,0xd1,0xe1
@@ -317,7 +317,7 @@
# INTEL: shl r9, r9
0x62,0xd4,0xb4,0x18,0xd1,0xe1
-# ATT: {nf} shlq %r9, %r9
+# ATT: {nf} shlq $1, %r9, %r9
# INTEL: {nf} shl r9, r9
0x62,0xd4,0xb4,0x1c,0xd1,0xe1
diff --git a/llvm/test/MC/Disassembler/X86/apx/shr.txt b/llvm/test/MC/Disassembler/X86/apx/shr.txt
index 1e7e1732b56fb..2ac2e32d46466 100644
--- a/llvm/test/MC/Disassembler/X86/apx/shr.txt
+++ b/llvm/test/MC/Disassembler/X86/apx/shr.txt
@@ -141,7 +141,7 @@
# INTEL: shr bl, bl
0x62,0xf4,0x64,0x18,0xd0,0xeb
-# ATT: {nf} shrb %bl, %bl
+# ATT: {nf} shrb $1, %bl, %bl
# INTEL: {nf} shr bl, bl
0x62,0xf4,0x64,0x1c,0xd0,0xeb
@@ -285,7 +285,7 @@
# INTEL: shr dx, dx
0x62,0xf4,0x6d,0x18,0xd1,0xea
-# ATT: {nf} shrw %dx, %dx
+# ATT: {nf} shrw $1, %dx, %dx
# INTEL: {nf} shr dx, dx
0x62,0xf4,0x6d,0x1c,0xd1,0xea
@@ -301,7 +301,7 @@
# INTEL: shr ecx, ecx
0x62,0xf4,0x74,0x18,0xd1,0xe9
-# ATT: {nf} shrl %ecx, %ecx
+# ATT: {nf} shrl $1, %ecx, %ecx
# INTEL: {nf} shr ecx, ecx
0x62,0xf4,0x74,0x1c,0xd1,0xe9
@@ -317,7 +317,7 @@
# INTEL: shr r9, r9
0x62,0xd4,0xb4,0x18,0xd1,0xe9
-# ATT: {nf} shrq %r9, %r9
+# ATT: {nf} shrq $1, %r9, %r9
# INTEL: {nf} shr r9, r9
0x62,0xd4,0xb4,0x1c,0xd1,0xe9
diff --git a/llvm/test/MC/X86/apx/rol-att.s b/llvm/test/MC/X86/apx/rol-att.s
index 30c1c3a9ffe4c..494d86e61053d 100644
--- a/llvm/test/MC/X86/apx/rol-att.s
+++ b/llvm/test/MC/X86/apx/rol-att.s
@@ -210,9 +210,9 @@
# CHECK: rolw %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x18,0xd1,0xc2]
rolw %dx, %dx
-# CHECK: {nf} rolw %dx, %dx
+# CHECK: {nf} rolw $1, %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xc2]
- {nf} rolw %dx, %dx
+ {nf} rolw $1, %dx, %dx
# CHECK: {evex} roll %ecx
# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd1,0xc1]
{evex} roll %ecx
@@ -222,9 +222,9 @@
# CHECK: roll %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x18,0xd1,0xc1]
roll %ecx, %ecx
-# CHECK: {nf} roll %ecx, %ecx
+# CHECK: {nf} roll $1, %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x1c,0xd1,0xc1]
- {nf} roll %ecx, %ecx
+ {nf} roll $1, %ecx, %ecx
# CHECK: {evex} rolq %r9
# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xd1,0xc1]
{evex} rolq %r9
@@ -234,9 +234,9 @@
# CHECK: rolq %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x18,0xd1,0xc1]
rolq %r9, %r9
-# CHECK: {nf} rolq %r9, %r9
+# CHECK: {nf} rolq $1, %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x1c,0xd1,0xc1]
- {nf} rolq %r9, %r9
+ {nf} rolq $1, %r9, %r9
# CHECK: {evex} rolb 291(%r8,%rax,4)
# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd0,0x84,0x80,0x23,0x01,0x00,0x00]
{evex} rolb 291(%r8,%rax,4)
diff --git a/llvm/test/MC/X86/apx/rol-encopt.s b/llvm/test/MC/X86/apx/rol-encopt.s
index d154779d1f626..b4e94c125eb6c 100644
--- a/llvm/test/MC/X86/apx/rol-encopt.s
+++ b/llvm/test/MC/X86/apx/rol-encopt.s
@@ -36,16 +36,16 @@
# CHECK: rolq %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x18,0xd1,0xc0]
rolq $1, %rax, %rbx
-# CHECK: {nf} rolb %al, %bl
+# CHECK: {nf} rolb $1, %al, %bl
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd0,0xc0]
{nf} rolb $1, %al, %bl
-# CHECK: {nf} rolw %ax, %bx
+# CHECK: {nf} rolw $1, %ax, %bx
# CHECK: encoding: [0x62,0xf4,0x65,0x1c,0xd1,0xc0]
{nf} rolw $1, %ax, %bx
-# CHECK: {nf} roll %eax, %ebx
+# CHECK: {nf} roll $1, %eax, %ebx
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd1,0xc0]
{nf} roll $1, %eax, %ebx
-# CHECK: {nf} rolq %rax, %rbx
+# CHECK: {nf} rolq $1, %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x1c,0xd1,0xc0]
{nf} rolq $1, %rax, %rbx
# CHECK: {evex} rolb 123(%r8,%rax,4)
diff --git a/llvm/test/MC/X86/apx/ror-att.s b/llvm/test/MC/X86/apx/ror-att.s
index aa877f20e4e5d..70338ad7d20e1 100644
--- a/llvm/test/MC/X86/apx/ror-att.s
+++ b/llvm/test/MC/X86/apx/ror-att.s
@@ -210,9 +210,9 @@
# CHECK: rorw %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x18,0xd1,0xca]
rorw %dx, %dx
-# CHECK: {nf} rorw %dx, %dx
+# CHECK: {nf} rorw $1, %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xca]
- {nf} rorw %dx, %dx
+ {nf} rorw $1, %dx, %dx
# CHECK: {evex} rorl %ecx
# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd1,0xc9]
{evex} rorl %ecx
@@ -222,9 +222,9 @@
# CHECK: rorl %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x18,0xd1,0xc9]
rorl %ecx, %ecx
-# CHECK: {nf} rorl %ecx, %ecx
+# CHECK: {nf} rorl $1, %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x1c,0xd1,0xc9]
- {nf} rorl %ecx, %ecx
+ {nf} rorl $1, %ecx, %ecx
# CHECK: {evex} rorq %r9
# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xd1,0xc9]
{evex} rorq %r9
@@ -234,9 +234,9 @@
# CHECK: rorq %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x18,0xd1,0xc9]
rorq %r9, %r9
-# CHECK: {nf} rorq %r9, %r9
+# CHECK: {nf} rorq $1, %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x1c,0xd1,0xc9]
- {nf} rorq %r9, %r9
+ {nf} rorq $1, %r9, %r9
# CHECK: {evex} rorb 291(%r8,%rax,4)
# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd0,0x8c,0x80,0x23,0x01,0x00,0x00]
{evex} rorb 291(%r8,%rax,4)
diff --git a/llvm/test/MC/X86/apx/ror-encopt.s b/llvm/test/MC/X86/apx/ror-encopt.s
index f1033a60f7d5c..c86bd99a66f65 100644
--- a/llvm/test/MC/X86/apx/ror-encopt.s
+++ b/llvm/test/MC/X86/apx/ror-encopt.s
@@ -36,16 +36,16 @@
# CHECK: rorq %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x18,0xd1,0xc8]
rorq $1, %rax, %rbx
-# CHECK: {nf} rorb %al, %bl
+# CHECK: {nf} rorb $1, %al, %bl
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd0,0xc8]
{nf} rorb $1, %al, %bl
-# CHECK: {nf} rorw %ax, %bx
+# CHECK: {nf} rorw $1, %ax, %bx
# CHECK: encoding: [0x62,0xf4,0x65,0x1c,0xd1,0xc8]
{nf} rorw $1, %ax, %bx
-# CHECK: {nf} rorl %eax, %ebx
+# CHECK: {nf} rorl $1, %eax, %ebx
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd1,0xc8]
{nf} rorl $1, %eax, %ebx
-# CHECK: {nf} rorq %rax, %rbx
+# CHECK: {nf} rorq $1, %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x1c,0xd1,0xc8]
{nf} rorq $1, %rax, %rbx
# CHECK: {evex} rorb 123(%r8,%rax,4)
diff --git a/llvm/test/MC/X86/apx/sar-att.s b/llvm/test/MC/X86/apx/sar-att.s
index 9ab96f277bc70..eb80497b7291c 100644
--- a/llvm/test/MC/X86/apx/sar-att.s
+++ b/llvm/test/MC/X86/apx/sar-att.s
@@ -210,9 +210,9 @@
# CHECK: sarw %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x18,0xd1,0xfa]
sarw %dx, %dx
-# CHECK: {nf} sarw %dx, %dx
+# CHECK: {nf} sarw $1, %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xfa]
- {nf} sarw %dx, %dx
+ {nf} sarw $1, %dx, %dx
# CHECK: {evex} sarl %ecx
# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd1,0xf9]
{evex} sarl %ecx
@@ -222,9 +222,9 @@
# CHECK: sarl %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x18,0xd1,0xf9]
sarl %ecx, %ecx
-# CHECK: {nf} sarl %ecx, %ecx
+# CHECK: {nf} sarl $1, %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x1c,0xd1,0xf9]
- {nf} sarl %ecx, %ecx
+ {nf} sarl $1, %ecx, %ecx
# CHECK: {evex} sarq %r9
# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xd1,0xf9]
{evex} sarq %r9
@@ -234,9 +234,9 @@
# CHECK: sarq %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x18,0xd1,0xf9]
sarq %r9, %r9
-# CHECK: {nf} sarq %r9, %r9
+# CHECK: {nf} sarq $1, %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x1c,0xd1,0xf9]
- {nf} sarq %r9, %r9
+ {nf} sarq $1, %r9, %r9
# CHECK: {evex} sarb 291(%r8,%rax,4)
# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd0,0xbc,0x80,0x23,0x01,0x00,0x00]
{evex} sarb 291(%r8,%rax,4)
diff --git a/llvm/test/MC/X86/apx/sar-encopt.s b/llvm/test/MC/X86/apx/sar-encopt.s
index 1399536bf1f7c..a85a17ff706ee 100644
--- a/llvm/test/MC/X86/apx/sar-encopt.s
+++ b/llvm/test/MC/X86/apx/sar-encopt.s
@@ -36,16 +36,16 @@
# CHECK: sarq %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x18,0xd1,0xf8]
sarq $1, %rax, %rbx
-# CHECK: {nf} sarb %al, %bl
+# CHECK: {nf} sarb $1, %al, %bl
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd0,0xf8]
{nf} sarb $1, %al, %bl
-# CHECK: {nf} sarw %ax, %bx
+# CHECK: {nf} sarw $1, %ax, %bx
# CHECK: encoding: [0x62,0xf4,0x65,0x1c,0xd1,0xf8]
{nf} sarw $1, %ax, %bx
-# CHECK: {nf} sarl %eax, %ebx
+# CHECK: {nf} sarl $1, %eax, %ebx
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd1,0xf8]
{nf} sarl $1, %eax, %ebx
-# CHECK: {nf} sarq %rax, %rbx
+# CHECK: {nf} sarq $1, %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x1c,0xd1,0xf8]
{nf} sarq $1, %rax, %rbx
# CHECK: {evex} sarb 123(%r8,%rax,4)
diff --git a/llvm/test/MC/X86/apx/shift-one-att.s b/llvm/test/MC/X86/apx/shift-one-att.s
new file mode 100644
index 0000000000000..ee5f3b0b7720e
--- /dev/null
+++ b/llvm/test/MC/X86/apx/shift-one-att.s
@@ -0,0 +1,81 @@
+# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s
+
+# CHECK: {nf} shlb $1, %cl, %dl
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd0,0xe1]
+{nf} shlb $1, %cl, %dl
+
+# CHECK: {nf} shlw $1, %cx, %dx
+# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xe1]
+{nf} shlw $1, %cx, %dx
+
+# CHECK: {nf} shll $1, %ecx, %edx
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd1,0xe1]
+{nf} shll $1, %ecx, %edx
+
+# CHECK: {nf} shlq $1, %rcx, %rdx
+# CHECK: encoding: [0x62,0xf4,0xec,0x1c,0xd1,0xe1]
+{nf} shlq $1, %rcx, %rdx
+
+# CHECK: {nf} shrb $1, %cl, %dl
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd0,0xe9]
+{nf} shrb $1, %cl, %dl
+
+# CHECK: {nf} shrw $1, %cx, %dx
+# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xe9]
+{nf} shrw $1, %cx, %dx
+
+# CHECK: {nf} shrl $1, %ecx, %edx
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd1,0xe9]
+{nf} shrl $1, %ecx, %edx
+
+# CHECK: {nf} shrq $1, %rcx, %rdx
+# CHECK: encoding: [0x62,0xf4,0xec,0x1c,0xd1,0xe9]
+{nf} shrq $1, %rcx, %rdx
+
+# CHECK: {nf} sarb $1, %cl, %dl
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd0,0xf9]
+{nf} sarb $1, %cl, %dl
+
+# CHECK: {nf} sarw $1, %cx, %dx
+# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xf9]
+{nf} sarw $1, %cx, %dx
+
+# CHECK: {nf} sarl $1, %ecx, %edx
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd1,0xf9]
+{nf} sarl $1, %ecx, %edx
+
+# CHECK: {nf} sarq $1, %rcx, %rdx
+# CHECK: encoding: [0x62,0xf4,0xec,0x1c,0xd1,0xf9]
+{nf} sarq $1, %rcx, %rdx
+
+# CHECK: {nf} rolb $1, %cl, %dl
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd0,0xc1]
+{nf} rolb $1, %cl, %dl
+
+# CHECK: {nf} rolw $1, %cx, %dx
+# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xc1]
+{nf} rolw $1, %cx, %dx
+
+# CHECK: {nf} roll $1, %ecx, %edx
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd1,0xc1]
+{nf} roll $1, %ecx, %edx
+
+# CHECK: {nf} rolq $1, %rcx, %rdx
+# CHECK: encoding: [0x62,0xf4,0xec,0x1c,0xd1,0xc1]
+{nf} rolq $1, %rcx, %rdx
+
+# CHECK: {nf} rorb $1, %cl, %dl
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd0,0xc9]
+{nf} rorb $1, %cl, %dl
+
+# CHECK: {nf} rorw $1, %cx, %dx
+# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xc9]
+{nf} rorw $1, %cx, %dx
+
+# CHECK: {nf} rorl $1, %ecx, %edx
+# CHECK: encoding: [0x62,0xf4,0x6c,0x1c,0xd1,0xc9]
+{nf} rorl $1, %ecx, %edx
+
+# CHECK: {nf} rorq $1, %rcx, %rdx
+# CHECK: encoding: [0x62,0xf4,0xec,0x1c,0xd1,0xc9]
+{nf} rorq $1, %rcx, %rdx
diff --git a/llvm/test/MC/X86/apx/shl-att.s b/llvm/test/MC/X86/apx/shl-att.s
index d86f6cf05a7db..a523c0767ac3b 100644
--- a/llvm/test/MC/X86/apx/shl-att.s
+++ b/llvm/test/MC/X86/apx/shl-att.s
@@ -210,9 +210,9 @@
# CHECK: shlw %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x18,0xd1,0xe2]
shlw %dx, %dx
-# CHECK: {nf} shlw %dx, %dx
+# CHECK: {nf} shlw $1, %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xe2]
- {nf} shlw %dx, %dx
+ {nf} shlw $1, %dx, %dx
# CHECK: {evex} shll %ecx
# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd1,0xe1]
{evex} shll %ecx
@@ -222,9 +222,9 @@
# CHECK: shll %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x18,0xd1,0xe1]
shll %ecx, %ecx
-# CHECK: {nf} shll %ecx, %ecx
+# CHECK: {nf} shll $1, %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x1c,0xd1,0xe1]
- {nf} shll %ecx, %ecx
+ {nf} shll $1, %ecx, %ecx
# CHECK: {evex} shlq %r9
# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xd1,0xe1]
{evex} shlq %r9
@@ -234,9 +234,9 @@
# CHECK: shlq %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x18,0xd1,0xe1]
shlq %r9, %r9
-# CHECK: {nf} shlq %r9, %r9
+# CHECK: {nf} shlq $1, %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x1c,0xd1,0xe1]
- {nf} shlq %r9, %r9
+ {nf} shlq $1, %r9, %r9
# CHECK: {evex} shlb 291(%r8,%rax,4)
# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd0,0xa4,0x80,0x23,0x01,0x00,0x00]
{evex} shlb 291(%r8,%rax,4)
diff --git a/llvm/test/MC/X86/apx/shl-encopt.s b/llvm/test/MC/X86/apx/shl-encopt.s
index 0feeddc140064..5225c867a970d 100644
--- a/llvm/test/MC/X86/apx/shl-encopt.s
+++ b/llvm/test/MC/X86/apx/shl-encopt.s
@@ -36,16 +36,16 @@
# CHECK: shlq %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x18,0xd1,0xe0]
shlq $1, %rax, %rbx
-# CHECK: {nf} shlb %al, %bl
+# CHECK: {nf} shlb $1, %al, %bl
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd0,0xe0]
{nf} shlb $1, %al, %bl
-# CHECK: {nf} shlw %ax, %bx
+# CHECK: {nf} shlw $1, %ax, %bx
# CHECK: encoding: [0x62,0xf4,0x65,0x1c,0xd1,0xe0]
{nf} shlw $1, %ax, %bx
-# CHECK: {nf} shll %eax, %ebx
+# CHECK: {nf} shll $1, %eax, %ebx
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd1,0xe0]
{nf} shll $1, %eax, %ebx
-# CHECK: {nf} shlq %rax, %rbx
+# CHECK: {nf} shlq $1, %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x1c,0xd1,0xe0]
{nf} shlq $1, %rax, %rbx
# CHECK: {evex} shlb 123(%r8,%rax,4)
diff --git a/llvm/test/MC/X86/apx/shr-att.s b/llvm/test/MC/X86/apx/shr-att.s
index 86656c325de2a..934536422d199 100644
--- a/llvm/test/MC/X86/apx/shr-att.s
+++ b/llvm/test/MC/X86/apx/shr-att.s
@@ -210,9 +210,9 @@
# CHECK: shrw %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x18,0xd1,0xea]
shrw %dx, %dx
-# CHECK: {nf} shrw %dx, %dx
+# CHECK: {nf} shrw $1, %dx, %dx
# CHECK: encoding: [0x62,0xf4,0x6d,0x1c,0xd1,0xea]
- {nf} shrw %dx, %dx
+ {nf} shrw $1, %dx, %dx
# CHECK: {evex} shrl %ecx
# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xd1,0xe9]
{evex} shrl %ecx
@@ -222,9 +222,9 @@
# CHECK: shrl %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x18,0xd1,0xe9]
shrl %ecx, %ecx
-# CHECK: {nf} shrl %ecx, %ecx
+# CHECK: {nf} shrl $1, %ecx, %ecx
# CHECK: encoding: [0x62,0xf4,0x74,0x1c,0xd1,0xe9]
- {nf} shrl %ecx, %ecx
+ {nf} shrl $1, %ecx, %ecx
# CHECK: {evex} shrq %r9
# CHECK: encoding: [0x62,0xd4,0xfc,0x08,0xd1,0xe9]
{evex} shrq %r9
@@ -234,9 +234,9 @@
# CHECK: shrq %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x18,0xd1,0xe9]
shrq %r9, %r9
-# CHECK: {nf} shrq %r9, %r9
+# CHECK: {nf} shrq $1, %r9, %r9
# CHECK: encoding: [0x62,0xd4,0xb4,0x1c,0xd1,0xe9]
- {nf} shrq %r9, %r9
+ {nf} shrq $1, %r9, %r9
# CHECK: {evex} shrb 291(%r8,%rax,4)
# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xd0,0xac,0x80,0x23,0x01,0x00,0x00]
{evex} shrb 291(%r8,%rax,4)
diff --git a/llvm/test/MC/X86/apx/shr-encopt.s b/llvm/test/MC/X86/apx/shr-encopt.s
index 97b6b70086573..b8ec4c18b685c 100644
--- a/llvm/test/MC/X86/apx/shr-encopt.s
+++ b/llvm/test/MC/X86/apx/shr-encopt.s
@@ -36,16 +36,16 @@
# CHECK: shrq %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x18,0xd1,0xe8]
shrq $1, %rax, %rbx
-# CHECK: {nf} shrb %al, %bl
+# CHECK: {nf} shrb $1, %al, %bl
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd0,0xe8]
{nf} shrb $1, %al, %bl
-# CHECK: {nf} shrw %ax, %bx
+# CHECK: {nf} shrw $1, %ax, %bx
# CHECK: encoding: [0x62,0xf4,0x65,0x1c,0xd1,0xe8]
{nf} shrw $1, %ax, %bx
-# CHECK: {nf} shrl %eax, %ebx
+# CHECK: {nf} shrl $1, %eax, %ebx
# CHECK: encoding: [0x62,0xf4,0x64,0x1c,0xd1,0xe8]
{nf} shrl $1, %eax, %ebx
-# CHECK: {nf} shrq %rax, %rbx
+# CHECK: {nf} shrq $1, %rax, %rbx
# CHECK: encoding: [0x62,0xf4,0xe4,0x1c,0xd1,0xe8]
{nf} shrq $1, %rax, %rbx
# CHECK: {evex} shrb 123(%r8,%rax,4)
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