[llvm] AMDGPU: Perform libcall recognition to replace fast OpenCL pow (PR #182135)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 18 12:50:48 PST 2026
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/182135
If a float-typed call site is marked with afn, replace the 4
flavors of pow with a faster variant.
This transforms pow, powr, pown, and rootn to __pow_fast,
__powr_fast, __pown_fast, and __rootn_fast if available. Also
attempts to handle all of the same basic folds on the new fast
variants that were already performed with the base forms. This
maintains optimizations with OpenCL when the device libs unsafe
math control library is deleted. This maintains the status quo
of how libcalls work, and only handles 4 new entry points. This
only helps with the elimination of the control library, and not
general libcall emission problems.
This makes no practical difference for HIP, which is the status
quo for libcall optimizations. AMDGPULibCalls recognizes the OpenCL
mangled names. e.g., OpenCL float "pow" is really _Z3powff but the
HIP provided function "powf" is really named _ZL4powfff, and std::pow
with float is _ZL3powff. The pass still runs for HIP, so by accident
if you used the OpenCL mangled function names, this would trigger.
Since the functions cannot yet be relied on from the library,
introduce a temporary module flag check. I'm not planning on emitting
it anywhere and it's a poor substitute for versioning the target.
>From 88c31b0786fd5de382510cc66fa7c1e2e9536f71 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Wed, 28 Jan 2026 10:05:31 +0100
Subject: [PATCH] AMDGPU: Perform libcall recognition to replace fast OpenCL
pow
If a float-typed call site is marked with afn, replace the 4
flavors of pow with a faster variant.
This transforms pow, powr, pown, and rootn to __pow_fast,
__powr_fast, __pown_fast, and __rootn_fast if available. Also
attempts to handle all of the same basic folds on the new fast
variants that were already performed with the base forms. This
maintains optimizations with OpenCL when the device libs unsafe
math control library is deleted. This maintains the status quo
of how libcalls work, and only handles 4 new entry points. This
only helps with the elimination of the control library, and not
general libcall emission problems.
This makes no practical difference for HIP, which is the status
quo for libcall optimizations. AMDGPULibCalls recognizes the OpenCL
mangled names. e.g., OpenCL float "pow" is really _Z3powff but the
HIP provided function "powf" is really named _ZL4powfff, and std::pow
with float is _ZL3powff. The pass still runs for HIP, so by accident
if you used the OpenCL mangled function names, this would trigger.
Since the functions cannot yet be relied on from the library,
introduce a temporary module flag check. I'm not planning on emitting
it anywhere and it's a poor substitute for versioning the target.
---
llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp | 123 +-
llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp | 19 +
llvm/lib/Target/AMDGPU/AMDGPULibFunc.h | 4 +
.../amdgpu-simplify-libcall-pow-codegen.ll | 51 +-
.../amdgpu-simplify-libcall-pow-fast.ll | 658 ++
.../AMDGPU/amdgpu-simplify-libcall-pow.ll | 5871 ++++++++++++-----
.../amdgpu-simplify-libcall-pown-fast.ll | 566 ++
.../AMDGPU/amdgpu-simplify-libcall-pown.ll | 296 +-
.../amdgpu-simplify-libcall-powr-fast.ll | 487 ++
.../AMDGPU/amdgpu-simplify-libcall-powr.ll | 2125 +++---
.../amdgpu-simplify-libcall-rootn-fast.ll | 452 ++
.../AMDGPU/amdgpu-simplify-libcall-rootn.ll | 1075 +--
12 files changed, 8495 insertions(+), 3232 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-fast.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown-fast.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr-fast.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-fast.ll
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp b/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
index d0c13d154995d..54aac24d95dbe 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
@@ -63,6 +63,19 @@ class AMDGPULibCalls {
// "FuncName" exists. It may create a new function prototype in pre-link mode.
FunctionCallee getFunction(Module *M, const FuncInfo &fInfo);
+ /// Wrapper around getFunction which tries to use a faster variant if
+ /// available, and falls back to a less fast option.
+ ///
+ /// Return a replacement function for \p fInfo that has float-typed fast
+ /// variants. \p NewFunc is a base replacement function to use. \p
+ /// NewFuncFastVariant is a faster version to use if the calling context knows
+ /// it's legal. If there is no fast variant to use, \p NewFuncFastVariant
+ /// should be EI_NONE.
+ FunctionCallee getFloatFastVariant(Module *M, const FuncInfo &fInfo,
+ FuncInfo &newInfo,
+ AMDGPULibFunc::EFuncId NewFunc,
+ AMDGPULibFunc::EFuncId NewFuncFastVariant);
+
bool parseFunctionName(const StringRef &FMangledName, FuncInfo &FInfo);
bool TDOFold(CallInst *CI, const FuncInfo &FInfo);
@@ -410,6 +423,22 @@ FunctionCallee AMDGPULibCalls::getFunction(Module *M, const FuncInfo &fInfo) {
: AMDGPULibFunc::getFunction(M, fInfo);
}
+FunctionCallee AMDGPULibCalls::getFloatFastVariant(
+ Module *M, const FuncInfo &fInfo, FuncInfo &newInfo,
+ AMDGPULibFunc::EFuncId NewFunc, AMDGPULibFunc::EFuncId FastVariant) {
+ assert(NewFunc != FastVariant);
+
+ if (FastVariant != AMDGPULibFunc::EI_NONE &&
+ getArgType(fInfo) == AMDGPULibFunc::F32) {
+ newInfo = AMDGPULibFunc(FastVariant, fInfo);
+ if (FunctionCallee NewCallee = getFunction(M, newInfo))
+ return NewCallee;
+ }
+
+ newInfo = AMDGPULibFunc(NewFunc, fInfo);
+ return getFunction(M, newInfo);
+}
+
bool AMDGPULibCalls::parseFunctionName(const StringRef &FMangledName,
FuncInfo &FInfo) {
return AMDGPULibFunc::parse(FMangledName, FInfo);
@@ -680,12 +709,21 @@ bool AMDGPULibCalls::fold(CallInst *CI) {
{CI->getType(), CI->getArgOperand(1)->getType()}));
return true;
}
- case AMDGPULibFunc::EI_POW: {
+ case AMDGPULibFunc::EI_POW:
+ case AMDGPULibFunc::EI_POW_FAST: {
Module *M = Callee->getParent();
- AMDGPULibFunc PowrInfo(AMDGPULibFunc::EI_POWR, FInfo);
- FunctionCallee PowrFunc = getFunction(M, PowrInfo);
CallInst *Call = cast<CallInst>(FPOp);
+ FuncInfo PowrInfo;
+ AMDGPULibFunc::EFuncId FastPowrFuncId =
+ FMF.approxFunc() || FInfo.getId() == AMDGPULibFunc::EI_POW_FAST
+ ? AMDGPULibFunc::EI_POWR_FAST
+ : AMDGPULibFunc::EI_NONE;
+ FunctionCallee PowrFunc = getFloatFastVariant(
+ M, FInfo, PowrInfo, AMDGPULibFunc::EI_POWR, FastPowrFuncId);
+
+ // TODO: Prefer fast pown to fast powr, but slow powr to slow pown.
+
// pow(x, y) -> powr(x, y) for x >= -0.0
// TODO: Account for flags on current call
if (PowrFunc && cannotBeOrderedLessThanZero(
@@ -698,8 +736,15 @@ bool AMDGPULibCalls::fold(CallInst *CI) {
if (isKnownIntegral(FPOp->getOperand(1), SQ.getWithInstruction(CI),
FPOp->getFastMathFlags())) {
FunctionType *PownType = getPownType(CI->getFunctionType());
- AMDGPULibFunc PownInfo(AMDGPULibFunc::EI_POWN, PownType, true);
- FunctionCallee PownFunc = getFunction(M, PownInfo);
+
+ FuncInfo PownInfo;
+ AMDGPULibFunc::EFuncId FastPownFuncId =
+ FMF.approxFunc() || FInfo.getId() == AMDGPULibFunc::EI_POW_FAST
+ ? AMDGPULibFunc::EI_POWN_FAST
+ : AMDGPULibFunc::EI_NONE;
+ FunctionCallee PownFunc = getFloatFastVariant(
+ M, FInfo, PownInfo, AMDGPULibFunc::EI_POWN, FastPownFuncId);
+
if (PownFunc) {
// TODO: If the incoming integral value is an sitofp/uitofp, it won't
// fold out without a known range. We can probably take the source
@@ -721,30 +766,78 @@ bool AMDGPULibCalls::fold(CallInst *CI) {
if (!FMF.approxFunc())
return false;
+
+ if (FInfo.getId() == AMDGPULibFunc::EI_POW && FMF.approxFunc() &&
+ getArgType(FInfo) == AMDGPULibFunc::F32) {
+ AMDGPULibFunc PowFastInfo(AMDGPULibFunc::EI_POW_FAST, FInfo);
+ if (FunctionCallee PowFastFunc = getFunction(M, PowFastInfo)) {
+ Call->setCalledFunction(PowFastFunc);
+ return fold_pow(FPOp, B, PowFastInfo) || true;
+ }
+ }
+
return expandFastPow(FPOp, B, PowKind::Pow);
}
case AMDGPULibFunc::EI_POWR:
+ case AMDGPULibFunc::EI_POWR_FAST: {
if (fold_pow(FPOp, B, FInfo))
return true;
if (!FMF.approxFunc())
return false;
+
+ if (FInfo.getId() == AMDGPULibFunc::EI_POWR && FMF.approxFunc() &&
+ getArgType(FInfo) == AMDGPULibFunc::F32) {
+ Module *M = Callee->getParent();
+ AMDGPULibFunc PowrFastInfo(AMDGPULibFunc::EI_POWR_FAST, FInfo);
+ if (FunctionCallee PowrFastFunc = getFunction(M, PowrFastInfo)) {
+ CI->setCalledFunction(PowrFastFunc);
+ return true;
+ }
+ }
+
if (!shouldReplaceLibcallWithIntrinsic(CI))
return false;
return expandFastPow(FPOp, B, PowKind::PowR);
+ }
case AMDGPULibFunc::EI_POWN:
+ case AMDGPULibFunc::EI_POWN_FAST: {
if (fold_pow(FPOp, B, FInfo))
return true;
if (!FMF.approxFunc())
return false;
+
+ if (FInfo.getId() == AMDGPULibFunc::EI_POWN &&
+ getArgType(FInfo) == AMDGPULibFunc::F32) {
+ Module *M = Callee->getParent();
+ AMDGPULibFunc PownFastInfo(AMDGPULibFunc::EI_POWN_FAST, FInfo);
+ if (FunctionCallee PownFastFunc = getFunction(M, PownFastInfo)) {
+ CI->setCalledFunction(PownFastFunc);
+ return true;
+ }
+ }
+
if (!shouldReplaceLibcallWithIntrinsic(CI))
return false;
return expandFastPow(FPOp, B, PowKind::PowN);
+ }
case AMDGPULibFunc::EI_ROOTN:
+ case AMDGPULibFunc::EI_ROOTN_FAST: {
if (fold_rootn(FPOp, B, FInfo))
return true;
if (!FMF.approxFunc())
return false;
+
+ if (getArgType(FInfo) == AMDGPULibFunc::F32) {
+ Module *M = Callee->getParent();
+ AMDGPULibFunc RootnFastInfo(AMDGPULibFunc::EI_ROOTN_FAST, FInfo);
+ if (FunctionCallee RootnFastFunc = getFunction(M, RootnFastInfo)) {
+ CI->setCalledFunction(RootnFastFunc);
+ return true;
+ }
+ }
+
return expandFastPow(FPOp, B, PowKind::RootN);
+ }
case AMDGPULibFunc::EI_SQRT:
// TODO: Allow with strictfp + constrained intrinsic
return tryReplaceLibcallWithSimpleIntrinsic(
@@ -846,8 +939,11 @@ static double log2(double V) {
bool AMDGPULibCalls::fold_pow(FPMathOperator *FPOp, IRBuilder<> &B,
const FuncInfo &FInfo) {
assert((FInfo.getId() == AMDGPULibFunc::EI_POW ||
+ FInfo.getId() == AMDGPULibFunc::EI_POW_FAST ||
FInfo.getId() == AMDGPULibFunc::EI_POWR ||
- FInfo.getId() == AMDGPULibFunc::EI_POWN) &&
+ FInfo.getId() == AMDGPULibFunc::EI_POWR_FAST ||
+ FInfo.getId() == AMDGPULibFunc::EI_POWN ||
+ FInfo.getId() == AMDGPULibFunc::EI_POWN_FAST) &&
"fold_pow: encounter a wrong function call");
Module *M = B.GetInsertBlock()->getModule();
@@ -1000,18 +1096,21 @@ bool AMDGPULibCalls::fold_pow(FPMathOperator *FPOp, IRBuilder<> &B,
V = log2(std::abs(V));
cnval = ConstantFP::get(eltType, V);
- needcopysign = (FInfo.getId() != AMDGPULibFunc::EI_POWR) &&
+ needcopysign = (FInfo.getId() != AMDGPULibFunc::EI_POWR &&
+ FInfo.getId() != AMDGPULibFunc::EI_POWR_FAST) &&
CF->isNegative();
} else {
needlog = true;
- needcopysign = needabs = FInfo.getId() != AMDGPULibFunc::EI_POWR;
+ needcopysign = needabs = FInfo.getId() != AMDGPULibFunc::EI_POWR &&
+ FInfo.getId() != AMDGPULibFunc::EI_POWR_FAST;
}
} else {
ConstantDataVector *CDV = dyn_cast<ConstantDataVector>(opr0);
if (!CDV) {
needlog = true;
- needcopysign = needabs = FInfo.getId() != AMDGPULibFunc::EI_POWR;
+ needcopysign = needabs = FInfo.getId() != AMDGPULibFunc::EI_POWR &&
+ FInfo.getId() != AMDGPULibFunc::EI_POWR_FAST;
} else {
assert ((int)CDV->getNumElements() == getVecSize(FInfo) &&
"Wrong vector size detected");
@@ -1036,7 +1135,8 @@ bool AMDGPULibCalls::fold_pow(FPMathOperator *FPOp, IRBuilder<> &B,
}
}
- if (needcopysign && (FInfo.getId() == AMDGPULibFunc::EI_POW)) {
+ if (needcopysign && (FInfo.getId() == AMDGPULibFunc::EI_POW ||
+ FInfo.getId() == AMDGPULibFunc::EI_POW_FAST)) {
// We cannot handle corner cases for a general pow() function, give up
// unless y is a constant integral value. Then proceed as if it were pown.
if (!isKnownIntegral(opr1, SQ.getWithInstruction(cast<Instruction>(FPOp)),
@@ -1064,7 +1164,8 @@ bool AMDGPULibCalls::fold_pow(FPMathOperator *FPOp, IRBuilder<> &B,
nval = CreateCallEx(B,LogExpr, nval, "__log2");
}
- if (FInfo.getId() == AMDGPULibFunc::EI_POWN) {
+ if (FInfo.getId() == AMDGPULibFunc::EI_POWN ||
+ FInfo.getId() == AMDGPULibFunc::EI_POWN_FAST) {
// convert int(32) to fp(f32 or f64)
opr1 = B.CreateSIToFP(opr1, nval->getType(), "pownI2F");
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp b/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
index 82233c0c891ad..68d617e343b99 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
@@ -254,8 +254,11 @@ static constexpr ManglingRule manglingRules[] = {
{ "normalize" , {1}, {E_ANY}},
{ "popcount" , {1}, {E_ANY}},
{ "pow" , {1}, {E_ANY,E_COPY}},
+{ "__pow_fast" , {1}, {E_ANY,E_COPY}},
{ "pown" , {1}, {E_ANY,E_SETBASE_I32}},
+{ "__pown_fast" , {1}, {E_ANY,E_SETBASE_I32}},
{ "powr" , {1}, {E_ANY,E_COPY}},
+{ "__powr_fast" , {1}, {E_ANY,E_COPY}},
{ "prefetch" , {1}, {E_CONSTPTR_ANY,EX_SIZET}},
{ "radians" , {1}, {E_ANY}},
{ "recip" , {1}, {E_ANY}},
@@ -266,6 +269,7 @@ static constexpr ManglingRule manglingRules[] = {
{ "rhadd" , {1}, {E_ANY,E_COPY}},
{ "rint" , {1}, {E_ANY}},
{ "rootn" , {1}, {E_ANY,E_SETBASE_I32}},
+{ "__rootn_fast" , {1}, {E_ANY,E_SETBASE_I32}},
{ "rotate" , {1}, {E_ANY,E_COPY}},
{ "round" , {1}, {E_ANY}},
{ "rsqrt" , {1}, {E_ANY}},
@@ -1079,6 +1083,21 @@ Function *AMDGPULibFunc::getFunction(Module *M, const AMDGPULibFunc &fInfo) {
if (!fInfo.isCompatibleSignature(*M, F->getFunctionType()))
return nullptr;
+ switch (fInfo.getId()) {
+ case AMDGPULibFunc::EI_POW_FAST:
+ case AMDGPULibFunc::EI_POWR_FAST:
+ case AMDGPULibFunc::EI_POWN_FAST:
+ case AMDGPULibFunc::EI_ROOTN_FAST:
+ // TODO: Remove this. This is not a real module flag used anywhere. This is
+ // a bringup hack so this transform is testable prior to the library
+ // functions existing.
+ if (!M->getModuleFlag("amdgpu-libcall-have-fast-pow"))
+ return nullptr;
+ break;
+ default:
+ break;
+ }
+
return F;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULibFunc.h b/llvm/lib/Target/AMDGPU/AMDGPULibFunc.h
index 580ef51b559d8..5a44cc4fc799e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULibFunc.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPULibFunc.h
@@ -150,8 +150,11 @@ class AMDGPULibFuncBase {
EI_NORMALIZE,
EI_POPCOUNT,
EI_POW,
+ EI_POW_FAST,
EI_POWN,
+ EI_POWN_FAST,
EI_POWR,
+ EI_POWR_FAST,
EI_PREFETCH,
EI_RADIANS,
EI_RECIP,
@@ -162,6 +165,7 @@ class AMDGPULibFuncBase {
EI_RHADD,
EI_RINT,
EI_ROOTN,
+ EI_ROOTN_FAST,
EI_ROTATE,
EI_ROUND,
EI_RSQRT,
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
index 5d08cef95810d..afe0971088bc1 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
@@ -33,51 +33,12 @@ define float @test_pow_fast_f32(float %x, float %y) {
; CHECK-LABEL: test_pow_fast_f32:
; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CHECK-NEXT: v_cmp_lg_f32_e32 vcc, 1.0, v0
-; CHECK-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
-; CHECK-NEXT: v_cmp_lg_f32_e32 vcc, 0, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
-; CHECK-NEXT: s_mov_b32 s4, 0x800000
-; CHECK-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; CHECK-NEXT: v_ldexp_f32 v2, |v0|, v2
-; CHECK-NEXT: v_log_f32_e32 v2, v2
-; CHECK-NEXT: v_mov_b32_e32 v3, 0x42000000
-; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; CHECK-NEXT: s_mov_b32 s4, 0xc2fc0000
-; CHECK-NEXT: v_sub_f32_e32 v2, v2, v3
-; CHECK-NEXT: v_mul_f32_e32 v3, v1, v2
-; CHECK-NEXT: v_mov_b32_e32 v4, 0x42800000
-; CHECK-NEXT: v_cmp_gt_f32_e32 vcc, s4, v3
-; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
-; CHECK-NEXT: v_fma_f32 v2, v1, v2, v3
-; CHECK-NEXT: v_exp_f32_e32 v2, v2
-; CHECK-NEXT: v_not_b32_e32 v3, 63
-; CHECK-NEXT: v_cndmask_b32_e32 v3, 0, v3, vcc
-; CHECK-NEXT: v_mul_f32_e32 v4, 0.5, v1
-; CHECK-NEXT: v_ldexp_f32 v2, v2, v3
-; CHECK-NEXT: v_trunc_f32_e32 v3, v1
-; CHECK-NEXT: v_trunc_f32_e32 v5, v4
-; CHECK-NEXT: v_cmp_eq_f32_e32 vcc, v3, v1
-; CHECK-NEXT: v_cmp_lg_f32_e64 s[4:5], v5, v4
-; CHECK-NEXT: s_and_b64 vcc, vcc, s[4:5]
-; CHECK-NEXT: v_cndmask_b32_e32 v4, 1.0, v0, vcc
-; CHECK-NEXT: s_brev_b32 s8, -2
-; CHECK-NEXT: v_cmp_lg_f32_e64 s[4:5], v3, v1
-; CHECK-NEXT: v_cmp_gt_f32_e64 s[6:7], 0, v0
-; CHECK-NEXT: v_bfi_b32 v2, s8, v2, v4
-; CHECK-NEXT: v_mov_b32_e32 v3, 0x7fc00000
-; CHECK-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5]
-; CHECK-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[4:5]
-; CHECK-NEXT: v_cmp_eq_f32_e64 s[4:5], 0, v0
-; CHECK-NEXT: v_cmp_gt_f32_e64 s[6:7], 0, v1
-; CHECK-NEXT: v_mov_b32_e32 v1, 0x7f800000
-; CHECK-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7]
-; CHECK-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[6:7]
-; CHECK-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
-; CHECK-NEXT: v_bfi_b32 v0, s8, v1, v0
-; CHECK-NEXT: v_cndmask_b32_e64 v0, v2, v0, s[4:5]
-; CHECK-NEXT: s_setpc_b64 s[30:31]
+; CHECK-NEXT: s_getpc_b64 s[16:17]
+; CHECK-NEXT: s_add_u32 s16, s16, _Z10__pow_fastff at gotpcrel32@lo+4
+; CHECK-NEXT: s_addc_u32 s17, s17, _Z10__pow_fastff at gotpcrel32@hi+12
+; CHECK-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
+; CHECK-NEXT: s_waitcnt lgkmcnt(0)
+; CHECK-NEXT: s_setpc_b64 s[16:17]
%pow = tail call fast float @_Z3powff(float %x, float %y)
ret float %pow
}
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-fast.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-fast.ll
new file mode 100644
index 0000000000000..961412ae45d2c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-fast.ll
@@ -0,0 +1,658 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink %s | FileCheck %s
+
+define float @test_pow_afn_f32(float %x, float %y) #0 {
+; CHECK-LABEL: define float @test_pow_afn_f32(
+; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z10__pow_fastff(float [[X]], float [[Y]])
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call afn float @_Z3powff(float %x, float %y)
+ ret float %call
+}
+
+declare float @_Z3powff(float, float) #1
+
+define <2 x float> @test_pow_afn_v2f32(<2 x float> %x, <2 x float> %y) #0 {
+; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32(
+; CHECK-SAME: <2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y)
+ ret <2 x float> %call
+}
+
+declare <2 x float> @_Z3powDv2_fS_(<2 x float>, <2 x float>) #1
+
+define <3 x float> @test_pow_afn_v3f32(<3 x float> %x, <3 x float> %y) #0 {
+; CHECK-LABEL: define <3 x float> @test_pow_afn_v3f32(
+; CHECK-SAME: <3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <3 x float> @_Z10__pow_fastDv3_fS_(<3 x float> [[X]], <3 x float> [[Y]])
+; CHECK-NEXT: ret <3 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <3 x float> @_Z3powDv3_fS_(<3 x float> %x, <3 x float> %y)
+ ret <3 x float> %call
+}
+
+declare <3 x float> @_Z3powDv3_fS_(<3 x float>, <3 x float>) #1
+
+define <4 x float> @test_pow_afn_v4f32(<4 x float> %x, <4 x float> %y) #0 {
+; CHECK-LABEL: define <4 x float> @test_pow_afn_v4f32(
+; CHECK-SAME: <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <4 x float> @_Z10__pow_fastDv4_fS_(<4 x float> [[X]], <4 x float> [[Y]])
+; CHECK-NEXT: ret <4 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <4 x float> @_Z3powDv4_fS_(<4 x float> %x, <4 x float> %y)
+ ret <4 x float> %call
+}
+
+declare <4 x float> @_Z3powDv4_fS_(<4 x float>, <4 x float>) #1
+
+define <8 x float> @test_pow_afn_v8f32(<8 x float> %x, <8 x float> %y) #0 {
+; CHECK-LABEL: define <8 x float> @test_pow_afn_v8f32(
+; CHECK-SAME: <8 x float> [[X:%.*]], <8 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <8 x float> @_Z10__pow_fastDv8_fS_(<8 x float> [[X]], <8 x float> [[Y]])
+; CHECK-NEXT: ret <8 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <8 x float> @_Z3powDv8_fS_(<8 x float> %x, <8 x float> %y)
+ ret <8 x float> %call
+}
+
+declare <8 x float> @_Z3powDv8_fS_(<8 x float>, <8 x float>) #1
+
+define <16 x float> @test_pow_afn_v16f32(<16 x float> %x, <16 x float> %y) #0 {
+; CHECK-LABEL: define <16 x float> @test_pow_afn_v16f32(
+; CHECK-SAME: <16 x float> [[X:%.*]], <16 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <16 x float> @_Z10__pow_fastDv16_fS_(<16 x float> [[X]], <16 x float> [[Y]])
+; CHECK-NEXT: ret <16 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <16 x float> @_Z3powDv16_fS_(<16 x float> %x, <16 x float> %y)
+ ret <16 x float> %call
+}
+
+declare <16 x float> @_Z3powDv16_fS_(<16 x float>, <16 x float>) #1
+
+
+define float @test_pow_afn_f32__known_positive_x(float nofpclass(ninf nnorm nsub nzero) %x, float %y) #0 {
+; CHECK-LABEL: define float @test_pow_afn_f32__known_positive_x(
+; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[X:%.*]], float [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float [[Y]])
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call afn float @_Z3powff(float %x, float %y)
+ ret float %call
+}
+
+define float @test_pow_afn_f32__known_positive_x__known_integral_y(float nofpclass(ninf nnorm nsub nzero) %x, i32 %y.int) #0 {
+; CHECK-LABEL: define float @test_pow_afn_f32__known_positive_x__known_integral_y(
+; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[X:%.*]], i32 [[Y_INT:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[Y:%.*]] = sitofp i32 [[Y_INT]] to float
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float [[Y]])
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %y = sitofp i32 %y.int to float
+ %call = tail call afn float @_Z3powff(float %x, float %y)
+ ret float %call
+}
+
+define <2 x float> @test_pow_afn_v2f32__known_positive_x(<2 x float> nofpclass(ninf nnorm nsub nzero) %x, <2 x float> %y) #0 {
+; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32__known_positive_x(
+; CHECK-SAME: <2 x float> nofpclass(ninf nzero nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y)
+ ret <2 x float> %call
+}
+
+define float @test_pow_afn_f32__known_integral_y(float %x, i32 %y.int) #0 {
+; CHECK-LABEL: define float @test_pow_afn_f32__known_integral_y(
+; CHECK-SAME: float [[X:%.*]], i32 [[Y_INT:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[Y:%.*]] = sitofp i32 [[Y_INT]] to float
+; CHECK-NEXT: [[TMP0:%.*]] = fptosi float [[Y]] to i32
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 [[TMP0]])
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %y = sitofp i32 %y.int to float
+ %call = tail call afn float @_Z3powff(float %x, float %y)
+ ret float %call
+}
+
+define <2 x float> @test_pow_afn_v2f32__known_integral_y(<2 x float> %x, <2 x i32> %y.int) #0 {
+; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32__known_integral_y(
+; CHECK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y_INT:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[Y:%.*]] = sitofp <2 x i32> [[Y_INT]] to <2 x float>
+; CHECK-NEXT: [[TMP0:%.*]] = fptosi <2 x float> [[Y]] to <2 x i32>
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[TMP0]])
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %y = sitofp <2 x i32> %y.int to <2 x float>
+ %call = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y)
+ ret <2 x float> %call
+}
+
+define float @test_pow_afn_f32__0(float %x) #0 {
+; CHECK-LABEL: define float @test_pow_afn_f32__0(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret float 1.000000e+00
+;
+entry:
+ %call = tail call afn float @_Z3powff(float %x, float 0.0)
+ ret float %call
+}
+
+define float @test_pow_afn_f32__1(float %x) #0 {
+; CHECK-LABEL: define float @test_pow_afn_f32__1(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret float [[X]]
+;
+entry:
+ %call = tail call afn float @_Z3powff(float %x, float 1.0)
+ ret float %call
+}
+
+define float @test_pow_afn_f32__2(float %x) #0 {
+; CHECK-LABEL: define float @test_pow_afn_f32__2(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2:%.*]] = fmul afn float [[X]], [[X]]
+; CHECK-NEXT: ret float [[__POW2]]
+;
+entry:
+ %call = tail call afn float @_Z3powff(float %x, float 2.0)
+ ret float %call
+}
+
+define float @test_pow_afn_f32__3(float %x) #0 {
+; CHECK-LABEL: define float @test_pow_afn_f32__3(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 3)
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call afn float @_Z3powff(float %x, float 3.0)
+ ret float %call
+}
+
+define float @test_pow_afn_f32__8(float %x) #0 {
+; CHECK-LABEL: define float @test_pow_afn_f32__8(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 8)
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call afn float @_Z3powff(float %x, float 8.0)
+ ret float %call
+}
+
+define float @test_pow_afn_f32__neg1(float %x) #0 {
+; CHECK-LABEL: define float @test_pow_afn_f32__neg1(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv afn float 1.000000e+00, [[X]]
+; CHECK-NEXT: ret float [[__POWRECIP]]
+;
+entry:
+ %call = tail call afn float @_Z3powff(float %x, float -1.0)
+ ret float %call
+}
+
+define float @test_pow_afn_f32__half(float %x) #0 {
+; CHECK-LABEL: define float @test_pow_afn_f32__half(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2SQRT:%.*]] = call afn float @_Z4sqrtf(float [[X]])
+; CHECK-NEXT: ret float [[__POW2SQRT]]
+;
+entry:
+ %call = tail call afn float @_Z3powff(float %x, float 0.5)
+ ret float %call
+}
+
+define float @test_pow_afn_f32__neghalf(float %x) #0 {
+; CHECK-LABEL: define float @test_pow_afn_f32__neghalf(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2RSQRT:%.*]] = call afn float @_Z5rsqrtf(float [[X]])
+; CHECK-NEXT: ret float [[__POW2RSQRT]]
+;
+entry:
+ %call = tail call afn float @_Z3powff(float %x, float -0.5)
+ ret float %call
+}
+
+define <2 x float> @test_pow_afn_v2f32__0(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32__0(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret <2 x float> splat (float 1.000000e+00)
+;
+entry:
+ %call = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> zeroinitializer)
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_pow_afn_v2f32__1(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32__1(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret <2 x float> [[X]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> splat (float 1.0))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_pow_afn_v2f32__2(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32__2(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2:%.*]] = fmul afn <2 x float> [[X]], [[X]]
+; CHECK-NEXT: ret <2 x float> [[__POW2]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> splat (float 2.0))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_pow_afn_v2f32__3(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32__3(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 3))
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> splat (float 3.0))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_pow_afn_v2f32__8(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32__8(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 8))
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> splat (float 8.0))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_pow_afn_v2f32__neg1(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32__neg1(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv afn <2 x float> splat (float 1.000000e+00), [[X]]
+; CHECK-NEXT: ret <2 x float> [[__POWRECIP]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> splat (float -1.0))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_pow_afn_v2f32__half(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32__half(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2SQRT:%.*]] = call afn <2 x float> @_Z4sqrtDv2_f(<2 x float> [[X]])
+; CHECK-NEXT: ret <2 x float> [[__POW2SQRT]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> splat (float 0.5))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_pow_afn_v2f32__neghalf(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32__neghalf(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2RSQRT:%.*]] = call afn <2 x float> @_Z5rsqrtDv2_f(<2 x float> [[X]])
+; CHECK-NEXT: ret <2 x float> [[__POW2RSQRT]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> splat (float -0.5))
+ ret <2 x float> %call
+}
+
+define float @test__pow_fast_f32(float %x, float %y) #0 {
+; CHECK-LABEL: define float @test__pow_fast_f32(
+; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z10__pow_fastff(float [[X]], float [[Y]])
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call float @_Z10__pow_fastff(float %x, float %y)
+ ret float %call
+}
+
+declare float @_Z10__pow_fastff(float, float) #1
+
+define <2 x float> @test__pow_fast_v2f32(<2 x float> %x, <2 x float> %y) #0 {
+; CHECK-LABEL: define <2 x float> @test__pow_fast_v2f32(
+; CHECK-SAME: <2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> %x, <2 x float> %y)
+ ret <2 x float> %call
+}
+
+declare <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float>, <2 x float>) #1
+
+define <3 x float> @test__pow_fast_v3f32(<3 x float> %x, <3 x float> %y) #0 {
+; CHECK-LABEL: define <3 x float> @test__pow_fast_v3f32(
+; CHECK-SAME: <3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <3 x float> @_Z10__pow_fastDv3_fS_(<3 x float> [[X]], <3 x float> [[Y]])
+; CHECK-NEXT: ret <3 x float> [[CALL]]
+;
+entry:
+ %call = tail call <3 x float> @_Z10__pow_fastDv3_fS_(<3 x float> %x, <3 x float> %y)
+ ret <3 x float> %call
+}
+
+declare <3 x float> @_Z10__pow_fastDv3_fS_(<3 x float>, <3 x float>) #1
+
+define <4 x float> @test__pow_fast_v4f32(<4 x float> %x, <4 x float> %y) #0 {
+; CHECK-LABEL: define <4 x float> @test__pow_fast_v4f32(
+; CHECK-SAME: <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <4 x float> @_Z10__pow_fastDv4_fS_(<4 x float> [[X]], <4 x float> [[Y]])
+; CHECK-NEXT: ret <4 x float> [[CALL]]
+;
+entry:
+ %call = tail call <4 x float> @_Z10__pow_fastDv4_fS_(<4 x float> %x, <4 x float> %y)
+ ret <4 x float> %call
+}
+
+declare <4 x float> @_Z10__pow_fastDv4_fS_(<4 x float>, <4 x float>) #1
+
+define <8 x float> @test__pow_fast_v8f32(<8 x float> %x, <8 x float> %y) #0 {
+; CHECK-LABEL: define <8 x float> @test__pow_fast_v8f32(
+; CHECK-SAME: <8 x float> [[X:%.*]], <8 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <8 x float> @_Z10__pow_fastDv8_fS_(<8 x float> [[X]], <8 x float> [[Y]])
+; CHECK-NEXT: ret <8 x float> [[CALL]]
+;
+entry:
+ %call = tail call <8 x float> @_Z10__pow_fastDv8_fS_(<8 x float> %x, <8 x float> %y)
+ ret <8 x float> %call
+}
+
+declare <8 x float> @_Z10__pow_fastDv8_fS_(<8 x float>, <8 x float>) #1
+
+define <16 x float> @test__pow_fast_v16f32(<16 x float> %x, <16 x float> %y) #0 {
+; CHECK-LABEL: define <16 x float> @test__pow_fast_v16f32(
+; CHECK-SAME: <16 x float> [[X:%.*]], <16 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <16 x float> @_Z10__pow_fastDv16_fS_(<16 x float> [[X]], <16 x float> [[Y]])
+; CHECK-NEXT: ret <16 x float> [[CALL]]
+;
+entry:
+ %call = tail call <16 x float> @_Z10__pow_fastDv16_fS_(<16 x float> %x, <16 x float> %y)
+ ret <16 x float> %call
+}
+
+declare <16 x float> @_Z10__pow_fastDv16_fS_(<16 x float>, <16 x float>) #1
+
+define float @test__pow_fast_f32__known_positive_x(float nofpclass(ninf nnorm nsub nzero) %x, float %y) #0 {
+; CHECK-LABEL: define float @test__pow_fast_f32__known_positive_x(
+; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[X:%.*]], float [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z11__powr_fastff(float [[X]], float [[Y]])
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call float @_Z10__pow_fastff(float %x, float %y)
+ ret float %call
+}
+
+define float @test__pow_fast_f32__known_positive_x_preserve_flags(float nofpclass(ninf nnorm nsub nzero) %x, float %y) #0 {
+; CHECK-LABEL: define float @test__pow_fast_f32__known_positive_x_preserve_flags(
+; CHECK-SAME: float nofpclass(ninf nzero nsub nnorm) [[X:%.*]], float [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call nsz contract nofpclass(snan) float @_Z11__powr_fastff(float [[X]], float [[Y]]), !keep.md [[META0:![0-9]+]]
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call contract nsz nofpclass(snan) float @_Z10__pow_fastff(float %x, float %y), !keep.md !{}
+ ret float %call
+}
+
+define <2 x float> @test__pow_fast_v2f32__known_positive_x(<2 x float> nofpclass(ninf nnorm nsub nzero) %x, <2 x float> %y) #0 {
+; CHECK-LABEL: define <2 x float> @test__pow_fast_v2f32__known_positive_x(
+; CHECK-SAME: <2 x float> nofpclass(ninf nzero nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> %x, <2 x float> %y)
+ ret <2 x float> %call
+}
+
+define float @test___pow_fast_f32__known_integral_y(float %x, i32 %y.int) #0 {
+; CHECK-LABEL: define float @test___pow_fast_f32__known_integral_y(
+; CHECK-SAME: float [[X:%.*]], i32 [[Y_INT:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[Y:%.*]] = sitofp i32 [[Y_INT]] to float
+; CHECK-NEXT: [[TMP0:%.*]] = fptosi float [[Y]] to i32
+; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z11__pown_fastfi(float [[X]], i32 [[TMP0]])
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %y = sitofp i32 %y.int to float
+ %call = tail call float @_Z10__pow_fastff(float %x, float %y)
+ ret float %call
+}
+
+define float @test__pow_fast_f32__0(float %x) #0 {
+; CHECK-LABEL: define float @test__pow_fast_f32__0(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret float 1.000000e+00
+;
+entry:
+ %call = tail call float @_Z10__pow_fastff(float %x, float 0.0)
+ ret float %call
+}
+
+define float @test__pow_fast_afn_f32__0(float %x) #0 {
+; CHECK-LABEL: define float @test__pow_fast_afn_f32__0(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret float 1.000000e+00
+;
+entry:
+ %call = tail call afn float @_Z10__pow_fastff(float %x, float 0.0)
+ ret float %call
+}
+
+define float @test__pow_fast_f32__2(float %x) #0 {
+; CHECK-LABEL: define float @test__pow_fast_f32__2(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2:%.*]] = fmul float [[X]], [[X]]
+; CHECK-NEXT: ret float [[__POW2]]
+;
+entry:
+ %call = tail call float @_Z10__pow_fastff(float %x, float 2.0)
+ ret float %call
+}
+
+define float @test__pow_fast_afn_f32__2(float %x) #0 {
+; CHECK-LABEL: define float @test__pow_fast_afn_f32__2(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2:%.*]] = fmul afn float [[X]], [[X]]
+; CHECK-NEXT: ret float [[__POW2]]
+;
+entry:
+ %call = tail call afn float @_Z10__pow_fastff(float %x, float 2.0)
+ ret float %call
+}
+
+define float @test__pow_fast_f32__half(float %x) #0 {
+; CHECK-LABEL: define float @test__pow_fast_f32__half(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2SQRT:%.*]] = call float @_Z4sqrtf(float [[X]])
+; CHECK-NEXT: ret float [[__POW2SQRT]]
+;
+entry:
+ %call = tail call float @_Z10__pow_fastff(float %x, float 0.5)
+ ret float %call
+}
+
+define float @test__pow_fast_afn_f32__half(float %x) #0 {
+; CHECK-LABEL: define float @test__pow_fast_afn_f32__half(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2SQRT:%.*]] = call afn float @_Z4sqrtf(float [[X]])
+; CHECK-NEXT: ret float [[__POW2SQRT]]
+;
+entry:
+ %call = tail call afn float @_Z10__pow_fastff(float %x, float 0.5)
+ ret float %call
+}
+
+define float @test__pow_fast_f32__neghalf(float %x) #0 {
+; CHECK-LABEL: define float @test__pow_fast_f32__neghalf(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2RSQRT:%.*]] = call float @_Z5rsqrtf(float [[X]])
+; CHECK-NEXT: ret float [[__POW2RSQRT]]
+;
+entry:
+ %call = tail call float @_Z10__pow_fastff(float %x, float -0.5)
+ ret float %call
+}
+
+define float @test__pow_fast_afn_f32__neghalf(float %x) #0 {
+; CHECK-LABEL: define float @test__pow_fast_afn_f32__neghalf(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2RSQRT:%.*]] = call afn float @_Z5rsqrtf(float [[X]])
+; CHECK-NEXT: ret float [[__POW2RSQRT]]
+;
+entry:
+ %call = tail call afn float @_Z10__pow_fastff(float %x, float -0.5)
+ ret float %call
+}
+
+define <2 x float> @test__pow_fast_v2f32__neghalf(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test__pow_fast_v2f32__neghalf(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2RSQRT:%.*]] = call <2 x float> @_Z5rsqrtDv2_f(<2 x float> [[X]])
+; CHECK-NEXT: ret <2 x float> [[__POW2RSQRT]]
+;
+entry:
+ %call = tail call <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> %x, <2 x float> splat (float -0.5))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test__pow_fast_afn_v2f32__neghalf(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test__pow_fast_afn_v2f32__neghalf(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2RSQRT:%.*]] = call afn <2 x float> @_Z5rsqrtDv2_f(<2 x float> [[X]])
+; CHECK-NEXT: ret <2 x float> [[__POW2RSQRT]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> %x, <2 x float> splat (float -0.5))
+ ret <2 x float> %call
+}
+
+define double @test_pow_afn_f64(double %x, double %y) #0 {
+; CHECK-LABEL: define double @test_pow_afn_f64(
+; CHECK-SAME: double [[X:%.*]], double [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn double @_Z3powdd(double [[X]], double [[Y]])
+; CHECK-NEXT: ret double [[CALL]]
+;
+entry:
+ %call = tail call afn double @_Z3powdd(double %x, double %y)
+ ret double %call
+}
+
+declare double @_Z3powdd(double, double) #0
+
+define <2 x double> @test_pow_afn_v2f64(<2 x double> %x, <2 x double> %y) #0 {
+; CHECK-LABEL: define <2 x double> @test_pow_afn_v2f64(
+; CHECK-SAME: <2 x double> [[X:%.*]], <2 x double> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x double> @_Z3powDv2_dS_(<2 x double> [[X]], <2 x double> [[Y]])
+; CHECK-NEXT: ret <2 x double> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x double> @_Z3powDv2_dS_(<2 x double> %x, <2 x double> %y)
+ ret <2 x double> %call
+}
+
+declare <2 x double> @_Z3powDv2_dS_(<2 x double>, <2 x double>) #0
+
+define half @test_pow_afn_f16(half %x, half %y) #0 {
+; CHECK-LABEL: define half @test_pow_afn_f16(
+; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn half @_Z3powDhDh(half [[X]], half [[Y]])
+; CHECK-NEXT: ret half [[CALL]]
+;
+entry:
+ %call = tail call afn half @_Z3powDhDh(half %x, half %y)
+ ret half %call
+}
+
+declare half @_Z3powDhDh(half, half) #0
+
+define <2 x half> @test_pow_afn_v2f16(<2 x half> %x, <2 x half> %y) #0 {
+; CHECK-LABEL: define <2 x half> @test_pow_afn_v2f16(
+; CHECK-SAME: <2 x half> [[X:%.*]], <2 x half> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x half> @_Z3powDv2_DhS_(<2 x half> [[X]], <2 x half> [[Y]]) #[[ATTR3:[0-9]+]]
+; CHECK-NEXT: ret <2 x half> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x half> @_Z3powDv2_DhS_(<2 x half> %x, <2 x half> %y)
+ ret <2 x half> %call
+}
+
+declare <2 x half> @_Z3powDv2_DhS_(<2 x half>, <2 x half>) #3
+
+attributes #0 = { mustprogress nofree norecurse nounwind willreturn memory(none) }
+attributes #1 = { mustprogress nofree nounwind willreturn memory(none) }
+;.
+; CHECK: [[META0]] = !{}
+;.
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
index 69ffaab43d8d3..b2d5bb2faeca7 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
-; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink %s | FileCheck %s
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink %s | FileCheck -check-prefixes=CHECK,PRELINK %s
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine %s | FileCheck -check-prefixes=CHECK,NOPRELINK %s
declare float @_Z3powff(float, float)
declare <2 x float> @_Z3powDv2_fS_(<2 x float>, <2 x float>)
@@ -29,568 +30,628 @@ declare float @llvm.round.f32(float)
declare float @llvm.roundeven.f32(float)
define float @test_pow_fast_f32(float %x, float %y) {
-; CHECK-LABEL: define float @test_pow_fast_f32
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast oeq float [[X]], 1.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select fast i1 [[TMP1]], float 1.000000e+00, float [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp fast oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP4:%.*]] = select fast i1 [[TMP3]], float 1.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = call fast float @llvm.log2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fmul fast float [[TMP2]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.exp2.f32(float [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp fast oeq float [[TMP9]], [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP2]], 5.000000e-01
-; CHECK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp fast une float [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select fast i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
-; CHECK-NEXT: [[TMP16:%.*]] = call fast float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
-; CHECK-NEXT: [[TMP17:%.*]] = call fast float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp fast une float [[TMP17]], [[TMP2]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp fast olt float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; CHECK-NEXT: [[TMP21:%.*]] = select fast i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
-; CHECK-NEXT: [[TMP22:%.*]] = fcmp fast oeq float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp fast olt float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP24:%.*]] = xor i1 [[TMP22]], [[TMP23]]
-; CHECK-NEXT: [[TMP25:%.*]] = select fast i1 [[TMP24]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP26:%.*]] = select fast i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
-; CHECK-NEXT: [[TMP27:%.*]] = call fast float @llvm.copysign.f32(float [[TMP25]], float [[TMP26]])
-; CHECK-NEXT: [[TMP28:%.*]] = select fast i1 [[TMP22]], float [[TMP27]], float [[TMP21]]
-; CHECK-NEXT: ret float [[TMP28]]
+; PRELINK-LABEL: define float @test_pow_fast_f32
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call fast float @_Z10__pow_fastff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_fast_f32
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp fast oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select fast i1 [[TMP1]], float 1.000000e+00, float [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp fast oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select fast i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call fast float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call fast float @llvm.log2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul fast float [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call fast float @llvm.exp2.f32(float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call fast float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp fast oeq float [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul fast float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call fast float @llvm.trunc.f32(float [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp fast une float [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select fast i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call fast float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call fast float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp fast une float [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp fast olt float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select fast i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp fast oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp fast olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP24:%.*]] = xor i1 [[TMP22]], [[TMP23]]
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select fast i1 [[TMP24]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select fast i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP27:%.*]] = call fast float @llvm.copysign.f32(float [[TMP25]], float [[TMP26]])
+; NOPRELINK-NEXT: [[TMP28:%.*]] = select fast i1 [[TMP22]], float [[TMP27]], float [[TMP21]]
+; NOPRELINK-NEXT: ret float [[TMP28]]
;
%pow = tail call fast float @_Z3powff(float %x, float %y)
ret float %pow
}
define <2 x float> @test_pow_fast_v2f32(<2 x float> %x, <2 x float> %y) {
-; CHECK-LABEL: define <2 x float> @test_pow_fast_v2f32
-; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp fast oeq <2 x float> [[X]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = select fast <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp fast oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = select fast <2 x i1> [[TMP3]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call fast <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = call fast <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fmul fast <2 x float> [[TMP2]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = call fast <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call fast <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp fast oeq <2 x float> [[TMP9]], [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = fmul fast <2 x float> [[TMP2]], splat (float 5.000000e-01)
-; CHECK-NEXT: [[TMP12:%.*]] = call fast <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP11]])
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp fast une <2 x float> [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select fast <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP16:%.*]] = call fast <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP8]], <2 x float> [[TMP15]])
-; CHECK-NEXT: [[TMP17:%.*]] = call fast <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp fast une <2 x float> [[TMP17]], [[TMP2]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp fast olt <2 x float> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[TMP18]]
-; CHECK-NEXT: [[TMP21:%.*]] = select fast <2 x i1> [[TMP20]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP16]]
-; CHECK-NEXT: [[TMP22:%.*]] = fcmp fast oeq <2 x float> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp fast olt <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP24:%.*]] = xor <2 x i1> [[TMP22]], [[TMP23]]
-; CHECK-NEXT: [[TMP25:%.*]] = select fast <2 x i1> [[TMP24]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP26:%.*]] = select fast <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
-; CHECK-NEXT: [[TMP27:%.*]] = call fast <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP25]], <2 x float> [[TMP26]])
-; CHECK-NEXT: [[TMP28:%.*]] = select fast <2 x i1> [[TMP22]], <2 x float> [[TMP27]], <2 x float> [[TMP21]]
-; CHECK-NEXT: ret <2 x float> [[TMP28]]
+; PRELINK-LABEL: define <2 x float> @test_pow_fast_v2f32
+; PRELINK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call fast <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_fast_v2f32
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp fast oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select fast <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp fast oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select fast <2 x i1> [[TMP3]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call fast <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call fast <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul fast <2 x float> [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call fast <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call fast <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp fast oeq <2 x float> [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul fast <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call fast <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp fast une <2 x float> [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select fast <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call fast <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP8]], <2 x float> [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call fast <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp fast une <2 x float> [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp fast olt <2 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select fast <2 x i1> [[TMP20]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp fast oeq <2 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp fast olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP24:%.*]] = xor <2 x i1> [[TMP22]], [[TMP23]]
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select fast <2 x i1> [[TMP24]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select fast <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP27:%.*]] = call fast <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP25]], <2 x float> [[TMP26]])
+; NOPRELINK-NEXT: [[TMP28:%.*]] = select fast <2 x i1> [[TMP22]], <2 x float> [[TMP27]], <2 x float> [[TMP21]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP28]]
;
%pow = tail call fast <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y)
ret <2 x float> %pow
}
define float @test_pow_afn_f32_nnan(float %x, float %y) {
-; CHECK-LABEL: define float @test_pow_afn_f32_nnan
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp nnan afn oeq float [[X]], 1.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select nnan afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP4:%.*]] = select nnan afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fmul nnan afn float [[TMP2]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[TMP9]], [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
-; CHECK-NEXT: [[TMP12:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP11]])
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une float [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
-; CHECK-NEXT: [[TMP16:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
-; CHECK-NEXT: [[TMP17:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[TMP17]], [[TMP2]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; CHECK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
-; CHECK-NEXT: [[TMP22:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP24:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp nnan afn une float [[TMP2]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP27:%.*]] = fcmp nnan afn oeq float [[TMP26]], 1.000000e+00
-; CHECK-NEXT: [[TMP28:%.*]] = fcmp nnan afn olt float [[TMP26]], 1.000000e+00
-; CHECK-NEXT: [[TMP29:%.*]] = xor i1 [[TMP28]], [[TMP25]]
-; CHECK-NEXT: [[TMP30:%.*]] = select nnan afn i1 [[TMP29]], float 0.000000e+00, float [[TMP24]]
-; CHECK-NEXT: [[TMP31:%.*]] = select nnan afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
-; CHECK-NEXT: [[TMP32:%.*]] = select nnan afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
-; CHECK-NEXT: [[TMP33:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq float [[TMP33]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP35:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
-; CHECK-NEXT: [[TMP37:%.*]] = fcmp nnan afn olt float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
-; CHECK-NEXT: [[TMP39:%.*]] = select nnan afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP40:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
-; CHECK-NEXT: [[TMP41:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
-; CHECK-NEXT: [[TMP42:%.*]] = select nnan afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
-; CHECK-NEXT: ret float [[TMP42]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_nnan
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan afn float @_Z10__pow_fastff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_nnan
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select nnan afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul nnan afn float [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une float [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp nnan afn une float [[TMP2]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = fcmp nnan afn oeq float [[TMP26]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp nnan afn olt float [[TMP26]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP29:%.*]] = xor i1 [[TMP28]], [[TMP25]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = select nnan afn i1 [[TMP29]], float 0.000000e+00, float [[TMP24]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select nnan afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = select nnan afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
+; NOPRELINK-NEXT: [[TMP33:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq float [[TMP33]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
+; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp nnan afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select nnan afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP40:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP41:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
+; NOPRELINK-NEXT: [[TMP42:%.*]] = select nnan afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
+; NOPRELINK-NEXT: ret float [[TMP42]]
;
%pow = tail call afn nnan float @_Z3powff(float %x, float %y)
ret float %pow
}
define float @test_pow_afn_f32_nnan_ninf(float %x, float %y) {
-; CHECK-LABEL: define float @test_pow_afn_f32_nnan_ninf
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp nnan ninf afn oeq float [[X]], 1.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select nnan ninf afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp nnan ninf afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP4:%.*]] = select nnan ninf afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fmul nnan ninf afn float [[TMP2]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call nnan ninf afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp nnan ninf afn oeq float [[TMP9]], [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = fmul nnan ninf afn float [[TMP2]], 5.000000e-01
-; CHECK-NEXT: [[TMP12:%.*]] = call nnan ninf afn float @llvm.trunc.f32(float [[TMP11]])
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp nnan ninf afn une float [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select nnan ninf afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
-; CHECK-NEXT: [[TMP16:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
-; CHECK-NEXT: [[TMP17:%.*]] = call nnan ninf afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp nnan ninf afn une float [[TMP17]], [[TMP2]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp nnan ninf afn olt float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; CHECK-NEXT: [[TMP21:%.*]] = select nnan ninf afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
-; CHECK-NEXT: [[TMP22:%.*]] = fcmp nnan ninf afn oeq float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp nnan ninf afn olt float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP24:%.*]] = xor i1 [[TMP22]], [[TMP23]]
-; CHECK-NEXT: [[TMP25:%.*]] = select nnan ninf afn i1 [[TMP24]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP26:%.*]] = select nnan ninf afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
-; CHECK-NEXT: [[TMP27:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP25]], float [[TMP26]])
-; CHECK-NEXT: [[TMP28:%.*]] = select nnan ninf afn i1 [[TMP22]], float [[TMP27]], float [[TMP21]]
-; CHECK-NEXT: ret float [[TMP28]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_nnan_ninf
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan ninf afn float @_Z10__pow_fastff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_nnan_ninf
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan ninf afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan ninf afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp nnan ninf afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select nnan ninf afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul nnan ninf afn float [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call nnan ninf afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan ninf afn oeq float [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan ninf afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call nnan ninf afn float @llvm.trunc.f32(float [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp nnan ninf afn une float [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan ninf afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call nnan ninf afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan ninf afn une float [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan ninf afn olt float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan ninf afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp nnan ninf afn oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan ninf afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP24:%.*]] = xor i1 [[TMP22]], [[TMP23]]
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select nnan ninf afn i1 [[TMP24]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select nnan ninf afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP27:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP25]], float [[TMP26]])
+; NOPRELINK-NEXT: [[TMP28:%.*]] = select nnan ninf afn i1 [[TMP22]], float [[TMP27]], float [[TMP21]]
+; NOPRELINK-NEXT: ret float [[TMP28]]
;
%pow = tail call afn nnan ninf float @_Z3powff(float %x, float %y)
ret float %pow
}
define <2 x float> @test_pow_afn_v2f32_nnan(<2 x float> %x, <2 x float> %y) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_nnan
-; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp nnan afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = select nnan afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = select nnan afn <2 x i1> [[TMP3]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = call nnan afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fmul nnan afn <2 x float> [[TMP2]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call nnan afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP9]], [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
-; CHECK-NEXT: [[TMP12:%.*]] = call nnan afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP11]])
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une <2 x float> [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select nnan afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP16:%.*]] = call nnan afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP8]], <2 x float> [[TMP15]])
-; CHECK-NEXT: [[TMP17:%.*]] = call nnan afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une <2 x float> [[TMP17]], [[TMP2]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt <2 x float> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[TMP18]]
-; CHECK-NEXT: [[TMP21:%.*]] = select nnan afn <2 x i1> [[TMP20]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP16]]
-; CHECK-NEXT: [[TMP22:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP22]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP24:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp nnan afn une <2 x float> [[TMP2]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP27:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP26]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP28:%.*]] = fcmp nnan afn olt <2 x float> [[TMP26]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP29:%.*]] = xor <2 x i1> [[TMP28]], [[TMP25]]
-; CHECK-NEXT: [[TMP30:%.*]] = select nnan afn <2 x i1> [[TMP29]], <2 x float> zeroinitializer, <2 x float> [[TMP24]]
-; CHECK-NEXT: [[TMP31:%.*]] = select nnan afn <2 x i1> [[TMP27]], <2 x float> splat (float 1.000000e+00), <2 x float> [[TMP30]]
-; CHECK-NEXT: [[TMP32:%.*]] = select nnan afn <2 x i1> [[TMP23]], <2 x float> [[TMP31]], <2 x float> [[TMP21]]
-; CHECK-NEXT: [[TMP33:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP33]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP35:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP36:%.*]] = or <2 x i1> [[TMP34]], [[TMP35]]
-; CHECK-NEXT: [[TMP37:%.*]] = fcmp nnan afn olt <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP38:%.*]] = xor <2 x i1> [[TMP35]], [[TMP37]]
-; CHECK-NEXT: [[TMP39:%.*]] = select nnan afn <2 x i1> [[TMP38]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP40:%.*]] = select nnan afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
-; CHECK-NEXT: [[TMP41:%.*]] = call nnan afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP39]], <2 x float> [[TMP40]])
-; CHECK-NEXT: [[TMP42:%.*]] = select nnan afn <2 x i1> [[TMP36]], <2 x float> [[TMP41]], <2 x float> [[TMP32]]
-; CHECK-NEXT: ret <2 x float> [[TMP42]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_nnan
+; PRELINK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan afn <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_nnan
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select nnan afn <2 x i1> [[TMP3]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul nnan afn <2 x float> [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call nnan afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call nnan afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une <2 x float> [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP8]], <2 x float> [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call nnan afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une <2 x float> [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt <2 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn <2 x i1> [[TMP20]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP22]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp nnan afn une <2 x float> [[TMP2]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP26]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp nnan afn olt <2 x float> [[TMP26]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP29:%.*]] = xor <2 x i1> [[TMP28]], [[TMP25]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = select nnan afn <2 x i1> [[TMP29]], <2 x float> zeroinitializer, <2 x float> [[TMP24]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select nnan afn <2 x i1> [[TMP27]], <2 x float> splat (float 1.000000e+00), <2 x float> [[TMP30]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = select nnan afn <2 x i1> [[TMP23]], <2 x float> [[TMP31]], <2 x float> [[TMP21]]
+; NOPRELINK-NEXT: [[TMP33:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP33]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP36:%.*]] = or <2 x i1> [[TMP34]], [[TMP35]]
+; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp nnan afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP38:%.*]] = xor <2 x i1> [[TMP35]], [[TMP37]]
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select nnan afn <2 x i1> [[TMP38]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP40:%.*]] = select nnan afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP41:%.*]] = call nnan afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP39]], <2 x float> [[TMP40]])
+; NOPRELINK-NEXT: [[TMP42:%.*]] = select nnan afn <2 x i1> [[TMP36]], <2 x float> [[TMP41]], <2 x float> [[TMP32]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP42]]
;
%pow = tail call afn nnan <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_nnan_ninf(<2 x float> %x, <2 x float> %y) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_nnan_ninf
-; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = select nnan ninf afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = select nnan ninf afn <2 x i1> [[TMP3]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[TMP9]], [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
-; CHECK-NEXT: [[TMP12:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP11]])
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp nnan ninf afn une <2 x float> [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select nnan ninf afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP16:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP8]], <2 x float> [[TMP15]])
-; CHECK-NEXT: [[TMP17:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp nnan ninf afn une <2 x float> [[TMP17]], [[TMP2]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp nnan ninf afn olt <2 x float> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[TMP18]]
-; CHECK-NEXT: [[TMP21:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP16]]
-; CHECK-NEXT: [[TMP22:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp nnan ninf afn olt <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP24:%.*]] = xor <2 x i1> [[TMP22]], [[TMP23]]
-; CHECK-NEXT: [[TMP25:%.*]] = select nnan ninf afn <2 x i1> [[TMP24]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP26:%.*]] = select nnan ninf afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
-; CHECK-NEXT: [[TMP27:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP25]], <2 x float> [[TMP26]])
-; CHECK-NEXT: [[TMP28:%.*]] = select nnan ninf afn <2 x i1> [[TMP22]], <2 x float> [[TMP27]], <2 x float> [[TMP21]]
-; CHECK-NEXT: ret <2 x float> [[TMP28]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_nnan_ninf
+; PRELINK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan ninf afn <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_nnan_ninf
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan ninf afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select nnan ninf afn <2 x i1> [[TMP3]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp nnan ninf afn une <2 x float> [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan ninf afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP8]], <2 x float> [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan ninf afn une <2 x float> [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan ninf afn olt <2 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan ninf afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP24:%.*]] = xor <2 x i1> [[TMP22]], [[TMP23]]
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select nnan ninf afn <2 x i1> [[TMP24]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select nnan ninf afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP27:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP25]], <2 x float> [[TMP26]])
+; NOPRELINK-NEXT: [[TMP28:%.*]] = select nnan ninf afn <2 x i1> [[TMP22]], <2 x float> [[TMP27]], <2 x float> [[TMP21]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP28]]
;
%pow = tail call afn nnan ninf <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y)
ret <2 x float> %pow
}
define float @test_pow_afn_f32(float %x, float %y) {
-; CHECK-LABEL: define float @test_pow_afn_f32
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP4:%.*]] = select afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.log2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fmul afn float [[TMP2]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = call afn float @llvm.exp2.f32(float [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = fmul afn float [[TMP2]], 5.000000e-01
-; CHECK-NEXT: [[TMP12:%.*]] = call afn float @llvm.trunc.f32(float [[TMP11]])
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp afn une float [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
-; CHECK-NEXT: [[TMP16:%.*]] = call afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
-; CHECK-NEXT: [[TMP17:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[TMP17]], [[TMP2]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp afn olt float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; CHECK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
-; CHECK-NEXT: [[TMP22:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP24:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp afn une float [[TMP2]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP27:%.*]] = fcmp afn oeq float [[TMP26]], 1.000000e+00
-; CHECK-NEXT: [[TMP28:%.*]] = fcmp afn olt float [[TMP26]], 1.000000e+00
-; CHECK-NEXT: [[TMP29:%.*]] = xor i1 [[TMP28]], [[TMP25]]
-; CHECK-NEXT: [[TMP30:%.*]] = select afn i1 [[TMP29]], float 0.000000e+00, float [[TMP24]]
-; CHECK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
-; CHECK-NEXT: [[TMP32:%.*]] = select afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
-; CHECK-NEXT: [[TMP33:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP34:%.*]] = fcmp afn oeq float [[TMP33]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP35:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
-; CHECK-NEXT: [[TMP37:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
-; CHECK-NEXT: [[TMP39:%.*]] = select afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP40:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
-; CHECK-NEXT: [[TMP41:%.*]] = call afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
-; CHECK-NEXT: [[TMP42:%.*]] = select afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
-; CHECK-NEXT: [[TMP43:%.*]] = fcmp afn uno float [[TMP4]], [[TMP2]]
-; CHECK-NEXT: [[TMP44:%.*]] = select afn i1 [[TMP43]], float 0x7FF8000000000000, float [[TMP42]]
-; CHECK-NEXT: ret float [[TMP44]]
+; PRELINK-LABEL: define float @test_pow_afn_f32
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z10__pow_fastff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.log2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul afn float [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn float @llvm.exp2.f32(float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call afn float @llvm.trunc.f32(float [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une float [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn une float [[TMP2]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = fcmp afn oeq float [[TMP26]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn olt float [[TMP26]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP29:%.*]] = xor i1 [[TMP28]], [[TMP25]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = select afn i1 [[TMP29]], float 0.000000e+00, float [[TMP24]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = select afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
+; NOPRELINK-NEXT: [[TMP33:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq float [[TMP33]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
+; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP40:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP41:%.*]] = call afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
+; NOPRELINK-NEXT: [[TMP42:%.*]] = select afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
+; NOPRELINK-NEXT: [[TMP43:%.*]] = fcmp afn uno float [[TMP4]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn i1 [[TMP43]], float 0x7FF8000000000000, float [[TMP42]]
+; NOPRELINK-NEXT: ret float [[TMP44]]
;
%pow = tail call afn float @_Z3powff(float %x, float %y)
ret float %pow
}
define <2 x float> @test_pow_afn_v2f32(<2 x float> %x, <2 x float> %y) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32
-; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = select afn <2 x i1> [[TMP3]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[TMP9]], [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = fmul afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
-; CHECK-NEXT: [[TMP12:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP11]])
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp afn une <2 x float> [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP16:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP8]], <2 x float> [[TMP15]])
-; CHECK-NEXT: [[TMP17:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp afn une <2 x float> [[TMP17]], [[TMP2]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp afn olt <2 x float> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[TMP18]]
-; CHECK-NEXT: [[TMP21:%.*]] = select afn <2 x i1> [[TMP20]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP16]]
-; CHECK-NEXT: [[TMP22:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <2 x float> [[TMP22]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP24:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp afn une <2 x float> [[TMP2]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP27:%.*]] = fcmp afn oeq <2 x float> [[TMP26]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP28:%.*]] = fcmp afn olt <2 x float> [[TMP26]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP29:%.*]] = xor <2 x i1> [[TMP28]], [[TMP25]]
-; CHECK-NEXT: [[TMP30:%.*]] = select afn <2 x i1> [[TMP29]], <2 x float> zeroinitializer, <2 x float> [[TMP24]]
-; CHECK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP27]], <2 x float> splat (float 1.000000e+00), <2 x float> [[TMP30]]
-; CHECK-NEXT: [[TMP32:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP31]], <2 x float> [[TMP21]]
-; CHECK-NEXT: [[TMP33:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <2 x float> [[TMP33]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP35:%.*]] = fcmp afn oeq <2 x float> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP36:%.*]] = or <2 x i1> [[TMP34]], [[TMP35]]
-; CHECK-NEXT: [[TMP37:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP38:%.*]] = xor <2 x i1> [[TMP35]], [[TMP37]]
-; CHECK-NEXT: [[TMP39:%.*]] = select afn <2 x i1> [[TMP38]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP40:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
-; CHECK-NEXT: [[TMP41:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP39]], <2 x float> [[TMP40]])
-; CHECK-NEXT: [[TMP42:%.*]] = select afn <2 x i1> [[TMP36]], <2 x float> [[TMP41]], <2 x float> [[TMP32]]
-; CHECK-NEXT: [[TMP43:%.*]] = fcmp afn uno <2 x float> [[TMP4]], [[TMP2]]
-; CHECK-NEXT: [[TMP44:%.*]] = select afn <2 x i1> [[TMP43]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP42]]
-; CHECK-NEXT: ret <2 x float> [[TMP44]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32
+; PRELINK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select afn <2 x i1> [[TMP3]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une <2 x float> [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP8]], <2 x float> [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une <2 x float> [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt <2 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <2 x i1> [[TMP20]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <2 x float> [[TMP22]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn une <2 x float> [[TMP2]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = fcmp afn oeq <2 x float> [[TMP26]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn olt <2 x float> [[TMP26]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP29:%.*]] = xor <2 x i1> [[TMP28]], [[TMP25]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = select afn <2 x i1> [[TMP29]], <2 x float> zeroinitializer, <2 x float> [[TMP24]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP27]], <2 x float> splat (float 1.000000e+00), <2 x float> [[TMP30]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP31]], <2 x float> [[TMP21]]
+; NOPRELINK-NEXT: [[TMP33:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <2 x float> [[TMP33]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp afn oeq <2 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP36:%.*]] = or <2 x i1> [[TMP34]], [[TMP35]]
+; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP38:%.*]] = xor <2 x i1> [[TMP35]], [[TMP37]]
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn <2 x i1> [[TMP38]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP40:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP41:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP39]], <2 x float> [[TMP40]])
+; NOPRELINK-NEXT: [[TMP42:%.*]] = select afn <2 x i1> [[TMP36]], <2 x float> [[TMP41]], <2 x float> [[TMP32]]
+; NOPRELINK-NEXT: [[TMP43:%.*]] = fcmp afn uno <2 x float> [[TMP4]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn <2 x i1> [[TMP43]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP42]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP44]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y)
ret <2 x float> %pow
}
define <3 x float> @test_pow_afn_v3f32(<3 x float> %x, <3 x float> %y) {
-; CHECK-LABEL: define <3 x float> @test_pow_afn_v3f32
-; CHECK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <3 x float> [[X]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <3 x i1> [[TMP1]], <3 x float> splat (float 1.000000e+00), <3 x float> [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = select afn <3 x i1> [[TMP3]], <3 x float> splat (float 1.000000e+00), <3 x float> [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <3 x float> @llvm.log2.v3f32(<3 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fmul afn <3 x float> [[TMP2]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = call afn <3 x float> @llvm.exp2.v3f32(<3 x float> [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call afn <3 x float> @llvm.trunc.v3f32(<3 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <3 x float> [[TMP9]], [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = fmul afn <3 x float> [[TMP2]], splat (float 5.000000e-01)
-; CHECK-NEXT: [[TMP12:%.*]] = call afn <3 x float> @llvm.trunc.v3f32(<3 x float> [[TMP11]])
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp afn une <3 x float> [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = and <3 x i1> [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select afn <3 x i1> [[TMP14]], <3 x float> [[TMP4]], <3 x float> splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP16:%.*]] = call afn <3 x float> @llvm.copysign.v3f32(<3 x float> [[TMP8]], <3 x float> [[TMP15]])
-; CHECK-NEXT: [[TMP17:%.*]] = call afn <3 x float> @llvm.trunc.v3f32(<3 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp afn une <3 x float> [[TMP17]], [[TMP2]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp afn olt <3 x float> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP20:%.*]] = and <3 x i1> [[TMP19]], [[TMP18]]
-; CHECK-NEXT: [[TMP21:%.*]] = select afn <3 x i1> [[TMP20]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP16]]
-; CHECK-NEXT: [[TMP22:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <3 x float> [[TMP22]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP24:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp afn une <3 x float> [[TMP2]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP27:%.*]] = fcmp afn oeq <3 x float> [[TMP26]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP28:%.*]] = fcmp afn olt <3 x float> [[TMP26]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP29:%.*]] = xor <3 x i1> [[TMP28]], [[TMP25]]
-; CHECK-NEXT: [[TMP30:%.*]] = select afn <3 x i1> [[TMP29]], <3 x float> zeroinitializer, <3 x float> [[TMP24]]
-; CHECK-NEXT: [[TMP31:%.*]] = select afn <3 x i1> [[TMP27]], <3 x float> splat (float 1.000000e+00), <3 x float> [[TMP30]]
-; CHECK-NEXT: [[TMP32:%.*]] = select afn <3 x i1> [[TMP23]], <3 x float> [[TMP31]], <3 x float> [[TMP21]]
-; CHECK-NEXT: [[TMP33:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <3 x float> [[TMP33]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP35:%.*]] = fcmp afn oeq <3 x float> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP36:%.*]] = or <3 x i1> [[TMP34]], [[TMP35]]
-; CHECK-NEXT: [[TMP37:%.*]] = fcmp afn olt <3 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP38:%.*]] = xor <3 x i1> [[TMP35]], [[TMP37]]
-; CHECK-NEXT: [[TMP39:%.*]] = select afn <3 x i1> [[TMP38]], <3 x float> zeroinitializer, <3 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP40:%.*]] = select afn <3 x i1> [[TMP14]], <3 x float> [[TMP4]], <3 x float> zeroinitializer
-; CHECK-NEXT: [[TMP41:%.*]] = call afn <3 x float> @llvm.copysign.v3f32(<3 x float> [[TMP39]], <3 x float> [[TMP40]])
-; CHECK-NEXT: [[TMP42:%.*]] = select afn <3 x i1> [[TMP36]], <3 x float> [[TMP41]], <3 x float> [[TMP32]]
-; CHECK-NEXT: [[TMP43:%.*]] = fcmp afn uno <3 x float> [[TMP4]], [[TMP2]]
-; CHECK-NEXT: [[TMP44:%.*]] = select afn <3 x i1> [[TMP43]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP42]]
-; CHECK-NEXT: ret <3 x float> [[TMP44]]
+; PRELINK-LABEL: define <3 x float> @test_pow_afn_v3f32
+; PRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <3 x float> @_Z10__pow_fastDv3_fS_(<3 x float> [[X]], <3 x float> [[Y]])
+; PRELINK-NEXT: ret <3 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <3 x float> @test_pow_afn_v3f32
+; NOPRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <3 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <3 x i1> [[TMP1]], <3 x float> splat (float 1.000000e+00), <3 x float> [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select afn <3 x i1> [[TMP3]], <3 x float> splat (float 1.000000e+00), <3 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <3 x float> @llvm.log2.v3f32(<3 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul afn <3 x float> [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn <3 x float> @llvm.exp2.v3f32(<3 x float> [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn <3 x float> @llvm.trunc.v3f32(<3 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <3 x float> [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul afn <3 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call afn <3 x float> @llvm.trunc.v3f32(<3 x float> [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une <3 x float> [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and <3 x i1> [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn <3 x i1> [[TMP14]], <3 x float> [[TMP4]], <3 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn <3 x float> @llvm.copysign.v3f32(<3 x float> [[TMP8]], <3 x float> [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn <3 x float> @llvm.trunc.v3f32(<3 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une <3 x float> [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt <3 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and <3 x i1> [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <3 x i1> [[TMP20]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <3 x float> [[TMP22]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn une <3 x float> [[TMP2]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = fcmp afn oeq <3 x float> [[TMP26]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn olt <3 x float> [[TMP26]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP29:%.*]] = xor <3 x i1> [[TMP28]], [[TMP25]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = select afn <3 x i1> [[TMP29]], <3 x float> zeroinitializer, <3 x float> [[TMP24]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <3 x i1> [[TMP27]], <3 x float> splat (float 1.000000e+00), <3 x float> [[TMP30]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = select afn <3 x i1> [[TMP23]], <3 x float> [[TMP31]], <3 x float> [[TMP21]]
+; NOPRELINK-NEXT: [[TMP33:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <3 x float> [[TMP33]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp afn oeq <3 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP36:%.*]] = or <3 x i1> [[TMP34]], [[TMP35]]
+; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp afn olt <3 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP38:%.*]] = xor <3 x i1> [[TMP35]], [[TMP37]]
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn <3 x i1> [[TMP38]], <3 x float> zeroinitializer, <3 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP40:%.*]] = select afn <3 x i1> [[TMP14]], <3 x float> [[TMP4]], <3 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP41:%.*]] = call afn <3 x float> @llvm.copysign.v3f32(<3 x float> [[TMP39]], <3 x float> [[TMP40]])
+; NOPRELINK-NEXT: [[TMP42:%.*]] = select afn <3 x i1> [[TMP36]], <3 x float> [[TMP41]], <3 x float> [[TMP32]]
+; NOPRELINK-NEXT: [[TMP43:%.*]] = fcmp afn uno <3 x float> [[TMP4]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn <3 x i1> [[TMP43]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP42]]
+; NOPRELINK-NEXT: ret <3 x float> [[TMP44]]
;
%pow = tail call afn <3 x float> @_Z3powDv3_fS_(<3 x float> %x, <3 x float> %y)
ret <3 x float> %pow
}
define <4 x float> @test_pow_afn_v4f32(<4 x float> %x, <4 x float> %y) {
-; CHECK-LABEL: define <4 x float> @test_pow_afn_v4f32
-; CHECK-SAME: (<4 x float> [[X:%.*]], <4 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <4 x float> [[X]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <4 x i1> [[TMP1]], <4 x float> splat (float 1.000000e+00), <4 x float> [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp afn oeq <4 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = select afn <4 x i1> [[TMP3]], <4 x float> splat (float 1.000000e+00), <4 x float> [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <4 x float> @llvm.log2.v4f32(<4 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fmul afn <4 x float> [[TMP2]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = call afn <4 x float> @llvm.exp2.v4f32(<4 x float> [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call afn <4 x float> @llvm.trunc.v4f32(<4 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <4 x float> [[TMP9]], [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = fmul afn <4 x float> [[TMP2]], splat (float 5.000000e-01)
-; CHECK-NEXT: [[TMP12:%.*]] = call afn <4 x float> @llvm.trunc.v4f32(<4 x float> [[TMP11]])
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp afn une <4 x float> [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = and <4 x i1> [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select afn <4 x i1> [[TMP14]], <4 x float> [[TMP4]], <4 x float> splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP16:%.*]] = call afn <4 x float> @llvm.copysign.v4f32(<4 x float> [[TMP8]], <4 x float> [[TMP15]])
-; CHECK-NEXT: [[TMP17:%.*]] = call afn <4 x float> @llvm.trunc.v4f32(<4 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp afn une <4 x float> [[TMP17]], [[TMP2]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp afn olt <4 x float> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP20:%.*]] = and <4 x i1> [[TMP19]], [[TMP18]]
-; CHECK-NEXT: [[TMP21:%.*]] = select afn <4 x i1> [[TMP20]], <4 x float> splat (float 0x7FF8000000000000), <4 x float> [[TMP16]]
-; CHECK-NEXT: [[TMP22:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <4 x float> [[TMP22]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP24:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp afn une <4 x float> [[TMP2]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP27:%.*]] = fcmp afn oeq <4 x float> [[TMP26]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP28:%.*]] = fcmp afn olt <4 x float> [[TMP26]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP29:%.*]] = xor <4 x i1> [[TMP28]], [[TMP25]]
-; CHECK-NEXT: [[TMP30:%.*]] = select afn <4 x i1> [[TMP29]], <4 x float> zeroinitializer, <4 x float> [[TMP24]]
-; CHECK-NEXT: [[TMP31:%.*]] = select afn <4 x i1> [[TMP27]], <4 x float> splat (float 1.000000e+00), <4 x float> [[TMP30]]
-; CHECK-NEXT: [[TMP32:%.*]] = select afn <4 x i1> [[TMP23]], <4 x float> [[TMP31]], <4 x float> [[TMP21]]
-; CHECK-NEXT: [[TMP33:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <4 x float> [[TMP33]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP35:%.*]] = fcmp afn oeq <4 x float> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP36:%.*]] = or <4 x i1> [[TMP34]], [[TMP35]]
-; CHECK-NEXT: [[TMP37:%.*]] = fcmp afn olt <4 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP38:%.*]] = xor <4 x i1> [[TMP35]], [[TMP37]]
-; CHECK-NEXT: [[TMP39:%.*]] = select afn <4 x i1> [[TMP38]], <4 x float> zeroinitializer, <4 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP40:%.*]] = select afn <4 x i1> [[TMP14]], <4 x float> [[TMP4]], <4 x float> zeroinitializer
-; CHECK-NEXT: [[TMP41:%.*]] = call afn <4 x float> @llvm.copysign.v4f32(<4 x float> [[TMP39]], <4 x float> [[TMP40]])
-; CHECK-NEXT: [[TMP42:%.*]] = select afn <4 x i1> [[TMP36]], <4 x float> [[TMP41]], <4 x float> [[TMP32]]
-; CHECK-NEXT: [[TMP43:%.*]] = fcmp afn uno <4 x float> [[TMP4]], [[TMP2]]
-; CHECK-NEXT: [[TMP44:%.*]] = select afn <4 x i1> [[TMP43]], <4 x float> splat (float 0x7FF8000000000000), <4 x float> [[TMP42]]
-; CHECK-NEXT: ret <4 x float> [[TMP44]]
+; PRELINK-LABEL: define <4 x float> @test_pow_afn_v4f32
+; PRELINK-SAME: (<4 x float> [[X:%.*]], <4 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <4 x float> @_Z10__pow_fastDv4_fS_(<4 x float> [[X]], <4 x float> [[Y]])
+; PRELINK-NEXT: ret <4 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <4 x float> @test_pow_afn_v4f32
+; NOPRELINK-SAME: (<4 x float> [[X:%.*]], <4 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <4 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <4 x i1> [[TMP1]], <4 x float> splat (float 1.000000e+00), <4 x float> [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp afn oeq <4 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select afn <4 x i1> [[TMP3]], <4 x float> splat (float 1.000000e+00), <4 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <4 x float> @llvm.log2.v4f32(<4 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul afn <4 x float> [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn <4 x float> @llvm.exp2.v4f32(<4 x float> [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn <4 x float> @llvm.trunc.v4f32(<4 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <4 x float> [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul afn <4 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call afn <4 x float> @llvm.trunc.v4f32(<4 x float> [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une <4 x float> [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and <4 x i1> [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn <4 x i1> [[TMP14]], <4 x float> [[TMP4]], <4 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn <4 x float> @llvm.copysign.v4f32(<4 x float> [[TMP8]], <4 x float> [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn <4 x float> @llvm.trunc.v4f32(<4 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une <4 x float> [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt <4 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and <4 x i1> [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <4 x i1> [[TMP20]], <4 x float> splat (float 0x7FF8000000000000), <4 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <4 x float> [[TMP22]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn une <4 x float> [[TMP2]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = fcmp afn oeq <4 x float> [[TMP26]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn olt <4 x float> [[TMP26]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP29:%.*]] = xor <4 x i1> [[TMP28]], [[TMP25]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = select afn <4 x i1> [[TMP29]], <4 x float> zeroinitializer, <4 x float> [[TMP24]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <4 x i1> [[TMP27]], <4 x float> splat (float 1.000000e+00), <4 x float> [[TMP30]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = select afn <4 x i1> [[TMP23]], <4 x float> [[TMP31]], <4 x float> [[TMP21]]
+; NOPRELINK-NEXT: [[TMP33:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <4 x float> [[TMP33]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp afn oeq <4 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP36:%.*]] = or <4 x i1> [[TMP34]], [[TMP35]]
+; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp afn olt <4 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP38:%.*]] = xor <4 x i1> [[TMP35]], [[TMP37]]
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn <4 x i1> [[TMP38]], <4 x float> zeroinitializer, <4 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP40:%.*]] = select afn <4 x i1> [[TMP14]], <4 x float> [[TMP4]], <4 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP41:%.*]] = call afn <4 x float> @llvm.copysign.v4f32(<4 x float> [[TMP39]], <4 x float> [[TMP40]])
+; NOPRELINK-NEXT: [[TMP42:%.*]] = select afn <4 x i1> [[TMP36]], <4 x float> [[TMP41]], <4 x float> [[TMP32]]
+; NOPRELINK-NEXT: [[TMP43:%.*]] = fcmp afn uno <4 x float> [[TMP4]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn <4 x i1> [[TMP43]], <4 x float> splat (float 0x7FF8000000000000), <4 x float> [[TMP42]]
+; NOPRELINK-NEXT: ret <4 x float> [[TMP44]]
;
%pow = tail call afn <4 x float> @_Z3powDv4_fS_(<4 x float> %x, <4 x float> %y)
ret <4 x float> %pow
}
define <8 x float> @test_pow_afn_v8f32(<8 x float> %x, <8 x float> %y) {
-; CHECK-LABEL: define <8 x float> @test_pow_afn_v8f32
-; CHECK-SAME: (<8 x float> [[X:%.*]], <8 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <8 x float> [[X]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <8 x i1> [[TMP1]], <8 x float> splat (float 1.000000e+00), <8 x float> [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp afn oeq <8 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = select afn <8 x i1> [[TMP3]], <8 x float> splat (float 1.000000e+00), <8 x float> [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <8 x float> @llvm.log2.v8f32(<8 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fmul afn <8 x float> [[TMP2]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = call afn <8 x float> @llvm.exp2.v8f32(<8 x float> [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call afn <8 x float> @llvm.trunc.v8f32(<8 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <8 x float> [[TMP9]], [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = fmul afn <8 x float> [[TMP2]], splat (float 5.000000e-01)
-; CHECK-NEXT: [[TMP12:%.*]] = call afn <8 x float> @llvm.trunc.v8f32(<8 x float> [[TMP11]])
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp afn une <8 x float> [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = and <8 x i1> [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select afn <8 x i1> [[TMP14]], <8 x float> [[TMP4]], <8 x float> splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP16:%.*]] = call afn <8 x float> @llvm.copysign.v8f32(<8 x float> [[TMP8]], <8 x float> [[TMP15]])
-; CHECK-NEXT: [[TMP17:%.*]] = call afn <8 x float> @llvm.trunc.v8f32(<8 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp afn une <8 x float> [[TMP17]], [[TMP2]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp afn olt <8 x float> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP20:%.*]] = and <8 x i1> [[TMP19]], [[TMP18]]
-; CHECK-NEXT: [[TMP21:%.*]] = select afn <8 x i1> [[TMP20]], <8 x float> splat (float 0x7FF8000000000000), <8 x float> [[TMP16]]
-; CHECK-NEXT: [[TMP22:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <8 x float> [[TMP22]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP24:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp afn une <8 x float> [[TMP2]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP27:%.*]] = fcmp afn oeq <8 x float> [[TMP26]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP28:%.*]] = fcmp afn olt <8 x float> [[TMP26]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP29:%.*]] = xor <8 x i1> [[TMP28]], [[TMP25]]
-; CHECK-NEXT: [[TMP30:%.*]] = select afn <8 x i1> [[TMP29]], <8 x float> zeroinitializer, <8 x float> [[TMP24]]
-; CHECK-NEXT: [[TMP31:%.*]] = select afn <8 x i1> [[TMP27]], <8 x float> splat (float 1.000000e+00), <8 x float> [[TMP30]]
-; CHECK-NEXT: [[TMP32:%.*]] = select afn <8 x i1> [[TMP23]], <8 x float> [[TMP31]], <8 x float> [[TMP21]]
-; CHECK-NEXT: [[TMP33:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <8 x float> [[TMP33]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP35:%.*]] = fcmp afn oeq <8 x float> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP36:%.*]] = or <8 x i1> [[TMP34]], [[TMP35]]
-; CHECK-NEXT: [[TMP37:%.*]] = fcmp afn olt <8 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP38:%.*]] = xor <8 x i1> [[TMP35]], [[TMP37]]
-; CHECK-NEXT: [[TMP39:%.*]] = select afn <8 x i1> [[TMP38]], <8 x float> zeroinitializer, <8 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP40:%.*]] = select afn <8 x i1> [[TMP14]], <8 x float> [[TMP4]], <8 x float> zeroinitializer
-; CHECK-NEXT: [[TMP41:%.*]] = call afn <8 x float> @llvm.copysign.v8f32(<8 x float> [[TMP39]], <8 x float> [[TMP40]])
-; CHECK-NEXT: [[TMP42:%.*]] = select afn <8 x i1> [[TMP36]], <8 x float> [[TMP41]], <8 x float> [[TMP32]]
-; CHECK-NEXT: [[TMP43:%.*]] = fcmp afn uno <8 x float> [[TMP4]], [[TMP2]]
-; CHECK-NEXT: [[TMP44:%.*]] = select afn <8 x i1> [[TMP43]], <8 x float> splat (float 0x7FF8000000000000), <8 x float> [[TMP42]]
-; CHECK-NEXT: ret <8 x float> [[TMP44]]
+; PRELINK-LABEL: define <8 x float> @test_pow_afn_v8f32
+; PRELINK-SAME: (<8 x float> [[X:%.*]], <8 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <8 x float> @_Z10__pow_fastDv8_fS_(<8 x float> [[X]], <8 x float> [[Y]])
+; PRELINK-NEXT: ret <8 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <8 x float> @test_pow_afn_v8f32
+; NOPRELINK-SAME: (<8 x float> [[X:%.*]], <8 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <8 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <8 x i1> [[TMP1]], <8 x float> splat (float 1.000000e+00), <8 x float> [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp afn oeq <8 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select afn <8 x i1> [[TMP3]], <8 x float> splat (float 1.000000e+00), <8 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <8 x float> @llvm.log2.v8f32(<8 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul afn <8 x float> [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn <8 x float> @llvm.exp2.v8f32(<8 x float> [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn <8 x float> @llvm.trunc.v8f32(<8 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <8 x float> [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul afn <8 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call afn <8 x float> @llvm.trunc.v8f32(<8 x float> [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une <8 x float> [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and <8 x i1> [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn <8 x i1> [[TMP14]], <8 x float> [[TMP4]], <8 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn <8 x float> @llvm.copysign.v8f32(<8 x float> [[TMP8]], <8 x float> [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn <8 x float> @llvm.trunc.v8f32(<8 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une <8 x float> [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt <8 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and <8 x i1> [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <8 x i1> [[TMP20]], <8 x float> splat (float 0x7FF8000000000000), <8 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <8 x float> [[TMP22]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn une <8 x float> [[TMP2]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = fcmp afn oeq <8 x float> [[TMP26]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn olt <8 x float> [[TMP26]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP29:%.*]] = xor <8 x i1> [[TMP28]], [[TMP25]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = select afn <8 x i1> [[TMP29]], <8 x float> zeroinitializer, <8 x float> [[TMP24]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <8 x i1> [[TMP27]], <8 x float> splat (float 1.000000e+00), <8 x float> [[TMP30]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = select afn <8 x i1> [[TMP23]], <8 x float> [[TMP31]], <8 x float> [[TMP21]]
+; NOPRELINK-NEXT: [[TMP33:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <8 x float> [[TMP33]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp afn oeq <8 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP36:%.*]] = or <8 x i1> [[TMP34]], [[TMP35]]
+; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp afn olt <8 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP38:%.*]] = xor <8 x i1> [[TMP35]], [[TMP37]]
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn <8 x i1> [[TMP38]], <8 x float> zeroinitializer, <8 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP40:%.*]] = select afn <8 x i1> [[TMP14]], <8 x float> [[TMP4]], <8 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP41:%.*]] = call afn <8 x float> @llvm.copysign.v8f32(<8 x float> [[TMP39]], <8 x float> [[TMP40]])
+; NOPRELINK-NEXT: [[TMP42:%.*]] = select afn <8 x i1> [[TMP36]], <8 x float> [[TMP41]], <8 x float> [[TMP32]]
+; NOPRELINK-NEXT: [[TMP43:%.*]] = fcmp afn uno <8 x float> [[TMP4]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn <8 x i1> [[TMP43]], <8 x float> splat (float 0x7FF8000000000000), <8 x float> [[TMP42]]
+; NOPRELINK-NEXT: ret <8 x float> [[TMP44]]
;
%pow = tail call afn <8 x float> @_Z3powDv8_fS_(<8 x float> %x, <8 x float> %y)
ret <8 x float> %pow
}
define <16 x float> @test_pow_afn_v16f32(<16 x float> %x, <16 x float> %y) {
-; CHECK-LABEL: define <16 x float> @test_pow_afn_v16f32
-; CHECK-SAME: (<16 x float> [[X:%.*]], <16 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <16 x float> [[X]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <16 x i1> [[TMP1]], <16 x float> splat (float 1.000000e+00), <16 x float> [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp afn oeq <16 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP4:%.*]] = select afn <16 x i1> [[TMP3]], <16 x float> splat (float 1.000000e+00), <16 x float> [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <16 x float> @llvm.log2.v16f32(<16 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fmul afn <16 x float> [[TMP2]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = call afn <16 x float> @llvm.exp2.v16f32(<16 x float> [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call afn <16 x float> @llvm.trunc.v16f32(<16 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <16 x float> [[TMP9]], [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = fmul afn <16 x float> [[TMP2]], splat (float 5.000000e-01)
-; CHECK-NEXT: [[TMP12:%.*]] = call afn <16 x float> @llvm.trunc.v16f32(<16 x float> [[TMP11]])
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp afn une <16 x float> [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = and <16 x i1> [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select afn <16 x i1> [[TMP14]], <16 x float> [[TMP4]], <16 x float> splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP16:%.*]] = call afn <16 x float> @llvm.copysign.v16f32(<16 x float> [[TMP8]], <16 x float> [[TMP15]])
-; CHECK-NEXT: [[TMP17:%.*]] = call afn <16 x float> @llvm.trunc.v16f32(<16 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp afn une <16 x float> [[TMP17]], [[TMP2]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp afn olt <16 x float> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP20:%.*]] = and <16 x i1> [[TMP19]], [[TMP18]]
-; CHECK-NEXT: [[TMP21:%.*]] = select afn <16 x i1> [[TMP20]], <16 x float> splat (float 0x7FF8000000000000), <16 x float> [[TMP16]]
-; CHECK-NEXT: [[TMP22:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <16 x float> [[TMP22]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP24:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp afn une <16 x float> [[TMP2]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP27:%.*]] = fcmp afn oeq <16 x float> [[TMP26]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP28:%.*]] = fcmp afn olt <16 x float> [[TMP26]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP29:%.*]] = xor <16 x i1> [[TMP28]], [[TMP25]]
-; CHECK-NEXT: [[TMP30:%.*]] = select afn <16 x i1> [[TMP29]], <16 x float> zeroinitializer, <16 x float> [[TMP24]]
-; CHECK-NEXT: [[TMP31:%.*]] = select afn <16 x i1> [[TMP27]], <16 x float> splat (float 1.000000e+00), <16 x float> [[TMP30]]
-; CHECK-NEXT: [[TMP32:%.*]] = select afn <16 x i1> [[TMP23]], <16 x float> [[TMP31]], <16 x float> [[TMP21]]
-; CHECK-NEXT: [[TMP33:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <16 x float> [[TMP33]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP35:%.*]] = fcmp afn oeq <16 x float> [[TMP4]], zeroinitializer
-; CHECK-NEXT: [[TMP36:%.*]] = or <16 x i1> [[TMP34]], [[TMP35]]
-; CHECK-NEXT: [[TMP37:%.*]] = fcmp afn olt <16 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP38:%.*]] = xor <16 x i1> [[TMP35]], [[TMP37]]
-; CHECK-NEXT: [[TMP39:%.*]] = select afn <16 x i1> [[TMP38]], <16 x float> zeroinitializer, <16 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP40:%.*]] = select afn <16 x i1> [[TMP14]], <16 x float> [[TMP4]], <16 x float> zeroinitializer
-; CHECK-NEXT: [[TMP41:%.*]] = call afn <16 x float> @llvm.copysign.v16f32(<16 x float> [[TMP39]], <16 x float> [[TMP40]])
-; CHECK-NEXT: [[TMP42:%.*]] = select afn <16 x i1> [[TMP36]], <16 x float> [[TMP41]], <16 x float> [[TMP32]]
-; CHECK-NEXT: [[TMP43:%.*]] = fcmp afn uno <16 x float> [[TMP4]], [[TMP2]]
-; CHECK-NEXT: [[TMP44:%.*]] = select afn <16 x i1> [[TMP43]], <16 x float> splat (float 0x7FF8000000000000), <16 x float> [[TMP42]]
-; CHECK-NEXT: ret <16 x float> [[TMP44]]
+; PRELINK-LABEL: define <16 x float> @test_pow_afn_v16f32
+; PRELINK-SAME: (<16 x float> [[X:%.*]], <16 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <16 x float> @_Z10__pow_fastDv16_fS_(<16 x float> [[X]], <16 x float> [[Y]])
+; PRELINK-NEXT: ret <16 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <16 x float> @test_pow_afn_v16f32
+; NOPRELINK-SAME: (<16 x float> [[X:%.*]], <16 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <16 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <16 x i1> [[TMP1]], <16 x float> splat (float 1.000000e+00), <16 x float> [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp afn oeq <16 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select afn <16 x i1> [[TMP3]], <16 x float> splat (float 1.000000e+00), <16 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <16 x float> @llvm.log2.v16f32(<16 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul afn <16 x float> [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn <16 x float> @llvm.exp2.v16f32(<16 x float> [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn <16 x float> @llvm.trunc.v16f32(<16 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <16 x float> [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul afn <16 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call afn <16 x float> @llvm.trunc.v16f32(<16 x float> [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une <16 x float> [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and <16 x i1> [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn <16 x i1> [[TMP14]], <16 x float> [[TMP4]], <16 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn <16 x float> @llvm.copysign.v16f32(<16 x float> [[TMP8]], <16 x float> [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn <16 x float> @llvm.trunc.v16f32(<16 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une <16 x float> [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt <16 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and <16 x i1> [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <16 x i1> [[TMP20]], <16 x float> splat (float 0x7FF8000000000000), <16 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <16 x float> [[TMP22]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn une <16 x float> [[TMP2]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = fcmp afn oeq <16 x float> [[TMP26]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn olt <16 x float> [[TMP26]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP29:%.*]] = xor <16 x i1> [[TMP28]], [[TMP25]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = select afn <16 x i1> [[TMP29]], <16 x float> zeroinitializer, <16 x float> [[TMP24]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <16 x i1> [[TMP27]], <16 x float> splat (float 1.000000e+00), <16 x float> [[TMP30]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = select afn <16 x i1> [[TMP23]], <16 x float> [[TMP31]], <16 x float> [[TMP21]]
+; NOPRELINK-NEXT: [[TMP33:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq <16 x float> [[TMP33]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp afn oeq <16 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP36:%.*]] = or <16 x i1> [[TMP34]], [[TMP35]]
+; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp afn olt <16 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP38:%.*]] = xor <16 x i1> [[TMP35]], [[TMP37]]
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn <16 x i1> [[TMP38]], <16 x float> zeroinitializer, <16 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP40:%.*]] = select afn <16 x i1> [[TMP14]], <16 x float> [[TMP4]], <16 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP41:%.*]] = call afn <16 x float> @llvm.copysign.v16f32(<16 x float> [[TMP39]], <16 x float> [[TMP40]])
+; NOPRELINK-NEXT: [[TMP42:%.*]] = select afn <16 x i1> [[TMP36]], <16 x float> [[TMP41]], <16 x float> [[TMP32]]
+; NOPRELINK-NEXT: [[TMP43:%.*]] = fcmp afn uno <16 x float> [[TMP4]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn <16 x i1> [[TMP43]], <16 x float> splat (float 0x7FF8000000000000), <16 x float> [[TMP42]]
+; NOPRELINK-NEXT: ret <16 x float> [[TMP44]]
;
%pow = tail call afn <16 x float> @_Z3powDv16_fS_(<16 x float> %x, <16 x float> %y)
ret <16 x float> %pow
@@ -907,273 +968,303 @@ define <16 x half> @test_pow_v16f16(<16 x half> %x, <16 x half> %y) {
}
define float @test_pow_afn_f32_minsize(float %x, float %y) #0 {
-; CHECK-LABEL: define float @test_pow_afn_f32_minsize
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR2:[0-9]+]] {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP4:%.*]] = select afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.log2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fmul afn float [[TMP2]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = call afn float @llvm.exp2.f32(float [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = fmul afn float [[TMP2]], 5.000000e-01
-; CHECK-NEXT: [[TMP12:%.*]] = call afn float @llvm.trunc.f32(float [[TMP11]])
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp afn une float [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
-; CHECK-NEXT: [[TMP16:%.*]] = call afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
-; CHECK-NEXT: [[TMP17:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[TMP17]], [[TMP2]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp afn olt float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; CHECK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
-; CHECK-NEXT: [[TMP22:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP24:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp afn une float [[TMP2]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP27:%.*]] = fcmp afn oeq float [[TMP26]], 1.000000e+00
-; CHECK-NEXT: [[TMP28:%.*]] = fcmp afn olt float [[TMP26]], 1.000000e+00
-; CHECK-NEXT: [[TMP29:%.*]] = xor i1 [[TMP28]], [[TMP25]]
-; CHECK-NEXT: [[TMP30:%.*]] = select afn i1 [[TMP29]], float 0.000000e+00, float [[TMP24]]
-; CHECK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
-; CHECK-NEXT: [[TMP32:%.*]] = select afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
-; CHECK-NEXT: [[TMP33:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP34:%.*]] = fcmp afn oeq float [[TMP33]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP35:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
-; CHECK-NEXT: [[TMP37:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
-; CHECK-NEXT: [[TMP39:%.*]] = select afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP40:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
-; CHECK-NEXT: [[TMP41:%.*]] = call afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
-; CHECK-NEXT: [[TMP42:%.*]] = select afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
-; CHECK-NEXT: [[TMP43:%.*]] = fcmp afn uno float [[TMP4]], [[TMP2]]
-; CHECK-NEXT: [[TMP44:%.*]] = select afn i1 [[TMP43]], float 0x7FF8000000000000, float [[TMP42]]
-; CHECK-NEXT: ret float [[TMP44]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_minsize
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR2:[0-9]+]] {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z10__pow_fastff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_minsize
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR2:[0-9]+]] {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.log2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul afn float [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn float @llvm.exp2.f32(float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call afn float @llvm.trunc.f32(float [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une float [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn une float [[TMP2]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = fcmp afn oeq float [[TMP26]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn olt float [[TMP26]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP29:%.*]] = xor i1 [[TMP28]], [[TMP25]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = select afn i1 [[TMP29]], float 0.000000e+00, float [[TMP24]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = select afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
+; NOPRELINK-NEXT: [[TMP33:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq float [[TMP33]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
+; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP40:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP41:%.*]] = call afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
+; NOPRELINK-NEXT: [[TMP42:%.*]] = select afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
+; NOPRELINK-NEXT: [[TMP43:%.*]] = fcmp afn uno float [[TMP4]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn i1 [[TMP43]], float 0x7FF8000000000000, float [[TMP42]]
+; NOPRELINK-NEXT: ret float [[TMP44]]
;
%pow = tail call afn float @_Z3powff(float %x, float %y)
ret float %pow
}
define float @test_pow_afn_f32_nnan_minsize(float %x, float %y) #0 {
-; CHECK-LABEL: define float @test_pow_afn_f32_nnan_minsize
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp nnan afn oeq float [[X]], 1.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select nnan afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP4:%.*]] = select nnan afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fmul nnan afn float [[TMP2]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[TMP9]], [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
-; CHECK-NEXT: [[TMP12:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP11]])
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une float [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
-; CHECK-NEXT: [[TMP16:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
-; CHECK-NEXT: [[TMP17:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[TMP17]], [[TMP2]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; CHECK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
-; CHECK-NEXT: [[TMP22:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP24:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp nnan afn une float [[TMP2]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP27:%.*]] = fcmp nnan afn oeq float [[TMP26]], 1.000000e+00
-; CHECK-NEXT: [[TMP28:%.*]] = fcmp nnan afn olt float [[TMP26]], 1.000000e+00
-; CHECK-NEXT: [[TMP29:%.*]] = xor i1 [[TMP28]], [[TMP25]]
-; CHECK-NEXT: [[TMP30:%.*]] = select nnan afn i1 [[TMP29]], float 0.000000e+00, float [[TMP24]]
-; CHECK-NEXT: [[TMP31:%.*]] = select nnan afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
-; CHECK-NEXT: [[TMP32:%.*]] = select nnan afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
-; CHECK-NEXT: [[TMP33:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq float [[TMP33]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP35:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
-; CHECK-NEXT: [[TMP37:%.*]] = fcmp nnan afn olt float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
-; CHECK-NEXT: [[TMP39:%.*]] = select nnan afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP40:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
-; CHECK-NEXT: [[TMP41:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
-; CHECK-NEXT: [[TMP42:%.*]] = select nnan afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
-; CHECK-NEXT: ret float [[TMP42]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_nnan_minsize
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR2]] {
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan afn float @_Z10__pow_fastff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_nnan_minsize
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR2]] {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select nnan afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul nnan afn float [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une float [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp nnan afn une float [[TMP2]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = fcmp nnan afn oeq float [[TMP26]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp nnan afn olt float [[TMP26]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP29:%.*]] = xor i1 [[TMP28]], [[TMP25]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = select nnan afn i1 [[TMP29]], float 0.000000e+00, float [[TMP24]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select nnan afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = select nnan afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
+; NOPRELINK-NEXT: [[TMP33:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq float [[TMP33]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
+; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp nnan afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select nnan afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP40:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP41:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
+; NOPRELINK-NEXT: [[TMP42:%.*]] = select nnan afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
+; NOPRELINK-NEXT: ret float [[TMP42]]
;
%pow = tail call afn nnan float @_Z3powff(float %x, float %y)
ret float %pow
}
define float @test_pow_afn_f32_noinline(float %x, float %y) {
-; CHECK-LABEL: define float @test_pow_afn_f32_noinline
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP4:%.*]] = select afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.log2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fmul afn float [[TMP2]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = call afn float @llvm.exp2.f32(float [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = fmul afn float [[TMP2]], 5.000000e-01
-; CHECK-NEXT: [[TMP12:%.*]] = call afn float @llvm.trunc.f32(float [[TMP11]])
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp afn une float [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
-; CHECK-NEXT: [[TMP16:%.*]] = call afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
-; CHECK-NEXT: [[TMP17:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[TMP17]], [[TMP2]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp afn olt float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; CHECK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
-; CHECK-NEXT: [[TMP22:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP24:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp afn une float [[TMP2]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP27:%.*]] = fcmp afn oeq float [[TMP26]], 1.000000e+00
-; CHECK-NEXT: [[TMP28:%.*]] = fcmp afn olt float [[TMP26]], 1.000000e+00
-; CHECK-NEXT: [[TMP29:%.*]] = xor i1 [[TMP28]], [[TMP25]]
-; CHECK-NEXT: [[TMP30:%.*]] = select afn i1 [[TMP29]], float 0.000000e+00, float [[TMP24]]
-; CHECK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
-; CHECK-NEXT: [[TMP32:%.*]] = select afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
-; CHECK-NEXT: [[TMP33:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP34:%.*]] = fcmp afn oeq float [[TMP33]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP35:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
-; CHECK-NEXT: [[TMP37:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
-; CHECK-NEXT: [[TMP39:%.*]] = select afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP40:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
-; CHECK-NEXT: [[TMP41:%.*]] = call afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
-; CHECK-NEXT: [[TMP42:%.*]] = select afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
-; CHECK-NEXT: [[TMP43:%.*]] = fcmp afn uno float [[TMP4]], [[TMP2]]
-; CHECK-NEXT: [[TMP44:%.*]] = select afn i1 [[TMP43]], float 0x7FF8000000000000, float [[TMP42]]
-; CHECK-NEXT: ret float [[TMP44]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_noinline
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z10__pow_fastff(float [[X]], float [[Y]]) #[[ATTR5:[0-9]+]]
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_noinline
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.log2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul afn float [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn float @llvm.exp2.f32(float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call afn float @llvm.trunc.f32(float [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une float [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn une float [[TMP2]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = fcmp afn oeq float [[TMP26]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn olt float [[TMP26]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP29:%.*]] = xor i1 [[TMP28]], [[TMP25]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = select afn i1 [[TMP29]], float 0.000000e+00, float [[TMP24]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = select afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
+; NOPRELINK-NEXT: [[TMP33:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp afn oeq float [[TMP33]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
+; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP40:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP41:%.*]] = call afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
+; NOPRELINK-NEXT: [[TMP42:%.*]] = select afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
+; NOPRELINK-NEXT: [[TMP43:%.*]] = fcmp afn uno float [[TMP4]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP44:%.*]] = select afn i1 [[TMP43]], float 0x7FF8000000000000, float [[TMP42]]
+; NOPRELINK-NEXT: ret float [[TMP44]]
;
%pow = tail call afn float @_Z3powff(float %x, float %y) #1
ret float %pow
}
define float @test_pow_afn_f32_nnan_noinline(float %x, float %y) {
-; CHECK-LABEL: define float @test_pow_afn_f32_nnan_noinline
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp nnan afn oeq float [[X]], 1.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select nnan afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP4:%.*]] = select nnan afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fmul nnan afn float [[TMP2]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[TMP9]], [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
-; CHECK-NEXT: [[TMP12:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP11]])
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une float [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
-; CHECK-NEXT: [[TMP16:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
-; CHECK-NEXT: [[TMP17:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[TMP17]], [[TMP2]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; CHECK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
-; CHECK-NEXT: [[TMP22:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP24:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp nnan afn une float [[TMP2]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP27:%.*]] = fcmp nnan afn oeq float [[TMP26]], 1.000000e+00
-; CHECK-NEXT: [[TMP28:%.*]] = fcmp nnan afn olt float [[TMP26]], 1.000000e+00
-; CHECK-NEXT: [[TMP29:%.*]] = xor i1 [[TMP28]], [[TMP25]]
-; CHECK-NEXT: [[TMP30:%.*]] = select nnan afn i1 [[TMP29]], float 0.000000e+00, float [[TMP24]]
-; CHECK-NEXT: [[TMP31:%.*]] = select nnan afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
-; CHECK-NEXT: [[TMP32:%.*]] = select nnan afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
-; CHECK-NEXT: [[TMP33:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq float [[TMP33]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP35:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
-; CHECK-NEXT: [[TMP37:%.*]] = fcmp nnan afn olt float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
-; CHECK-NEXT: [[TMP39:%.*]] = select nnan afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP40:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
-; CHECK-NEXT: [[TMP41:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
-; CHECK-NEXT: [[TMP42:%.*]] = select nnan afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
-; CHECK-NEXT: ret float [[TMP42]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_nnan_noinline
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan afn float @_Z10__pow_fastff(float [[X]], float [[Y]]) #[[ATTR5]]
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_nnan_noinline
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select nnan afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul nnan afn float [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une float [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp nnan afn une float [[TMP2]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = fcmp nnan afn oeq float [[TMP26]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp nnan afn olt float [[TMP26]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP29:%.*]] = xor i1 [[TMP28]], [[TMP25]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = select nnan afn i1 [[TMP29]], float 0.000000e+00, float [[TMP24]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select nnan afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = select nnan afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
+; NOPRELINK-NEXT: [[TMP33:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq float [[TMP33]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
+; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp nnan afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select nnan afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP40:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP41:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
+; NOPRELINK-NEXT: [[TMP42:%.*]] = select nnan afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
+; NOPRELINK-NEXT: ret float [[TMP42]]
;
%pow = tail call afn nnan float @_Z3powff(float %x, float %y) #1
ret float %pow
}
define float @test_pow_afn_f32_strictfp(float %x, float %y) #2 {
-; CHECK-LABEL: define float @test_pow_afn_f32_strictfp
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR3:[0-9]+]] {
-; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[X]], float 1.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
-; CHECK-NEXT: [[TMP2:%.*]] = select nnan nsz afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
-; CHECK-NEXT: [[TMP3:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP2]], float 0.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
-; CHECK-NEXT: [[TMP4:%.*]] = select nnan nsz afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan nsz afn float @llvm.fabs.f32(float [[TMP4]]) #[[ATTR3]]
-; CHECK-NEXT: [[TMP6:%.*]] = call nnan nsz afn float @llvm.log2.f32(float [[TMP5]]) #[[ATTR3]]
-; CHECK-NEXT: [[TMP7:%.*]] = call nnan nsz afn float @llvm.experimental.constrained.fmul.f32(float [[TMP2]], float [[TMP6]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR3]]
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan nsz afn float @llvm.exp2.f32(float [[TMP7]]) #[[ATTR3]]
-; CHECK-NEXT: [[TMP9:%.*]] = call nnan nsz afn float @llvm.trunc.f32(float [[TMP2]]) #[[ATTR3]]
-; CHECK-NEXT: [[TMP10:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP9]], float [[TMP2]], metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
-; CHECK-NEXT: [[TMP11:%.*]] = call nnan nsz afn float @llvm.experimental.constrained.fmul.f32(float [[TMP2]], float 5.000000e-01, metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR3]]
-; CHECK-NEXT: [[TMP12:%.*]] = call nnan nsz afn float @llvm.trunc.f32(float [[TMP11]]) #[[ATTR3]]
-; CHECK-NEXT: [[TMP13:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP12]], float [[TMP11]], metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
-; CHECK-NEXT: [[TMP14:%.*]] = xor i1 [[TMP13]], true
-; CHECK-NEXT: [[TMP15:%.*]] = and i1 [[TMP10]], [[TMP14]]
-; CHECK-NEXT: [[TMP16:%.*]] = select nnan nsz afn i1 [[TMP15]], float [[TMP4]], float 1.000000e+00
-; CHECK-NEXT: [[TMP17:%.*]] = call nnan nsz afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP16]]) #[[ATTR3]]
-; CHECK-NEXT: [[TMP18:%.*]] = call nnan nsz afn float @llvm.trunc.f32(float [[TMP2]]) #[[ATTR3]]
-; CHECK-NEXT: [[TMP19:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP18]], float [[TMP2]], metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
-; CHECK-NEXT: [[TMP20:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP4]], float 0.000000e+00, metadata !"olt", metadata !"fpexcept.strict") #[[ATTR3]]
-; CHECK-NEXT: [[TMP21:%.*]] = xor i1 [[TMP19]], true
-; CHECK-NEXT: [[TMP22:%.*]] = and i1 [[TMP20]], [[TMP21]]
-; CHECK-NEXT: [[TMP23:%.*]] = select nnan nsz afn i1 [[TMP22]], float 0x7FF8000000000000, float [[TMP17]]
-; CHECK-NEXT: [[TMP24:%.*]] = call nnan nsz afn float @llvm.fabs.f32(float [[TMP2]]) #[[ATTR3]]
-; CHECK-NEXT: [[TMP25:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP24]], float 0x7FF0000000000000, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
-; CHECK-NEXT: [[TMP26:%.*]] = call nnan nsz afn float @llvm.fabs.f32(float [[TMP2]]) #[[ATTR3]]
-; CHECK-NEXT: [[TMP27:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP2]], float [[TMP26]], metadata !"une", metadata !"fpexcept.strict") #[[ATTR3]]
-; CHECK-NEXT: [[TMP28:%.*]] = call nnan nsz afn float @llvm.fabs.f32(float [[TMP4]]) #[[ATTR3]]
-; CHECK-NEXT: [[TMP29:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP28]], float 1.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
-; CHECK-NEXT: [[TMP30:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP28]], float 1.000000e+00, metadata !"olt", metadata !"fpexcept.strict") #[[ATTR3]]
-; CHECK-NEXT: [[TMP31:%.*]] = xor i1 [[TMP30]], [[TMP27]]
-; CHECK-NEXT: [[TMP32:%.*]] = select nnan nsz afn i1 [[TMP31]], float 0.000000e+00, float [[TMP26]]
-; CHECK-NEXT: [[TMP33:%.*]] = select nnan nsz afn i1 [[TMP29]], float [[TMP28]], float [[TMP32]]
-; CHECK-NEXT: [[TMP34:%.*]] = select nnan nsz afn i1 [[TMP25]], float [[TMP33]], float [[TMP23]]
-; CHECK-NEXT: [[TMP35:%.*]] = call nnan nsz afn float @llvm.fabs.f32(float [[TMP4]]) #[[ATTR3]]
-; CHECK-NEXT: [[TMP36:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP35]], float 0x7FF0000000000000, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
-; CHECK-NEXT: [[TMP37:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP4]], float 0.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
-; CHECK-NEXT: [[TMP38:%.*]] = or i1 [[TMP36]], [[TMP37]]
-; CHECK-NEXT: [[TMP39:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP2]], float 0.000000e+00, metadata !"olt", metadata !"fpexcept.strict") #[[ATTR3]]
-; CHECK-NEXT: [[TMP40:%.*]] = xor i1 [[TMP37]], [[TMP39]]
-; CHECK-NEXT: [[TMP41:%.*]] = select nnan nsz afn i1 [[TMP40]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP42:%.*]] = select nnan nsz afn i1 [[TMP15]], float [[TMP4]], float 0.000000e+00
-; CHECK-NEXT: [[TMP43:%.*]] = call nnan nsz afn float @llvm.copysign.f32(float [[TMP41]], float [[TMP42]]) #[[ATTR3]]
-; CHECK-NEXT: [[TMP44:%.*]] = select nnan nsz afn i1 [[TMP38]], float [[TMP43]], float [[TMP34]]
-; CHECK-NEXT: [[TMP45:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP4]], float [[TMP2]], metadata !"uno", metadata !"fpexcept.strict") #[[ATTR3]]
-; CHECK-NEXT: [[TMP46:%.*]] = select nnan nsz afn i1 [[TMP45]], float 0x7FF8000000000000, float [[TMP44]]
-; CHECK-NEXT: ret float [[TMP46]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_strictfp
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR3:[0-9]+]] {
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan nsz afn float @_Z10__pow_fastff(float [[X]], float [[Y]]) #[[ATTR3]]
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_strictfp
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR3:[0-9]+]] {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[X]], float 1.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan nsz afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP2]], float 0.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select nnan nsz afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan nsz afn float @llvm.fabs.f32(float [[TMP4]]) #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan nsz afn float @llvm.log2.f32(float [[TMP5]]) #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call nnan nsz afn float @llvm.experimental.constrained.fmul.f32(float [[TMP2]], float [[TMP6]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan nsz afn float @llvm.exp2.f32(float [[TMP7]]) #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call nnan nsz afn float @llvm.trunc.f32(float [[TMP2]]) #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP9]], float [[TMP2]], metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = call nnan nsz afn float @llvm.experimental.constrained.fmul.f32(float [[TMP2]], float 5.000000e-01, metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call nnan nsz afn float @llvm.trunc.f32(float [[TMP11]]) #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP12]], float [[TMP11]], metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = xor i1 [[TMP13]], true
+; NOPRELINK-NEXT: [[TMP15:%.*]] = and i1 [[TMP10]], [[TMP14]]
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select nnan nsz afn i1 [[TMP15]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call nnan nsz afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP16]]) #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP18:%.*]] = call nnan nsz afn float @llvm.trunc.f32(float [[TMP2]]) #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP18]], float [[TMP2]], metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP4]], float 0.000000e+00, metadata !"olt", metadata !"fpexcept.strict") #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = xor i1 [[TMP19]], true
+; NOPRELINK-NEXT: [[TMP22:%.*]] = and i1 [[TMP20]], [[TMP21]]
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select nnan nsz afn i1 [[TMP22]], float 0x7FF8000000000000, float [[TMP17]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = call nnan nsz afn float @llvm.fabs.f32(float [[TMP2]]) #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP25:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP24]], float 0x7FF0000000000000, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call nnan nsz afn float @llvm.fabs.f32(float [[TMP2]]) #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP27:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP2]], float [[TMP26]], metadata !"une", metadata !"fpexcept.strict") #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call nnan nsz afn float @llvm.fabs.f32(float [[TMP4]]) #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP28]], float 1.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP28]], float 1.000000e+00, metadata !"olt", metadata !"fpexcept.strict") #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = xor i1 [[TMP30]], [[TMP27]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = select nnan nsz afn i1 [[TMP31]], float 0.000000e+00, float [[TMP26]]
+; NOPRELINK-NEXT: [[TMP33:%.*]] = select nnan nsz afn i1 [[TMP29]], float [[TMP28]], float [[TMP32]]
+; NOPRELINK-NEXT: [[TMP34:%.*]] = select nnan nsz afn i1 [[TMP25]], float [[TMP33]], float [[TMP23]]
+; NOPRELINK-NEXT: [[TMP35:%.*]] = call nnan nsz afn float @llvm.fabs.f32(float [[TMP4]]) #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP36:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP35]], float 0x7FF0000000000000, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP37:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP4]], float 0.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP38:%.*]] = or i1 [[TMP36]], [[TMP37]]
+; NOPRELINK-NEXT: [[TMP39:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP2]], float 0.000000e+00, metadata !"olt", metadata !"fpexcept.strict") #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP40:%.*]] = xor i1 [[TMP37]], [[TMP39]]
+; NOPRELINK-NEXT: [[TMP41:%.*]] = select nnan nsz afn i1 [[TMP40]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP42:%.*]] = select nnan nsz afn i1 [[TMP15]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP43:%.*]] = call nnan nsz afn float @llvm.copysign.f32(float [[TMP41]], float [[TMP42]]) #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP44:%.*]] = select nnan nsz afn i1 [[TMP38]], float [[TMP43]], float [[TMP34]]
+; NOPRELINK-NEXT: [[TMP45:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP4]], float [[TMP2]], metadata !"uno", metadata !"fpexcept.strict") #[[ATTR3]]
+; NOPRELINK-NEXT: [[TMP46:%.*]] = select nnan nsz afn i1 [[TMP45]], float 0x7FF8000000000000, float [[TMP44]]
+; NOPRELINK-NEXT: ret float [[TMP46]]
;
%pow = tail call afn nsz nnan float @_Z3powff(float %x, float %y) #2
ret float %pow
}
define float @test_pow_fast_f32_nobuiltin(float %x, float %y) {
-; CHECK-LABEL: define float @test_pow_fast_f32_nobuiltin
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call fast float @_Z3powff(float [[X]], float [[Y]]) #[[ATTR6:[0-9]+]]
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_fast_f32_nobuiltin
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call fast float @_Z3powff(float [[X]], float [[Y]]) #[[ATTR6:[0-9]+]]
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_fast_f32_nobuiltin
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call fast float @_Z3powff(float [[X]], float [[Y]]) #[[ATTR5:[0-9]+]]
+; NOPRELINK-NEXT: ret float [[POW]]
;
%pow = tail call fast float @_Z3powff(float %x, float %y) #3
ret float %pow
@@ -1216,9 +1307,44 @@ define <2 x float> @test_pow_afn_v2f32_neg0.0(<2 x float> %x) {
}
define <2 x float> @test_pow_afn_v2f32_plus_minus_0.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_0.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: ret <2 x float> splat (float 1.000000e+00)
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_0.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: ret <2 x float> splat (float 1.000000e+00)
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_0.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float 0.000000e+00, float -0.000000e+00>
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select afn <2 x i1> [[TMP3]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une <2 x float> [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP8]], <2 x float> [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une <2 x float> [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt <2 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <2 x i1> [[TMP20]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <2 x float> [[TMP22]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn oeq <2 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = or <2 x i1> [[TMP23]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP24]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> [[TMP28]], <2 x float> [[TMP21]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 0.0, float -0.0>)
ret <2 x float> %pow
@@ -1243,100 +1369,309 @@ define <3 x float> @test_pow_afn_v3f32_neg0.0_splat_undef(<3 x float> %x, <3 x f
}
define float @test_pow_afn_f32_0.5(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32_0.5
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[__POW2SQRT:%.*]] = call afn float @_Z4sqrtf(float [[X]])
-; CHECK-NEXT: ret float [[__POW2SQRT]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_0.5
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[__POW2SQRT:%.*]] = call afn float @_Z4sqrtf(float [[X]])
+; PRELINK-NEXT: ret float [[__POW2SQRT]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_0.5
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float 5.000000e-01
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
+; NOPRELINK-NEXT: ret float [[TMP29]]
;
%pow = tail call afn float @_Z3powff(float %x, float 0.5)
ret float %pow
}
define float @test_pow_afn_f32_neg0.5(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32_neg0.5
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[__POW2RSQRT:%.*]] = call afn float @_Z5rsqrtf(float [[X]])
-; CHECK-NEXT: ret float [[__POW2RSQRT]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_neg0.5
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[__POW2RSQRT:%.*]] = call afn float @_Z5rsqrtf(float [[X]])
+; PRELINK-NEXT: ret float [[__POW2RSQRT]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_neg0.5
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float -5.000000e-01
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor i1 [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP23]], float [[TMP28]], float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
+; NOPRELINK-NEXT: ret float [[TMP31]]
;
%pow = tail call afn float @_Z3powff(float %x, float -0.5)
ret float %pow
}
define <2 x float> @test_pow_afn_v2f32_0.5(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_0.5
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[__POW2SQRT:%.*]] = call afn <2 x float> @_Z4sqrtDv2_f(<2 x float> [[X]])
-; CHECK-NEXT: ret <2 x float> [[__POW2SQRT]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_0.5
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[__POW2SQRT:%.*]] = call afn <2 x float> @_Z4sqrtDv2_f(<2 x float> [[X]])
+; PRELINK-NEXT: ret <2 x float> [[__POW2SQRT]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_0.5
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP29]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 0.5, float 0.5>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_neg0.5(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg0.5
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[__POW2RSQRT:%.*]] = call afn <2 x float> @_Z5rsqrtDv2_f(<2 x float> [[X]])
-; CHECK-NEXT: ret <2 x float> [[__POW2RSQRT]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg0.5
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[__POW2RSQRT:%.*]] = call afn <2 x float> @_Z5rsqrtDv2_f(<2 x float> [[X]])
+; PRELINK-NEXT: ret <2 x float> [[__POW2RSQRT]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg0.5
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float -5.000000e-01)
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float -0.5, float -0.5>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_plus_minus_0.5(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_0.5
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float 5.000000e-01, float -5.000000e-01>
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; CHECK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
-; CHECK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
-; CHECK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
-; CHECK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
-; CHECK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
-; CHECK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; CHECK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
-; CHECK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
-; CHECK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
-; CHECK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
-; CHECK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
-; CHECK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
-; CHECK-NEXT: ret <2 x float> [[TMP31]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_0.5
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 5.000000e-01, float -5.000000e-01>)
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_0.5
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float 5.000000e-01, float -5.000000e-01>
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 0.5, float -0.5>)
ret <2 x float> %pow
}
define <3 x float> @test_pow_afn_v3f32_0.5_splat_undef(<3 x float> %x, <3 x float> %y) {
-; CHECK-LABEL: define <3 x float> @test_pow_afn_v3f32_0.5_splat_undef
-; CHECK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[__POW2SQRT:%.*]] = call afn <3 x float> @_Z4sqrtDv3_f(<3 x float> [[X]])
-; CHECK-NEXT: ret <3 x float> [[__POW2SQRT]]
+; PRELINK-LABEL: define <3 x float> @test_pow_afn_v3f32_0.5_splat_undef
+; PRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[__POW2SQRT:%.*]] = call afn <3 x float> @_Z4sqrtDv3_f(<3 x float> [[X]])
+; PRELINK-NEXT: ret <3 x float> [[__POW2SQRT]]
+;
+; NOPRELINK-LABEL: define <3 x float> @test_pow_afn_v3f32_0.5_splat_undef
+; NOPRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <3 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <3 x i1> [[TMP1]], <3 x float> splat (float 1.000000e+00), <3 x float> <float 5.000000e-01, float poison, float 5.000000e-01>
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <3 x float> @llvm.log2.v3f32(<3 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <3 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <3 x float> @llvm.exp2.v3f32(<3 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <3 x float> @llvm.trunc.v3f32(<3 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <3 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <3 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <3 x float> @llvm.trunc.v3f32(<3 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <3 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <3 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <3 x i1> [[TMP12]], <3 x float> [[X]], <3 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <3 x float> @llvm.copysign.v3f32(<3 x float> [[TMP6]], <3 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <3 x float> @llvm.trunc.v3f32(<3 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <3 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <3 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <3 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <3 x i1> [[TMP18]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <3 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <3 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <3 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <3 x i1> [[TMP22]], <3 x float> zeroinitializer, <3 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <3 x i1> [[TMP12]], <3 x float> [[X]], <3 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <3 x float> @llvm.copysign.v3f32(<3 x float> [[TMP24]], <3 x float> [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <3 x i1> [[TMP23]], <3 x float> [[TMP26]], <3 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <3 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <3 x i1> [[TMP28]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP27]]
+; NOPRELINK-NEXT: ret <3 x float> [[TMP29]]
;
%pow = tail call afn <3 x float> @_Z3powDv3_fS_(<3 x float> %x, <3 x float> <float 0.5, float poison, float 0.5>)
ret <3 x float> %pow
}
define <3 x float> @test_pow_afn_v3f32_neg0.5_splat_undef(<3 x float> %x, <3 x float> %y) {
-; CHECK-LABEL: define <3 x float> @test_pow_afn_v3f32_neg0.5_splat_undef
-; CHECK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[__POW2RSQRT:%.*]] = call afn <3 x float> @_Z5rsqrtDv3_f(<3 x float> [[X]])
-; CHECK-NEXT: ret <3 x float> [[__POW2RSQRT]]
+; PRELINK-LABEL: define <3 x float> @test_pow_afn_v3f32_neg0.5_splat_undef
+; PRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[__POW2RSQRT:%.*]] = call afn <3 x float> @_Z5rsqrtDv3_f(<3 x float> [[X]])
+; PRELINK-NEXT: ret <3 x float> [[__POW2RSQRT]]
+;
+; NOPRELINK-LABEL: define <3 x float> @test_pow_afn_v3f32_neg0.5_splat_undef
+; NOPRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <3 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <3 x i1> [[TMP1]], <3 x float> splat (float 1.000000e+00), <3 x float> <float -5.000000e-01, float poison, float -5.000000e-01>
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <3 x float> @llvm.log2.v3f32(<3 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <3 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <3 x float> @llvm.exp2.v3f32(<3 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <3 x float> @llvm.trunc.v3f32(<3 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <3 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <3 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <3 x float> @llvm.trunc.v3f32(<3 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <3 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <3 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <3 x i1> [[TMP12]], <3 x float> [[X]], <3 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <3 x float> @llvm.copysign.v3f32(<3 x float> [[TMP6]], <3 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <3 x float> @llvm.trunc.v3f32(<3 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <3 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <3 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <3 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <3 x i1> [[TMP18]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <3 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <3 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <3 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <3 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <3 x i1> [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <3 x i1> [[TMP25]], <3 x float> zeroinitializer, <3 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <3 x i1> [[TMP12]], <3 x float> [[X]], <3 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <3 x float> @llvm.copysign.v3f32(<3 x float> [[TMP26]], <3 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <3 x i1> [[TMP23]], <3 x float> [[TMP28]], <3 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <3 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <3 x i1> [[TMP30]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <3 x float> [[TMP31]]
;
%pow = tail call afn <3 x float> @_Z3powDv3_fS_(<3 x float> %x, <3 x float> <float -0.5, float poison, float -0.5>)
ret <3 x float> %pow
@@ -1381,10 +1716,45 @@ define <2 x float> @test_pow_afn_v2f32_neg1.0(<2 x float> %x) {
}
define <2 x float> @test_pow_afn_v2f32_plus_minus_1.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_1.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 1, i32 -1>)
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_1.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 1, i32 -1>)
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_1.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float 1.000000e+00, float -1.000000e+00>
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 1.0, float -1.0>)
ret <2 x float> %pow
@@ -1420,10 +1790,45 @@ define float @test_pow_afn_f32_2.0(float %x) {
}
define float @test_pow_afn_f32_neg2.0(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32_neg2.0
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 -2)
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_neg2.0
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 -2)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_neg2.0
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float -2.000000e+00
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor i1 [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP23]], float [[TMP28]], float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
+; NOPRELINK-NEXT: ret float [[TMP31]]
;
%pow = tail call afn float @_Z3powff(float %x, float -2.0)
ret float %pow
@@ -1440,708 +1845,1931 @@ define <2 x float> @test_pow_afn_v2f32_2.0(<2 x float> %x) {
}
define <2 x float> @test_pow_afn_v2f32_neg2.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg2.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -2))
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg2.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -2))
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg2.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float -2.000000e+00)
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float -2.0, float -2.0>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_plus_minus_2.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_2.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 2, i32 -2>)
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_2.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 2, i32 -2>)
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_2.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float 2.000000e+00, float -2.000000e+00>
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 2.0, float -2.0>)
ret <2 x float> %pow
}
define float @test_pow_afn_f32_3.0(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32_3.0
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 3)
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_3.0
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 3)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_3.0
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float 3.000000e+00
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
+; NOPRELINK-NEXT: ret float [[TMP29]]
;
%pow = tail call afn float @_Z3powff(float %x, float 3.0)
ret float %pow
}
define float @test_pow_afn_f32_neg3.0(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32_neg3.0
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 -3)
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_neg3.0
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 -3)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_neg3.0
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float -3.000000e+00
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor i1 [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP23]], float [[TMP28]], float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
+; NOPRELINK-NEXT: ret float [[TMP31]]
;
%pow = tail call afn float @_Z3powff(float %x, float -3.0)
ret float %pow
}
define <2 x float> @test_pow_afn_v2f32_3.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_3.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 3))
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_3.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 3))
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_3.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float 3.000000e+00)
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP29]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 3.0, float 3.0>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_neg3.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg3.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -3))
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg3.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -3))
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg3.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float -3.000000e+00)
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float -3.0, float -3.0>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_plus_minus_3.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_3.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 3, i32 -3>)
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_3.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 3, i32 -3>)
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_3.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float 3.000000e+00, float -3.000000e+00>
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 3.0, float -3.0>)
ret <2 x float> %pow
}
define float @test_pow_afn_f32_3.99(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32_3.99
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float 0x400FEB8520000000
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; CHECK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
-; CHECK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
-; CHECK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
-; CHECK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
-; CHECK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
-; CHECK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
-; CHECK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; CHECK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
-; CHECK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
-; CHECK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
-; CHECK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
-; CHECK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
-; CHECK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
-; CHECK-NEXT: ret float [[TMP29]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_3.99
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z10__pow_fastff(float [[X]], float 0x400FEB8520000000)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_3.99
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float 0x400FEB8520000000
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
+; NOPRELINK-NEXT: ret float [[TMP29]]
;
%pow = tail call afn float @_Z3powff(float %x, float 0x400FEB8520000000)
ret float %pow
}
define float @test_pow_afn_f32_neg3.99(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32_neg3.99
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float 0xC00FEB8520000000
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
-; CHECK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
-; CHECK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
-; CHECK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
-; CHECK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
-; CHECK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
-; CHECK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
-; CHECK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; CHECK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
-; CHECK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
-; CHECK-NEXT: [[TMP24:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP25:%.*]] = xor i1 [[TMP22]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
-; CHECK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
-; CHECK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP23]], float [[TMP28]], float [[TMP19]]
-; CHECK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
-; CHECK-NEXT: ret float [[TMP31]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_neg3.99
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z10__pow_fastff(float [[X]], float 0xC00FEB8520000000)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_neg3.99
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float 0xC00FEB8520000000
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor i1 [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP23]], float [[TMP28]], float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
+; NOPRELINK-NEXT: ret float [[TMP31]]
;
%pow = tail call afn float @_Z3powff(float %x, float 0xC00FEB8520000000)
ret float %pow
}
define <2 x float> @test_pow_afn_v2f32_3.99(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_3.99
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float 0x400FEB8520000000)
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; CHECK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
-; CHECK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
-; CHECK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
-; CHECK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
-; CHECK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
-; CHECK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; CHECK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
-; CHECK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
-; CHECK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
-; CHECK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
-; CHECK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
-; CHECK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
-; CHECK-NEXT: ret <2 x float> [[TMP29]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_3.99
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 0x400FEB8520000000))
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_3.99
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float 0x400FEB8520000000)
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP29]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 0x400FEB8520000000, float 0x400FEB8520000000>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_neg3.99(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg3.99
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float 0xC00FEB8520000000)
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; CHECK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
-; CHECK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
-; CHECK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
-; CHECK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
-; CHECK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
-; CHECK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; CHECK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
-; CHECK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
-; CHECK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
-; CHECK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
-; CHECK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
-; CHECK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
-; CHECK-NEXT: ret <2 x float> [[TMP31]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg3.99
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 0xC00FEB8520000000))
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg3.99
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float 0xC00FEB8520000000)
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 0xC00FEB8520000000, float 0xC00FEB8520000000>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_plus_minus_3.99(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_3.99
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float 0x400FEB8520000000, float 0xC00FEB8520000000>
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; CHECK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
-; CHECK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
-; CHECK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
-; CHECK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
-; CHECK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
-; CHECK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; CHECK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
-; CHECK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
-; CHECK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
-; CHECK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
-; CHECK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
-; CHECK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
-; CHECK-NEXT: ret <2 x float> [[TMP31]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_3.99
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 0x400FEB8520000000, float 0xC00FEB8520000000>)
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_3.99
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float 0x400FEB8520000000, float 0xC00FEB8520000000>
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 0x400FEB8520000000, float 0xC00FEB8520000000>)
ret <2 x float> %pow
}
define float @test_pow_afn_f32_8.0(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32_8.0
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 8)
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_8.0
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 8)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_8.0
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float 8.000000e+00
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
+; NOPRELINK-NEXT: ret float [[TMP29]]
;
%pow = tail call afn float @_Z3powff(float %x, float 8.0)
ret float %pow
}
define float @test_pow_afn_f32_neg8.0(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32_neg8.0
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 -8)
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_neg8.0
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 -8)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_neg8.0
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float -8.000000e+00
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor i1 [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP23]], float [[TMP28]], float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
+; NOPRELINK-NEXT: ret float [[TMP31]]
;
%pow = tail call afn float @_Z3powff(float %x, float -8.0)
ret float %pow
}
define <2 x float> @test_pow_afn_v2f32_8.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_8.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 8))
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_8.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 8))
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_8.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float 8.000000e+00)
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP29]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 8.0, float 8.0>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_neg8.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg8.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -8))
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg8.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -8))
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg8.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float -8.000000e+00)
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float -8.0, float -8.0>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_plus_minus_8.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_8.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 8, i32 -8>)
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_8.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 8, i32 -8>)
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_8.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float 8.000000e+00, float -8.000000e+00>
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 8.0, float -8.0>)
ret <2 x float> %pow
}
define float @test_pow_afn_f32_12.0(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32_12.0
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 12)
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_12.0
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 12)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_12.0
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float 1.200000e+01
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
+; NOPRELINK-NEXT: ret float [[TMP29]]
;
%pow = tail call afn float @_Z3powff(float %x, float 12.0)
ret float %pow
}
define float @test_pow_afn_f32_neg12.0(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32_neg12.0
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 -12)
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_neg12.0
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 -12)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_neg12.0
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float -1.200000e+01
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor i1 [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP23]], float [[TMP28]], float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
+; NOPRELINK-NEXT: ret float [[TMP31]]
;
%pow = tail call afn float @_Z3powff(float %x, float -12.0)
ret float %pow
}
define <2 x float> @test_pow_afn_v2f32_12.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_12.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 12))
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_12.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 12))
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_12.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float 1.200000e+01)
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP29]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 12.0, float 12.0>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_neg12.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg12.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -12))
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg12.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -12))
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg12.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float -1.200000e+01)
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float -12.0, float -12.0>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_plus_minus_12.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_12.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 12, i32 -12>)
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_12.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 12, i32 -12>)
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_12.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float 1.200000e+01, float -1.200000e+01>
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 12.0, float -12.0>)
ret <2 x float> %pow
}
define float @test_pow_afn_f32_13.0(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32_13.0
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 13)
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_13.0
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 13)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_13.0
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float 1.300000e+01
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
+; NOPRELINK-NEXT: ret float [[TMP29]]
;
%pow = tail call afn float @_Z3powff(float %x, float 13.0)
ret float %pow
}
define float @test_pow_afn_f32_neg13.0(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32_neg13.0
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 -13)
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_neg13.0
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 -13)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_neg13.0
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float -1.300000e+01
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor i1 [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP23]], float [[TMP28]], float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
+; NOPRELINK-NEXT: ret float [[TMP31]]
;
%pow = tail call afn float @_Z3powff(float %x, float -13.0)
ret float %pow
}
define <2 x float> @test_pow_afn_v2f32_13.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_13.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 13))
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_13.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 13))
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_13.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float 1.300000e+01)
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP29]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 13.0, float 13.0>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_neg13.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg13.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -13))
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg13.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -13))
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_neg13.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float -1.300000e+01)
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float -13.0, float -13.0>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_13.0_15.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_13.0_15.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 13, i32 15>)
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_13.0_15.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 13, i32 15>)
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_13.0_15.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float 1.300000e+01, float 1.500000e+01>
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP29]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 13.0, float 15.0>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_13.0_14.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_13.0_14.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 13, i32 14>)
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_13.0_14.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 13, i32 14>)
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_13.0_14.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float 1.300000e+01, float 1.400000e+01>
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP29]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 13.0, float 14.0>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_14.0_16.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_14.0_16.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 14, i32 16>)
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_14.0_16.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 14, i32 16>)
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_14.0_16.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float 1.400000e+01, float 1.600000e+01>
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP24]], <2 x float> [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP26]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP28]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP29]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 14.0, float 16.0>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_plus_minus_13.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_13.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 13, i32 -13>)
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_13.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 13, i32 -13>)
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_13.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float 1.300000e+01, float -1.300000e+01>
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 13.0, float -13.0>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_plus_minus_13.0_minus_14.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_13.0_minus_14.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 -13, i32 -14>)
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_13.0_minus_14.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 -13, i32 -14>)
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_plus_minus_13.0_minus_14.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float -1.300000e+01, float -1.400000e+01>
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq <2 x float> [[TMP20]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or <2 x i1> [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor <2 x i1> [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> [[TMP28]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float -13.0, float -14.0>)
ret <2 x float> %pow
}
define float @test_pow_afn_f32_nnan_x_known_positive(float nofpclass(ninf nnorm nsub) %x, float %y) {
-; CHECK-LABEL: define float @test_pow_afn_f32_nnan_x_known_positive
-; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call nnan afn float @_Z4powrff(float [[X]], float [[Y]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_nnan_x_known_positive
+; PRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan afn float @_Z11__powr_fastff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_nnan_x_known_positive
+; NOPRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select nnan afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul nnan afn float [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une float [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn oeq float [[TMP17]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP19:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan afn une float [[TMP2]], [[TMP19]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp nnan afn oeq float [[TMP21]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn olt float [[TMP21]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP24:%.*]] = xor i1 [[TMP23]], [[TMP20]]
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select nnan afn i1 [[TMP24]], float 0.000000e+00, float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select nnan afn i1 [[TMP22]], float 1.000000e+00, float [[TMP25]]
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select nnan afn i1 [[TMP18]], float [[TMP26]], float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = fcmp nnan afn oeq float [[TMP28]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP31:%.*]] = or i1 [[TMP29]], [[TMP30]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = fcmp nnan afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP33:%.*]] = xor i1 [[TMP30]], [[TMP32]]
+; NOPRELINK-NEXT: [[TMP34:%.*]] = select nnan afn i1 [[TMP33]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP35:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP36:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP34]], float [[TMP35]])
+; NOPRELINK-NEXT: [[TMP37:%.*]] = select nnan afn i1 [[TMP31]], float [[TMP36]], float [[TMP27]]
+; NOPRELINK-NEXT: ret float [[TMP37]]
;
%pow = tail call afn nnan float @_Z3powff(float %x, float %y)
ret float %pow
}
define float @test_pow_afn_f32_nnan_ninf_x_known_positive(float nofpclass(ninf nnorm nsub) %x, float %y) {
-; CHECK-LABEL: define float @test_pow_afn_f32_nnan_ninf_x_known_positive
-; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[X]])
-; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[Y]], [[__LOG2]]
-; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
-; CHECK-NEXT: ret float [[__EXP2]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_nnan_ninf_x_known_positive
+; PRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[X]])
+; PRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[Y]], [[__LOG2]]
+; PRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
+; PRELINK-NEXT: ret float [[__EXP2]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_nnan_ninf_x_known_positive
+; NOPRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan ninf afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan ninf afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp nnan ninf afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select nnan ninf afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = fmul nnan ninf afn float [[TMP2]], [[TMP5]]
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP6]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp nnan ninf afn oeq float [[TMP8]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fmul nnan ninf afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP11:%.*]] = call nnan ninf afn float @llvm.trunc.f32(float [[TMP10]])
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp nnan ninf afn une float [[TMP11]], [[TMP10]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = and i1 [[TMP9]], [[TMP12]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = select nnan ninf afn i1 [[TMP13]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[TMP14]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp nnan ninf afn oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp nnan ninf afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = xor i1 [[TMP16]], [[TMP17]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select nnan ninf afn i1 [[TMP18]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP20:%.*]] = select nnan ninf afn i1 [[TMP13]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP21:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP19]], float [[TMP20]])
+; NOPRELINK-NEXT: [[TMP22:%.*]] = select nnan ninf afn i1 [[TMP16]], float [[TMP21]], float [[TMP15]]
+; NOPRELINK-NEXT: ret float [[TMP22]]
;
%pow = tail call afn nnan ninf float @_Z3powff(float %x, float %y)
ret float %pow
}
define <2 x float> @test_pow_afn_v2f32_nnan_x_known_positive(<2 x float> nofpclass(ninf nnorm nsub) %x, <2 x float> %y) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_nnan_x_known_positive
-; CHECK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call nnan afn <2 x float> @_Z4powrDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_nnan_x_known_positive
+; PRELINK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_nnan_x_known_positive
+; NOPRELINK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select nnan afn <2 x i1> [[TMP3]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul nnan afn <2 x float> [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call nnan afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call nnan afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une <2 x float> [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP8]], <2 x float> [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP17]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP19:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan afn une <2 x float> [[TMP2]], [[TMP19]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP21]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn olt <2 x float> [[TMP21]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = xor <2 x i1> [[TMP23]], [[TMP20]]
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select nnan afn <2 x i1> [[TMP24]], <2 x float> zeroinitializer, <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select nnan afn <2 x i1> [[TMP22]], <2 x float> splat (float 1.000000e+00), <2 x float> [[TMP25]]
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select nnan afn <2 x i1> [[TMP18]], <2 x float> [[TMP26]], <2 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP28]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = or <2 x i1> [[TMP29]], [[TMP30]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = fcmp nnan afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP33:%.*]] = xor <2 x i1> [[TMP30]], [[TMP32]]
+; NOPRELINK-NEXT: [[TMP34:%.*]] = select nnan afn <2 x i1> [[TMP33]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP35:%.*]] = select nnan afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP36:%.*]] = call nnan afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP34]], <2 x float> [[TMP35]])
+; NOPRELINK-NEXT: [[TMP37:%.*]] = select nnan afn <2 x i1> [[TMP31]], <2 x float> [[TMP36]], <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP37]]
;
%pow = tail call afn nnan <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_nnan_ninf_x_known_positive(<2 x float> nofpclass(ninf nnorm nsub) %x, <2 x float> %y) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_nnan_ninf_x_known_positive
-; CHECK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[Y]], [[__LOG2]]
-; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]])
-; CHECK-NEXT: ret <2 x float> [[__EXP2]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_nnan_ninf_x_known_positive
+; PRELINK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[X]])
+; PRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[Y]], [[__LOG2]]
+; PRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]])
+; PRELINK-NEXT: ret <2 x float> [[__EXP2]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_nnan_ninf_x_known_positive
+; NOPRELINK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan ninf afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select nnan ninf afn <2 x i1> [[TMP3]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], [[TMP5]]
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP6]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[TMP8]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP11:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP10]])
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp nnan ninf afn une <2 x float> [[TMP11]], [[TMP10]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = and <2 x i1> [[TMP9]], [[TMP12]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = select nnan ninf afn <2 x i1> [[TMP13]], <2 x float> [[TMP4]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP7]], <2 x float> [[TMP14]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp nnan ninf afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = xor <2 x i1> [[TMP16]], [[TMP17]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select nnan ninf afn <2 x i1> [[TMP18]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP20:%.*]] = select nnan ninf afn <2 x i1> [[TMP13]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP21:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP19]], <2 x float> [[TMP20]])
+; NOPRELINK-NEXT: [[TMP22:%.*]] = select nnan ninf afn <2 x i1> [[TMP16]], <2 x float> [[TMP21]], <2 x float> [[TMP15]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP22]]
;
%pow = tail call afn nnan ninf <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y)
ret <2 x float> %pow
}
define float @test_pow_f32_x_known_positive(float nofpclass(ninf nnorm nsub) %x, float %y) {
-; CHECK-LABEL: define float @test_pow_f32_x_known_positive
-; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32_x_known_positive
+; PRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32_x_known_positive
+; NOPRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y]])
+; NOPRELINK-NEXT: ret float [[POW]]
;
%pow = tail call float @_Z3powff(float %x, float %y)
ret float %pow
}
define float @test_pow_afn_f32_x_known_positive(float nofpclass(ninf nnorm nsub) %x, float %y) {
-; CHECK-LABEL: define float @test_pow_afn_f32_x_known_positive
-; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4powrff(float [[X]], float [[Y]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_x_known_positive
+; PRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_x_known_positive
+; NOPRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.log2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul afn float [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn float @llvm.exp2.f32(float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call afn float @llvm.trunc.f32(float [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une float [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn oeq float [[TMP17]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP19:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une float [[TMP2]], [[TMP19]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[TMP21]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn olt float [[TMP21]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP24:%.*]] = xor i1 [[TMP23]], [[TMP20]]
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP24]], float 0.000000e+00, float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP22]], float 1.000000e+00, float [[TMP25]]
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP18]], float [[TMP26]], float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = fcmp afn oeq float [[TMP28]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP31:%.*]] = or i1 [[TMP29]], [[TMP30]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP33:%.*]] = xor i1 [[TMP30]], [[TMP32]]
+; NOPRELINK-NEXT: [[TMP34:%.*]] = select afn i1 [[TMP33]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP35:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP36:%.*]] = call afn float @llvm.copysign.f32(float [[TMP34]], float [[TMP35]])
+; NOPRELINK-NEXT: [[TMP37:%.*]] = select afn i1 [[TMP31]], float [[TMP36]], float [[TMP27]]
+; NOPRELINK-NEXT: [[TMP38:%.*]] = fcmp afn uno float [[TMP4]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn i1 [[TMP38]], float 0x7FF8000000000000, float [[TMP37]]
+; NOPRELINK-NEXT: ret float [[TMP39]]
;
%pow = tail call afn float @_Z3powff(float %x, float %y)
ret float %pow
}
define <2 x float> @test_pow_v2f32_x_known_positive(<2 x float> nofpclass(ninf nnorm nsub) %x, <2 x float> %y) {
-; CHECK-LABEL: define <2 x float> @test_pow_v2f32_x_known_positive
-; CHECK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z4powrDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_v2f32_x_known_positive
+; PRELINK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z4powrDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_v2f32_x_known_positive
+; NOPRELINK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z3powDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
+; NOPRELINK-NEXT: ret <2 x float> [[POW]]
;
%pow = tail call <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_x_known_positive(<2 x float> nofpclass(ninf nnorm nsub) %x, <2 x float> %y) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_x_known_positive
-; CHECK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_x_known_positive
+; PRELINK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_x_known_positive
+; NOPRELINK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select afn <2 x i1> [[TMP3]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une <2 x float> [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP8]], <2 x float> [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn oeq <2 x float> [[TMP17]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP19:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une <2 x float> [[TMP2]], [[TMP19]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq <2 x float> [[TMP21]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn olt <2 x float> [[TMP21]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = xor <2 x i1> [[TMP23]], [[TMP20]]
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn <2 x i1> [[TMP24]], <2 x float> zeroinitializer, <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> splat (float 1.000000e+00), <2 x float> [[TMP25]]
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP18]], <2 x float> [[TMP26]], <2 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = fcmp afn oeq <2 x float> [[TMP28]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn oeq <2 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = or <2 x i1> [[TMP29]], [[TMP30]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = fcmp afn olt <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP33:%.*]] = xor <2 x i1> [[TMP30]], [[TMP32]]
+; NOPRELINK-NEXT: [[TMP34:%.*]] = select afn <2 x i1> [[TMP33]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP35:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP36:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP34]], <2 x float> [[TMP35]])
+; NOPRELINK-NEXT: [[TMP37:%.*]] = select afn <2 x i1> [[TMP31]], <2 x float> [[TMP36]], <2 x float> [[TMP27]]
+; NOPRELINK-NEXT: [[TMP38:%.*]] = fcmp afn uno <2 x float> [[TMP4]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select afn <2 x i1> [[TMP38]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP37]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP39]]
;
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y)
ret <2 x float> %pow
}
define double @test_pow_afn_f64_nnan_x_known_positive(double nofpclass(ninf nnorm nsub) %x, double %y) {
-; CHECK-LABEL: define double @test_pow_afn_f64_nnan_x_known_positive
-; CHECK-SAME: (double nofpclass(ninf nsub nnorm) [[X:%.*]], double [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call nnan afn double @_Z4powrdd(double [[X]], double [[Y]])
-; CHECK-NEXT: ret double [[POW]]
+; PRELINK-LABEL: define double @test_pow_afn_f64_nnan_x_known_positive
+; PRELINK-SAME: (double nofpclass(ninf nsub nnorm) [[X:%.*]], double [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan afn double @_Z4powrdd(double [[X]], double [[Y]])
+; PRELINK-NEXT: ret double [[POW]]
+;
+; NOPRELINK-LABEL: define double @test_pow_afn_f64_nnan_x_known_positive
+; NOPRELINK-SAME: (double nofpclass(ninf nsub nnorm) [[X:%.*]], double [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call nnan afn double @_Z3powdd(double [[X]], double [[Y]])
+; NOPRELINK-NEXT: ret double [[POW]]
;
%pow = tail call afn nnan double @_Z3powdd(double %x, double %y)
ret double %pow
}
define double @test_pow_afn_f64_nnan_ninf_x_known_positive(double nofpclass(ninf nnorm nsub) %x, double %y) {
-; CHECK-LABEL: define double @test_pow_afn_f64_nnan_ninf_x_known_positive
-; CHECK-SAME: (double nofpclass(ninf nsub nnorm) [[X:%.*]], double [[Y:%.*]]) {
-; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn double @_Z4log2d(double [[X]])
-; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn double [[Y]], [[__LOG2]]
-; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) double @_Z4exp2d(double [[__YLOGX]])
-; CHECK-NEXT: ret double [[__EXP2]]
+; PRELINK-LABEL: define double @test_pow_afn_f64_nnan_ninf_x_known_positive
+; PRELINK-SAME: (double nofpclass(ninf nsub nnorm) [[X:%.*]], double [[Y:%.*]]) {
+; PRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn double @_Z4log2d(double [[X]])
+; PRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn double [[Y]], [[__LOG2]]
+; PRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) double @_Z4exp2d(double [[__YLOGX]])
+; PRELINK-NEXT: ret double [[__EXP2]]
+;
+; NOPRELINK-LABEL: define double @test_pow_afn_f64_nnan_ninf_x_known_positive
+; NOPRELINK-SAME: (double nofpclass(ninf nsub nnorm) [[X:%.*]], double [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call nnan ninf afn double @_Z3powdd(double [[X]], double [[Y]])
+; NOPRELINK-NEXT: ret double [[POW]]
;
%pow = tail call afn nnan ninf double @_Z3powdd(double %x, double %y)
ret double %pow
}
define <2 x double> @test_pow_afn_v2f64_nnan_x_known_positive(<2 x double> nofpclass(ninf nnorm nsub) %x, <2 x double> %y) {
-; CHECK-LABEL: define <2 x double> @test_pow_afn_v2f64_nnan_x_known_positive
-; CHECK-SAME: (<2 x double> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x double> [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call nnan afn <2 x double> @_Z4powrDv2_dS_(<2 x double> [[X]], <2 x double> [[Y]])
-; CHECK-NEXT: ret <2 x double> [[POW]]
+; PRELINK-LABEL: define <2 x double> @test_pow_afn_v2f64_nnan_x_known_positive
+; PRELINK-SAME: (<2 x double> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x double> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan afn <2 x double> @_Z4powrDv2_dS_(<2 x double> [[X]], <2 x double> [[Y]])
+; PRELINK-NEXT: ret <2 x double> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x double> @test_pow_afn_v2f64_nnan_x_known_positive
+; NOPRELINK-SAME: (<2 x double> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x double> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call nnan afn <2 x double> @_Z3powDv2_dS_(<2 x double> [[X]], <2 x double> [[Y]])
+; NOPRELINK-NEXT: ret <2 x double> [[POW]]
;
%pow = tail call afn nnan <2 x double> @_Z3powDv2_dS_(<2 x double> %x, <2 x double> %y)
ret <2 x double> %pow
}
define <2 x double> @test_pow_afn_v2f64_nnan_ninf_x_known_positive(<2 x double> nofpclass(ninf nnorm nsub) %x, <2 x double> %y) {
-; CHECK-LABEL: define <2 x double> @test_pow_afn_v2f64_nnan_ninf_x_known_positive
-; CHECK-SAME: (<2 x double> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x double> [[Y:%.*]]) {
-; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x double> @_Z4log2Dv2_d(<2 x double> [[X]])
-; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x double> [[Y]], [[__LOG2]]
-; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x double> @_Z4exp2Dv2_d(<2 x double> [[__YLOGX]])
-; CHECK-NEXT: ret <2 x double> [[__EXP2]]
+; PRELINK-LABEL: define <2 x double> @test_pow_afn_v2f64_nnan_ninf_x_known_positive
+; PRELINK-SAME: (<2 x double> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x double> [[Y:%.*]]) {
+; PRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x double> @_Z4log2Dv2_d(<2 x double> [[X]])
+; PRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x double> [[Y]], [[__LOG2]]
+; PRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x double> @_Z4exp2Dv2_d(<2 x double> [[__YLOGX]])
+; PRELINK-NEXT: ret <2 x double> [[__EXP2]]
+;
+; NOPRELINK-LABEL: define <2 x double> @test_pow_afn_v2f64_nnan_ninf_x_known_positive
+; NOPRELINK-SAME: (<2 x double> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x double> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call nnan ninf afn <2 x double> @_Z3powDv2_dS_(<2 x double> [[X]], <2 x double> [[Y]])
+; NOPRELINK-NEXT: ret <2 x double> [[POW]]
;
%pow = tail call afn nnan ninf <2 x double> @_Z3powDv2_dS_(<2 x double> %x, <2 x double> %y)
ret <2 x double> %pow
}
define double @test_pow_f64_x_known_positive(double nofpclass(ninf nnorm nsub) %x, double %y) {
-; CHECK-LABEL: define double @test_pow_f64_x_known_positive
-; CHECK-SAME: (double nofpclass(ninf nsub nnorm) [[X:%.*]], double [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call double @_Z4powrdd(double [[X]], double [[Y]])
-; CHECK-NEXT: ret double [[POW]]
+; PRELINK-LABEL: define double @test_pow_f64_x_known_positive
+; PRELINK-SAME: (double nofpclass(ninf nsub nnorm) [[X:%.*]], double [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call double @_Z4powrdd(double [[X]], double [[Y]])
+; PRELINK-NEXT: ret double [[POW]]
+;
+; NOPRELINK-LABEL: define double @test_pow_f64_x_known_positive
+; NOPRELINK-SAME: (double nofpclass(ninf nsub nnorm) [[X:%.*]], double [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call double @_Z3powdd(double [[X]], double [[Y]])
+; NOPRELINK-NEXT: ret double [[POW]]
;
%pow = tail call double @_Z3powdd(double %x, double %y)
ret double %pow
}
define double @test_pow_afn_f64_x_known_positive(double nofpclass(ninf nnorm nsub) %x, double %y) {
-; CHECK-LABEL: define double @test_pow_afn_f64_x_known_positive
-; CHECK-SAME: (double nofpclass(ninf nsub nnorm) [[X:%.*]], double [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn double @_Z4powrdd(double [[X]], double [[Y]])
-; CHECK-NEXT: ret double [[POW]]
+; PRELINK-LABEL: define double @test_pow_afn_f64_x_known_positive
+; PRELINK-SAME: (double nofpclass(ninf nsub nnorm) [[X:%.*]], double [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn double @_Z4powrdd(double [[X]], double [[Y]])
+; PRELINK-NEXT: ret double [[POW]]
+;
+; NOPRELINK-LABEL: define double @test_pow_afn_f64_x_known_positive
+; NOPRELINK-SAME: (double nofpclass(ninf nsub nnorm) [[X:%.*]], double [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn double @_Z3powdd(double [[X]], double [[Y]])
+; NOPRELINK-NEXT: ret double [[POW]]
;
%pow = tail call afn double @_Z3powdd(double %x, double %y)
ret double %pow
}
define <2 x double> @test_pow_v2f64_x_known_positive(<2 x double> nofpclass(ninf nnorm nsub) %x, <2 x double> %y) {
-; CHECK-LABEL: define <2 x double> @test_pow_v2f64_x_known_positive
-; CHECK-SAME: (<2 x double> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x double> [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call <2 x double> @_Z4powrDv2_dS_(<2 x double> [[X]], <2 x double> [[Y]])
-; CHECK-NEXT: ret <2 x double> [[POW]]
+; PRELINK-LABEL: define <2 x double> @test_pow_v2f64_x_known_positive
+; PRELINK-SAME: (<2 x double> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x double> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call <2 x double> @_Z4powrDv2_dS_(<2 x double> [[X]], <2 x double> [[Y]])
+; PRELINK-NEXT: ret <2 x double> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x double> @test_pow_v2f64_x_known_positive
+; NOPRELINK-SAME: (<2 x double> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x double> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call <2 x double> @_Z3powDv2_dS_(<2 x double> [[X]], <2 x double> [[Y]])
+; NOPRELINK-NEXT: ret <2 x double> [[POW]]
;
%pow = tail call <2 x double> @_Z3powDv2_dS_(<2 x double> %x, <2 x double> %y)
ret <2 x double> %pow
}
define <2 x double> @test_pow_afn_v2f64_x_known_positive(<2 x double> nofpclass(ninf nnorm nsub) %x, <2 x double> %y) {
-; CHECK-LABEL: define <2 x double> @test_pow_afn_v2f64_x_known_positive
-; CHECK-SAME: (<2 x double> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x double> [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x double> @_Z4powrDv2_dS_(<2 x double> [[X]], <2 x double> [[Y]])
-; CHECK-NEXT: ret <2 x double> [[POW]]
+; PRELINK-LABEL: define <2 x double> @test_pow_afn_v2f64_x_known_positive
+; PRELINK-SAME: (<2 x double> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x double> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x double> @_Z4powrDv2_dS_(<2 x double> [[X]], <2 x double> [[Y]])
+; PRELINK-NEXT: ret <2 x double> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x double> @test_pow_afn_v2f64_x_known_positive
+; NOPRELINK-SAME: (<2 x double> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x double> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x double> @_Z3powDv2_dS_(<2 x double> [[X]], <2 x double> [[Y]])
+; NOPRELINK-NEXT: ret <2 x double> [[POW]]
;
%pow = tail call afn <2 x double> @_Z3powDv2_dS_(<2 x double> %x, <2 x double> %y)
ret <2 x double> %pow
}
define half @test_pow_afn_f16_nnan_x_known_positive(half nofpclass(ninf nnorm nsub) %x, half %y) {
-; CHECK-LABEL: define half @test_pow_afn_f16_nnan_x_known_positive
-; CHECK-SAME: (half nofpclass(ninf nsub nnorm) [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call nnan afn half @_Z4powrDhDh(half [[X]], half [[Y]])
-; CHECK-NEXT: ret half [[POW]]
+; PRELINK-LABEL: define half @test_pow_afn_f16_nnan_x_known_positive
+; PRELINK-SAME: (half nofpclass(ninf nsub nnorm) [[X:%.*]], half [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan afn half @_Z4powrDhDh(half [[X]], half [[Y]])
+; PRELINK-NEXT: ret half [[POW]]
+;
+; NOPRELINK-LABEL: define half @test_pow_afn_f16_nnan_x_known_positive
+; NOPRELINK-SAME: (half nofpclass(ninf nsub nnorm) [[X:%.*]], half [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call nnan afn half @_Z3powDhDh(half [[X]], half [[Y]])
+; NOPRELINK-NEXT: ret half [[POW]]
;
%pow = tail call afn nnan half @_Z3powDhDh(half %x, half %y)
ret half %pow
}
define half @test_pow_afn_f16_nnan_ninf_x_known_positive(half nofpclass(ninf nnorm nsub) %x, half %y) {
-; CHECK-LABEL: define half @test_pow_afn_f16_nnan_ninf_x_known_positive
-; CHECK-SAME: (half nofpclass(ninf nsub nnorm) [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn half @llvm.log2.f16(half [[X]])
-; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn half [[Y]], [[__LOG2]]
-; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) half @llvm.exp2.f16(half [[__YLOGX]])
-; CHECK-NEXT: ret half [[__EXP2]]
+; PRELINK-LABEL: define half @test_pow_afn_f16_nnan_ninf_x_known_positive
+; PRELINK-SAME: (half nofpclass(ninf nsub nnorm) [[X:%.*]], half [[Y:%.*]]) {
+; PRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn half @llvm.log2.f16(half [[X]])
+; PRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn half [[Y]], [[__LOG2]]
+; PRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) half @llvm.exp2.f16(half [[__YLOGX]])
+; PRELINK-NEXT: ret half [[__EXP2]]
+;
+; NOPRELINK-LABEL: define half @test_pow_afn_f16_nnan_ninf_x_known_positive
+; NOPRELINK-SAME: (half nofpclass(ninf nsub nnorm) [[X:%.*]], half [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call nnan ninf afn half @_Z3powDhDh(half [[X]], half [[Y]])
+; NOPRELINK-NEXT: ret half [[POW]]
;
%pow = tail call afn nnan ninf half @_Z3powDhDh(half %x, half %y)
ret half %pow
}
define <2 x half> @test_pow_afn_v2f16_nnan_x_known_positive(<2 x half> nofpclass(ninf nnorm nsub) %x, <2 x half> %y) {
-; CHECK-LABEL: define <2 x half> @test_pow_afn_v2f16_nnan_x_known_positive
-; CHECK-SAME: (<2 x half> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x half> [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call nnan afn <2 x half> @_Z4powrDv2_DhS_(<2 x half> [[X]], <2 x half> [[Y]])
-; CHECK-NEXT: ret <2 x half> [[POW]]
+; PRELINK-LABEL: define <2 x half> @test_pow_afn_v2f16_nnan_x_known_positive
+; PRELINK-SAME: (<2 x half> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x half> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan afn <2 x half> @_Z4powrDv2_DhS_(<2 x half> [[X]], <2 x half> [[Y]])
+; PRELINK-NEXT: ret <2 x half> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x half> @test_pow_afn_v2f16_nnan_x_known_positive
+; NOPRELINK-SAME: (<2 x half> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x half> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call nnan afn <2 x half> @_Z3powDv2_DhS_(<2 x half> [[X]], <2 x half> [[Y]])
+; NOPRELINK-NEXT: ret <2 x half> [[POW]]
;
%pow = tail call afn nnan <2 x half> @_Z3powDv2_DhS_(<2 x half> %x, <2 x half> %y)
ret <2 x half> %pow
}
define <2 x half> @test_pow_afn_v2f16_nnan_ninf_x_known_positive(<2 x half> nofpclass(ninf nnorm nsub) %x, <2 x half> %y) {
-; CHECK-LABEL: define <2 x half> @test_pow_afn_v2f16_nnan_ninf_x_known_positive
-; CHECK-SAME: (<2 x half> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x half> [[Y:%.*]]) {
-; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x half> @llvm.log2.v2f16(<2 x half> [[X]])
-; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x half> [[Y]], [[__LOG2]]
-; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x half> @llvm.exp2.v2f16(<2 x half> [[__YLOGX]])
-; CHECK-NEXT: ret <2 x half> [[__EXP2]]
+; PRELINK-LABEL: define <2 x half> @test_pow_afn_v2f16_nnan_ninf_x_known_positive
+; PRELINK-SAME: (<2 x half> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x half> [[Y:%.*]]) {
+; PRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x half> @llvm.log2.v2f16(<2 x half> [[X]])
+; PRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x half> [[Y]], [[__LOG2]]
+; PRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x half> @llvm.exp2.v2f16(<2 x half> [[__YLOGX]])
+; PRELINK-NEXT: ret <2 x half> [[__EXP2]]
+;
+; NOPRELINK-LABEL: define <2 x half> @test_pow_afn_v2f16_nnan_ninf_x_known_positive
+; NOPRELINK-SAME: (<2 x half> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x half> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call nnan ninf afn <2 x half> @_Z3powDv2_DhS_(<2 x half> [[X]], <2 x half> [[Y]])
+; NOPRELINK-NEXT: ret <2 x half> [[POW]]
;
%pow = tail call afn nnan ninf <2 x half> @_Z3powDv2_DhS_(<2 x half> %x, <2 x half> %y)
ret <2 x half> %pow
}
define half @test_pow_f16_x_known_positive(half nofpclass(ninf nnorm nsub) %x, half %y) {
-; CHECK-LABEL: define half @test_pow_f16_x_known_positive
-; CHECK-SAME: (half nofpclass(ninf nsub nnorm) [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call half @_Z4powrDhDh(half [[X]], half [[Y]])
-; CHECK-NEXT: ret half [[POW]]
+; PRELINK-LABEL: define half @test_pow_f16_x_known_positive
+; PRELINK-SAME: (half nofpclass(ninf nsub nnorm) [[X:%.*]], half [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call half @_Z4powrDhDh(half [[X]], half [[Y]])
+; PRELINK-NEXT: ret half [[POW]]
+;
+; NOPRELINK-LABEL: define half @test_pow_f16_x_known_positive
+; NOPRELINK-SAME: (half nofpclass(ninf nsub nnorm) [[X:%.*]], half [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call half @_Z3powDhDh(half [[X]], half [[Y]])
+; NOPRELINK-NEXT: ret half [[POW]]
;
%pow = tail call half @_Z3powDhDh(half %x, half %y)
ret half %pow
}
define half @test_pow_afn_f16_x_known_positive(half nofpclass(ninf nnorm nsub) %x, half %y) {
-; CHECK-LABEL: define half @test_pow_afn_f16_x_known_positive
-; CHECK-SAME: (half nofpclass(ninf nsub nnorm) [[X:%.*]], half [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn half @_Z4powrDhDh(half [[X]], half [[Y]])
-; CHECK-NEXT: ret half [[POW]]
+; PRELINK-LABEL: define half @test_pow_afn_f16_x_known_positive
+; PRELINK-SAME: (half nofpclass(ninf nsub nnorm) [[X:%.*]], half [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn half @_Z4powrDhDh(half [[X]], half [[Y]])
+; PRELINK-NEXT: ret half [[POW]]
+;
+; NOPRELINK-LABEL: define half @test_pow_afn_f16_x_known_positive
+; NOPRELINK-SAME: (half nofpclass(ninf nsub nnorm) [[X:%.*]], half [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn half @_Z3powDhDh(half [[X]], half [[Y]])
+; NOPRELINK-NEXT: ret half [[POW]]
;
%pow = tail call afn half @_Z3powDhDh(half %x, half %y)
ret half %pow
}
define <2 x half> @test_pow_v2f16_x_known_positive(<2 x half> nofpclass(ninf nnorm nsub) %x, <2 x half> %y) {
-; CHECK-LABEL: define <2 x half> @test_pow_v2f16_x_known_positive
-; CHECK-SAME: (<2 x half> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x half> [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call <2 x half> @_Z4powrDv2_DhS_(<2 x half> [[X]], <2 x half> [[Y]])
-; CHECK-NEXT: ret <2 x half> [[POW]]
+; PRELINK-LABEL: define <2 x half> @test_pow_v2f16_x_known_positive
+; PRELINK-SAME: (<2 x half> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x half> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call <2 x half> @_Z4powrDv2_DhS_(<2 x half> [[X]], <2 x half> [[Y]])
+; PRELINK-NEXT: ret <2 x half> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x half> @test_pow_v2f16_x_known_positive
+; NOPRELINK-SAME: (<2 x half> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x half> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call <2 x half> @_Z3powDv2_DhS_(<2 x half> [[X]], <2 x half> [[Y]])
+; NOPRELINK-NEXT: ret <2 x half> [[POW]]
;
%pow = tail call <2 x half> @_Z3powDv2_DhS_(<2 x half> %x, <2 x half> %y)
ret <2 x half> %pow
}
define <2 x half> @test_pow_afn_v2f16_x_known_positive(<2 x half> nofpclass(ninf nnorm nsub) %x, <2 x half> %y) {
-; CHECK-LABEL: define <2 x half> @test_pow_afn_v2f16_x_known_positive
-; CHECK-SAME: (<2 x half> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x half> [[Y:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x half> @_Z4powrDv2_DhS_(<2 x half> [[X]], <2 x half> [[Y]])
-; CHECK-NEXT: ret <2 x half> [[POW]]
+; PRELINK-LABEL: define <2 x half> @test_pow_afn_v2f16_x_known_positive
+; PRELINK-SAME: (<2 x half> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x half> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x half> @_Z4powrDv2_DhS_(<2 x half> [[X]], <2 x half> [[Y]])
+; PRELINK-NEXT: ret <2 x half> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x half> @test_pow_afn_v2f16_x_known_positive
+; NOPRELINK-SAME: (<2 x half> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x half> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x half> @_Z3powDv2_DhS_(<2 x half> [[X]], <2 x half> [[Y]])
+; NOPRELINK-NEXT: ret <2 x half> [[POW]]
;
%pow = tail call afn <2 x half> @_Z3powDv2_DhS_(<2 x half> %x, <2 x half> %y)
ret <2 x half> %pow
@@ -2195,50 +3823,75 @@ define float @test_pow_f32__y_2(float %x) {
}
define float @test_pow_f32__y_n2(float %x) {
-; CHECK-LABEL: define float @test_pow_f32__y_n2
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 -2)
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32__y_n2
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 -2)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32__y_n2
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float -2.000000e+00)
+; NOPRELINK-NEXT: ret float [[POW]]
;
%pow = tail call float @_Z3powff(float %x, float -2.0)
ret float %pow
}
define float @test_pow_f32__y_half(float %x) {
-; CHECK-LABEL: define float @test_pow_f32__y_half
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[__POW2SQRT:%.*]] = call float @_Z4sqrtf(float [[X]])
-; CHECK-NEXT: ret float [[__POW2SQRT]]
+; PRELINK-LABEL: define float @test_pow_f32__y_half
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[__POW2SQRT:%.*]] = call float @_Z4sqrtf(float [[X]])
+; PRELINK-NEXT: ret float [[__POW2SQRT]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32__y_half
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float 5.000000e-01)
+; NOPRELINK-NEXT: ret float [[POW]]
;
%pow = tail call float @_Z3powff(float %x, float 0.5)
ret float %pow
}
define float @test_pow_f32__y_neg_half(float %x) {
-; CHECK-LABEL: define float @test_pow_f32__y_neg_half
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[__POW2RSQRT:%.*]] = call float @_Z5rsqrtf(float [[X]])
-; CHECK-NEXT: ret float [[__POW2RSQRT]]
+; PRELINK-LABEL: define float @test_pow_f32__y_neg_half
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[__POW2RSQRT:%.*]] = call float @_Z5rsqrtf(float [[X]])
+; PRELINK-NEXT: ret float [[__POW2RSQRT]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32__y_neg_half
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float -5.000000e-01)
+; NOPRELINK-NEXT: ret float [[POW]]
;
%pow = tail call float @_Z3powff(float %x, float -0.5)
ret float %pow
}
define float @test_pow_f32__y_3(float %x) {
-; CHECK-LABEL: define float @test_pow_f32__y_3
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 3)
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32__y_3
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 3)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32__y_3
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float 3.000000e+00)
+; NOPRELINK-NEXT: ret float [[POW]]
;
%pow = tail call float @_Z3powff(float %x, float 3.0)
ret float %pow
}
define float @test_pow_f32__y_n3(float %x) {
-; CHECK-LABEL: define float @test_pow_f32__y_n3
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 -3)
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32__y_n3
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 -3)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32__y_n3
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float -3.000000e+00)
+; NOPRELINK-NEXT: ret float [[POW]]
;
%pow = tail call float @_Z3powff(float %x, float -3.0)
ret float %pow
@@ -2312,50 +3965,75 @@ define <2 x float> @test_pow_v2f32__y_2(<2 x float> %x) {
}
define <2 x float> @test_pow_v2f32__y_n2(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_v2f32__y_n2
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -2))
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_v2f32__y_n2
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -2))
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_v2f32__y_n2
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z3powDv2_fS_(<2 x float> [[X]], <2 x float> splat (float -2.000000e+00))
+; NOPRELINK-NEXT: ret <2 x float> [[POW]]
;
%pow = tail call <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float -2.0, float -2.0>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_v2f32__y_half(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_v2f32__y_half
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[__POW2SQRT:%.*]] = call <2 x float> @_Z4sqrtDv2_f(<2 x float> [[X]])
-; CHECK-NEXT: ret <2 x float> [[__POW2SQRT]]
+; PRELINK-LABEL: define <2 x float> @test_pow_v2f32__y_half
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[__POW2SQRT:%.*]] = call <2 x float> @_Z4sqrtDv2_f(<2 x float> [[X]])
+; PRELINK-NEXT: ret <2 x float> [[__POW2SQRT]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_v2f32__y_half
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z3powDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 5.000000e-01))
+; NOPRELINK-NEXT: ret <2 x float> [[POW]]
;
%pow = tail call <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 0.5, float 0.5>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_v2f32__y_neg_half(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_v2f32__y_neg_half
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[__POW2RSQRT:%.*]] = call <2 x float> @_Z5rsqrtDv2_f(<2 x float> [[X]])
-; CHECK-NEXT: ret <2 x float> [[__POW2RSQRT]]
+; PRELINK-LABEL: define <2 x float> @test_pow_v2f32__y_neg_half
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[__POW2RSQRT:%.*]] = call <2 x float> @_Z5rsqrtDv2_f(<2 x float> [[X]])
+; PRELINK-NEXT: ret <2 x float> [[__POW2RSQRT]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_v2f32__y_neg_half
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z3powDv2_fS_(<2 x float> [[X]], <2 x float> splat (float -5.000000e-01))
+; NOPRELINK-NEXT: ret <2 x float> [[POW]]
;
%pow = tail call <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float -0.5, float -0.5>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_v2f32__y_3(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_v2f32__y_3
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 3))
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_v2f32__y_3
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 3))
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_v2f32__y_3
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z3powDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 3.000000e+00))
+; NOPRELINK-NEXT: ret <2 x float> [[POW]]
;
%pow = tail call <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 3.0, float 3.0>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_v2f32__y_n3(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_v2f32__y_n3
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -3))
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_v2f32__y_n3
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -3))
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_v2f32__y_n3
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z3powDv2_fS_(<2 x float> [[X]], <2 x float> splat (float -3.000000e+00))
+; NOPRELINK-NEXT: ret <2 x float> [[POW]]
;
%pow = tail call <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float -3.0,float -3.0>)
ret <2 x float> %pow
@@ -2420,32 +4098,49 @@ define float @test_pow_f32__known_positive__y_2(float nofpclass(ninf nnorm nsub)
}
define float @test_pow_f32__known_positive__y_half(float nofpclass(ninf nnorm nsub) %x) {
-; CHECK-LABEL: define float @test_pow_f32__known_positive__y_half
-; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]]) {
-; CHECK-NEXT: [[__POW2SQRT:%.*]] = call float @_Z4sqrtf(float [[X]])
-; CHECK-NEXT: ret float [[__POW2SQRT]]
+; PRELINK-LABEL: define float @test_pow_f32__known_positive__y_half
+; PRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]]) {
+; PRELINK-NEXT: [[__POW2SQRT:%.*]] = call float @_Z4sqrtf(float [[X]])
+; PRELINK-NEXT: ret float [[__POW2SQRT]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32__known_positive__y_half
+; NOPRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float 5.000000e-01)
+; NOPRELINK-NEXT: ret float [[POW]]
;
%pow = tail call float @_Z3powff(float %x, float 0.5)
ret float %pow
}
define float @test_pow_f32__known_positive__y_neghalf(float nofpclass(ninf nnorm nsub) %x) {
-; CHECK-LABEL: define float @test_pow_f32__known_positive__y_neghalf
-; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]]) {
-; CHECK-NEXT: [[__POW2RSQRT:%.*]] = call float @_Z5rsqrtf(float [[X]])
-; CHECK-NEXT: ret float [[__POW2RSQRT]]
+; PRELINK-LABEL: define float @test_pow_f32__known_positive__y_neghalf
+; PRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]]) {
+; PRELINK-NEXT: [[__POW2RSQRT:%.*]] = call float @_Z5rsqrtf(float [[X]])
+; PRELINK-NEXT: ret float [[__POW2RSQRT]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32__known_positive__y_neghalf
+; NOPRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float -5.000000e-01)
+; NOPRELINK-NEXT: ret float [[POW]]
;
%pow = tail call float @_Z3powff(float %x, float -0.5)
ret float %pow
}
define float @test_pow_f32_x_assumed_oge_0(float %x, float %y) {
-; CHECK-LABEL: define float @test_pow_f32_x_assumed_oge_0
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[X_OGE_ZERO:%.*]] = fcmp oge float [[X]], 0.000000e+00
-; CHECK-NEXT: call void @llvm.assume(i1 [[X_OGE_ZERO]])
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32_x_assumed_oge_0
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[X_OGE_ZERO:%.*]] = fcmp oge float [[X]], 0.000000e+00
+; PRELINK-NEXT: call void @llvm.assume(i1 [[X_OGE_ZERO]])
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32_x_assumed_oge_0
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[X_OGE_ZERO:%.*]] = fcmp oge float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: call void @llvm.assume(i1 [[X_OGE_ZERO]])
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y]])
+; NOPRELINK-NEXT: ret float [[POW]]
;
%x.oge.zero = fcmp oge float %x, 0.0
call void @llvm.assume(i1 %x.oge.zero)
@@ -2454,12 +4149,19 @@ define float @test_pow_f32_x_assumed_oge_0(float %x, float %y) {
}
define float @test_pow_f32_x_assumed_ogt_0(float %x, float %y) {
-; CHECK-LABEL: define float @test_pow_f32_x_assumed_ogt_0
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[X_OGE_ZERO:%.*]] = fcmp ogt float [[X]], 0.000000e+00
-; CHECK-NEXT: call void @llvm.assume(i1 [[X_OGE_ZERO]])
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32_x_assumed_ogt_0
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[X_OGE_ZERO:%.*]] = fcmp ogt float [[X]], 0.000000e+00
+; PRELINK-NEXT: call void @llvm.assume(i1 [[X_OGE_ZERO]])
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32_x_assumed_ogt_0
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[X_OGE_ZERO:%.*]] = fcmp ogt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: call void @llvm.assume(i1 [[X_OGE_ZERO]])
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y]])
+; NOPRELINK-NEXT: ret float [[POW]]
;
%x.oge.zero = fcmp ogt float %x, 0.0
call void @llvm.assume(i1 %x.oge.zero)
@@ -2468,12 +4170,19 @@ define float @test_pow_f32_x_assumed_ogt_0(float %x, float %y) {
}
define float @test_pow_f32_x_assumed_uge_0(float %x, float %y) {
-; CHECK-LABEL: define float @test_pow_f32_x_assumed_uge_0
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[X_UGE_ZERO:%.*]] = fcmp uge float [[X]], 0.000000e+00
-; CHECK-NEXT: call void @llvm.assume(i1 [[X_UGE_ZERO]])
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32_x_assumed_uge_0
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[X_UGE_ZERO:%.*]] = fcmp uge float [[X]], 0.000000e+00
+; PRELINK-NEXT: call void @llvm.assume(i1 [[X_UGE_ZERO]])
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32_x_assumed_uge_0
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[X_UGE_ZERO:%.*]] = fcmp uge float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: call void @llvm.assume(i1 [[X_UGE_ZERO]])
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y]])
+; NOPRELINK-NEXT: ret float [[POW]]
;
%x.uge.zero = fcmp uge float %x, 0.0
call void @llvm.assume(i1 %x.uge.zero)
@@ -2482,12 +4191,19 @@ define float @test_pow_f32_x_assumed_uge_0(float %x, float %y) {
}
define float @test_pow_f32_x_assumed_ugt_0(float %x, float %y) {
-; CHECK-LABEL: define float @test_pow_f32_x_assumed_ugt_0
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[X_UGT_ZERO:%.*]] = fcmp ugt float [[X]], 0.000000e+00
-; CHECK-NEXT: call void @llvm.assume(i1 [[X_UGT_ZERO]])
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32_x_assumed_ugt_0
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[X_UGT_ZERO:%.*]] = fcmp ugt float [[X]], 0.000000e+00
+; PRELINK-NEXT: call void @llvm.assume(i1 [[X_UGT_ZERO]])
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32_x_assumed_ugt_0
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[X_UGT_ZERO:%.*]] = fcmp ugt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: call void @llvm.assume(i1 [[X_UGT_ZERO]])
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y]])
+; NOPRELINK-NEXT: ret float [[POW]]
;
%x.ugt.zero = fcmp ugt float %x, 0.0
call void @llvm.assume(i1 %x.ugt.zero)
@@ -2496,20 +4212,70 @@ define float @test_pow_f32_x_assumed_ugt_0(float %x, float %y) {
}
define float @test_pow_afn_f32__y_poison(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32__y_poison
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 poison)
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32__y_poison
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 poison)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32__y_poison
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call afn float @llvm.log2.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.exp2.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.copysign.f32(float [[TMP3]], float [[X]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp afn oeq float [[TMP5]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = or i1 [[TMP6]], [[TMP7]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.copysign.f32(float [[TMP9]], float [[X]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn i1 [[TMP8]], float [[TMP10]], float [[TMP4]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float 0x7FF8000000000000, float [[TMP11]]
+; NOPRELINK-NEXT: ret float [[TMP13]]
;
%pow = tail call afn float @_Z3powff(float %x, float poison)
ret float %pow
}
define float @test_pow_afn_f32__y_3(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32__y_3
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 3)
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32__y_3
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 3)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32__y_3
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float 3.000000e+00
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
+; NOPRELINK-NEXT: ret float [[TMP29]]
;
%pow = tail call afn float @_Z3powff(float %x, float 3.0)
ret float %pow
@@ -2527,10 +4293,43 @@ define float @test_pow_afn_f32_nnan_ninf__y_3(float %x) {
}
define float @test_pow_afn_f32__y_4(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32__y_4
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 4)
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32__y_4
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 4)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32__y_4
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float 4.000000e+00
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
+; NOPRELINK-NEXT: ret float [[TMP29]]
;
%pow = tail call afn float @_Z3powff(float %x, float 4.0)
ret float %pow
@@ -2548,43 +4347,81 @@ define float @test_pow_afn_f32_nnan_ninf__y_4(float %x) {
}
define float @test_pow_afn_f32_nnan_ninf__y_4_5(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32_nnan_ninf__y_4_5
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp nnan ninf afn oeq float [[X]], 1.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select nnan ninf afn i1 [[TMP1]], float 1.000000e+00, float 4.500000e+00
-; CHECK-NEXT: [[TMP3:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul nnan ninf afn float [[TMP2]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = call nnan ninf afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp nnan ninf afn oeq float [[TMP7]], [[TMP2]]
-; CHECK-NEXT: [[TMP9:%.*]] = fmul nnan ninf afn float [[TMP2]], 5.000000e-01
-; CHECK-NEXT: [[TMP10:%.*]] = call nnan ninf afn float @llvm.trunc.f32(float [[TMP9]])
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp nnan ninf afn une float [[TMP10]], [[TMP9]]
-; CHECK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
-; CHECK-NEXT: [[TMP13:%.*]] = select nnan ninf afn i1 [[TMP12]], float [[X]], float 1.000000e+00
-; CHECK-NEXT: [[TMP14:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
-; CHECK-NEXT: [[TMP15:%.*]] = call nnan ninf afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP16:%.*]] = fcmp nnan ninf afn une float [[TMP15]], [[TMP2]]
-; CHECK-NEXT: [[TMP17:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
-; CHECK-NEXT: [[TMP19:%.*]] = select nnan ninf afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
-; CHECK-NEXT: [[TMP20:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP21:%.*]] = select nnan ninf afn i1 [[TMP20]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP22:%.*]] = select nnan ninf afn i1 [[TMP12]], float [[X]], float 0.000000e+00
-; CHECK-NEXT: [[TMP23:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP21]], float [[TMP22]])
-; CHECK-NEXT: [[TMP24:%.*]] = select nnan ninf afn i1 [[TMP20]], float [[TMP23]], float [[TMP19]]
-; CHECK-NEXT: ret float [[TMP24]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_nnan_ninf__y_4_5
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan ninf afn float @_Z10__pow_fastff(float [[X]], float 4.500000e+00)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_nnan_ninf__y_4_5
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan ninf afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan ninf afn i1 [[TMP1]], float 1.000000e+00, float 4.500000e+00
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul nnan ninf afn float [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call nnan ninf afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp nnan ninf afn oeq float [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan ninf afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call nnan ninf afn float @llvm.trunc.f32(float [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp nnan ninf afn une float [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select nnan ninf afn i1 [[TMP12]], float [[X]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call nnan ninf afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp nnan ninf afn une float [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select nnan ninf afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan ninf afn i1 [[TMP20]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP22:%.*]] = select nnan ninf afn i1 [[TMP12]], float [[X]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP21]], float [[TMP22]])
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select nnan ninf afn i1 [[TMP20]], float [[TMP23]], float [[TMP19]]
+; NOPRELINK-NEXT: ret float [[TMP24]]
;
%pow = tail call afn nnan ninf float @_Z3powff(float %x, float 4.5)
ret float %pow
}
define float @test_pow_afn_f32__y_5(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32__y_5
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 5)
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32__y_5
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 5)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32__y_5
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float 5.000000e+00
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call afn float @llvm.copysign.f32(float [[TMP24]], float [[TMP25]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP23]], float [[TMP26]], float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP28]], float 0x7FF8000000000000, float [[TMP27]]
+; NOPRELINK-NEXT: ret float [[TMP29]]
;
%pow = tail call afn float @_Z3powff(float %x, float 5.0)
ret float %pow
@@ -2603,10 +4440,45 @@ define float @test_pow_afn_f32_nnan_ninf__y_5(float %x) {
}
define float @test_pow_afn_f32__y_neg5(float %x) {
-; CHECK-LABEL: define float @test_pow_afn_f32__y_neg5
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 -5)
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32__y_neg5
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 -5)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32__y_neg5
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float -5.000000e+00
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.trunc.f32(float [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn une float [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and i1 [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[X]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp afn une float [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn oeq float [[TMP20]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = or i1 [[TMP21]], [[TMP22]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP25:%.*]] = xor i1 [[TMP22]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP12]], float [[X]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP23]], float [[TMP28]], float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
+; NOPRELINK-NEXT: ret float [[TMP31]]
;
%pow = tail call afn float @_Z3powff(float %x, float -5.0)
ret float %pow
@@ -2670,66 +4542,76 @@ define <2 x float> @test_pow_afn_v2f32_nnan_ninf__y_4(<2 x float> %x) {
}
define <2 x float> @test_pow_afn_v2f32_nnan_ninf__y_4_5(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_nnan_ninf__y_4_5
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = select nnan ninf afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float 4.500000e+00)
-; CHECK-NEXT: [[TMP3:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; CHECK-NEXT: [[TMP9:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
-; CHECK-NEXT: [[TMP10:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp nnan ninf afn une <2 x float> [[TMP10]], [[TMP9]]
-; CHECK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
-; CHECK-NEXT: [[TMP13:%.*]] = select nnan ninf afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP14:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
-; CHECK-NEXT: [[TMP15:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP16:%.*]] = fcmp nnan ninf afn une <2 x float> [[TMP15]], [[TMP2]]
-; CHECK-NEXT: [[TMP17:%.*]] = fcmp nnan ninf afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; CHECK-NEXT: [[TMP19:%.*]] = select nnan ninf afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
-; CHECK-NEXT: [[TMP20:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP21:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP22:%.*]] = select nnan ninf afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
-; CHECK-NEXT: [[TMP23:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP21]], <2 x float> [[TMP22]])
-; CHECK-NEXT: [[TMP24:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> [[TMP23]], <2 x float> [[TMP19]]
-; CHECK-NEXT: ret <2 x float> [[TMP24]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_nnan_ninf__y_4_5
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan ninf afn <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 4.500000e+00))
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_nnan_ninf__y_4_5
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan ninf afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> splat (float 4.500000e+00)
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp nnan ninf afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select nnan ninf afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp nnan ninf afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp nnan ninf afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select nnan ninf afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = select nnan ninf afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP21]], <2 x float> [[TMP22]])
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> [[TMP23]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP24]]
;
%pow = tail call afn nnan ninf <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 4.5, float 4.5>)
ret <2 x float> %pow
}
define <2 x float> @test_pow_afn_v2f32_nnan_ninf__y_4_5_undef(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_nnan_ninf__y_4_5_undef
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP2:%.*]] = select nnan ninf afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float 4.500000e+00, float poison>
-; CHECK-NEXT: [[TMP3:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[TMP7]], [[TMP2]]
-; CHECK-NEXT: [[TMP9:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
-; CHECK-NEXT: [[TMP10:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp nnan ninf afn une <2 x float> [[TMP10]], [[TMP9]]
-; CHECK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
-; CHECK-NEXT: [[TMP13:%.*]] = select nnan ninf afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP14:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
-; CHECK-NEXT: [[TMP15:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP16:%.*]] = fcmp nnan ninf afn une <2 x float> [[TMP15]], [[TMP2]]
-; CHECK-NEXT: [[TMP17:%.*]] = fcmp nnan ninf afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
-; CHECK-NEXT: [[TMP19:%.*]] = select nnan ninf afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
-; CHECK-NEXT: [[TMP20:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP21:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP22:%.*]] = select nnan ninf afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
-; CHECK-NEXT: [[TMP23:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP21]], <2 x float> [[TMP22]])
-; CHECK-NEXT: [[TMP24:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> [[TMP23]], <2 x float> [[TMP19]]
-; CHECK-NEXT: ret <2 x float> [[TMP24]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_nnan_ninf__y_4_5_undef
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan ninf afn <2 x float> @_Z10__pow_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 4.500000e+00, float poison>)
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_nnan_ninf__y_4_5_undef
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan ninf afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> <float 4.500000e+00, float poison>
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[TMP7]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fmul nnan ninf afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP9]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp nnan ninf afn une <2 x float> [[TMP10]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = and <2 x i1> [[TMP8]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select nnan ninf afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = call nnan ninf afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp nnan ninf afn une <2 x float> [[TMP15]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp nnan ninf afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select nnan ninf afn <2 x i1> [[TMP18]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP22:%.*]] = select nnan ninf afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP21]], <2 x float> [[TMP22]])
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> [[TMP23]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP24]]
;
%pow = tail call afn nnan ninf <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 4.5, float poison>)
ret <2 x float> %pow
@@ -2773,10 +4655,15 @@ define float @test_pow_afn_f32_nnan_ninf__y_5_known_positive_with_ninf_flag(floa
}
define double @test_pow_afn_f64__y_3(double %x) {
-; CHECK-LABEL: define double @test_pow_afn_f64__y_3
-; CHECK-SAME: (double [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn double @_Z4powndi(double [[X]], i32 3)
-; CHECK-NEXT: ret double [[POW]]
+; PRELINK-LABEL: define double @test_pow_afn_f64__y_3
+; PRELINK-SAME: (double [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn double @_Z4powndi(double [[X]], i32 3)
+; PRELINK-NEXT: ret double [[POW]]
+;
+; NOPRELINK-LABEL: define double @test_pow_afn_f64__y_3
+; NOPRELINK-SAME: (double [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn double @_Z3powdd(double [[X]], double 3.000000e+00)
+; NOPRELINK-NEXT: ret double [[POW]]
;
%pow = tail call afn double @_Z3powdd(double %x, double 3.0)
ret double %pow
@@ -2794,10 +4681,15 @@ define double @test_pow_afn_f64_nnan_ninf__y_3(double %x) {
}
define double @test_pow_afn_f64__y_4(double %x) {
-; CHECK-LABEL: define double @test_pow_afn_f64__y_4
-; CHECK-SAME: (double [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn double @_Z4powndi(double [[X]], i32 4)
-; CHECK-NEXT: ret double [[POW]]
+; PRELINK-LABEL: define double @test_pow_afn_f64__y_4
+; PRELINK-SAME: (double [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn double @_Z4powndi(double [[X]], i32 4)
+; PRELINK-NEXT: ret double [[POW]]
+;
+; NOPRELINK-LABEL: define double @test_pow_afn_f64__y_4
+; NOPRELINK-SAME: (double [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn double @_Z3powdd(double [[X]], double 4.000000e+00)
+; NOPRELINK-NEXT: ret double [[POW]]
;
%pow = tail call afn double @_Z3powdd(double %x, double 4.0)
ret double %pow
@@ -2825,10 +4717,15 @@ define double @test_pow_afn_f64_nnan_ninf__y_4_5(double %x) {
}
define double @test_pow_afn_f64__y_5(double %x) {
-; CHECK-LABEL: define double @test_pow_afn_f64__y_5
-; CHECK-SAME: (double [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn double @_Z4powndi(double [[X]], i32 5)
-; CHECK-NEXT: ret double [[POW]]
+; PRELINK-LABEL: define double @test_pow_afn_f64__y_5
+; PRELINK-SAME: (double [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn double @_Z4powndi(double [[X]], i32 5)
+; PRELINK-NEXT: ret double [[POW]]
+;
+; NOPRELINK-LABEL: define double @test_pow_afn_f64__y_5
+; NOPRELINK-SAME: (double [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn double @_Z3powdd(double [[X]], double 5.000000e+00)
+; NOPRELINK-NEXT: ret double [[POW]]
;
%pow = tail call afn double @_Z3powdd(double %x, double 5.0)
ret double %pow
@@ -2847,10 +4744,15 @@ define double @test_pow_afn_f64_nnan_ninf__y_5(double %x) {
}
define double @test_pow_afn_f64__y_neg5(double %x) {
-; CHECK-LABEL: define double @test_pow_afn_f64__y_neg5
-; CHECK-SAME: (double [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn double @_Z4powndi(double [[X]], i32 -5)
-; CHECK-NEXT: ret double [[POW]]
+; PRELINK-LABEL: define double @test_pow_afn_f64__y_neg5
+; PRELINK-SAME: (double [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn double @_Z4powndi(double [[X]], i32 -5)
+; PRELINK-NEXT: ret double [[POW]]
+;
+; NOPRELINK-LABEL: define double @test_pow_afn_f64__y_neg5
+; NOPRELINK-SAME: (double [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn double @_Z3powdd(double [[X]], double -5.000000e+00)
+; NOPRELINK-NEXT: ret double [[POW]]
;
%pow = tail call afn double @_Z3powdd(double %x, double -5.0)
ret double %pow
@@ -2927,10 +4829,15 @@ define <2 x double> @test_pow_afn_v2f64_nnan_ninf__y_5(<2 x double> %x) {
}
define half @test_pow_afn_f16__y_3(half %x) {
-; CHECK-LABEL: define half @test_pow_afn_f16__y_3
-; CHECK-SAME: (half [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn half @_Z4pownDhi(half [[X]], i32 3)
-; CHECK-NEXT: ret half [[POW]]
+; PRELINK-LABEL: define half @test_pow_afn_f16__y_3
+; PRELINK-SAME: (half [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn half @_Z4pownDhi(half [[X]], i32 3)
+; PRELINK-NEXT: ret half [[POW]]
+;
+; NOPRELINK-LABEL: define half @test_pow_afn_f16__y_3
+; NOPRELINK-SAME: (half [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn half @_Z3powDhDh(half [[X]], half 0xH4200)
+; NOPRELINK-NEXT: ret half [[POW]]
;
%pow = tail call afn half @_Z3powDhDh(half %x, half 3.0)
ret half %pow
@@ -2948,10 +4855,15 @@ define half @test_pow_afn_f16_nnan_ninf__y_3(half %x) {
}
define half @test_pow_afn_f16__y_4(half %x) {
-; CHECK-LABEL: define half @test_pow_afn_f16__y_4
-; CHECK-SAME: (half [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn half @_Z4pownDhi(half [[X]], i32 4)
-; CHECK-NEXT: ret half [[POW]]
+; PRELINK-LABEL: define half @test_pow_afn_f16__y_4
+; PRELINK-SAME: (half [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn half @_Z4pownDhi(half [[X]], i32 4)
+; PRELINK-NEXT: ret half [[POW]]
+;
+; NOPRELINK-LABEL: define half @test_pow_afn_f16__y_4
+; NOPRELINK-SAME: (half [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn half @_Z3powDhDh(half [[X]], half 0xH4400)
+; NOPRELINK-NEXT: ret half [[POW]]
;
%pow = tail call afn half @_Z3powDhDh(half %x, half 4.0)
ret half %pow
@@ -2979,10 +4891,15 @@ define half @test_pow_afn_f16_nnan_ninf__y_4_5(half %x) {
}
define half @test_pow_afn_f16__y_5(half %x) {
-; CHECK-LABEL: define half @test_pow_afn_f16__y_5
-; CHECK-SAME: (half [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn half @_Z4pownDhi(half [[X]], i32 5)
-; CHECK-NEXT: ret half [[POW]]
+; PRELINK-LABEL: define half @test_pow_afn_f16__y_5
+; PRELINK-SAME: (half [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn half @_Z4pownDhi(half [[X]], i32 5)
+; PRELINK-NEXT: ret half [[POW]]
+;
+; NOPRELINK-LABEL: define half @test_pow_afn_f16__y_5
+; NOPRELINK-SAME: (half [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn half @_Z3powDhDh(half [[X]], half 0xH4500)
+; NOPRELINK-NEXT: ret half [[POW]]
;
%pow = tail call afn half @_Z3powDhDh(half %x, half 5.0)
ret half %pow
@@ -3001,10 +4918,15 @@ define half @test_pow_afn_f16_nnan_ninf__y_5(half %x) {
}
define half @test_pow_afn_f16__y_neg5(half %x) {
-; CHECK-LABEL: define half @test_pow_afn_f16__y_neg5
-; CHECK-SAME: (half [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call afn half @_Z4pownDhi(half [[X]], i32 -5)
-; CHECK-NEXT: ret half [[POW]]
+; PRELINK-LABEL: define half @test_pow_afn_f16__y_neg5
+; PRELINK-SAME: (half [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn half @_Z4pownDhi(half [[X]], i32 -5)
+; PRELINK-NEXT: ret half [[POW]]
+;
+; NOPRELINK-LABEL: define half @test_pow_afn_f16__y_neg5
+; NOPRELINK-SAME: (half [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call afn half @_Z3powDhDh(half [[X]], half 0xHC500)
+; NOPRELINK-NEXT: ret half [[POW]]
;
%pow = tail call afn half @_Z3powDhDh(half %x, half -5.0)
ret half %pow
@@ -3081,12 +5003,18 @@ define <2 x half> @test_pow_afn_v2f16_nnan_ninf__y_5(<2 x half> %x) {
}
define float @test_pow_f32_known_integral_sitofp(float %x, i32 %y) {
-; CHECK-LABEL: define float @test_pow_f32_known_integral_sitofp
-; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32_known_integral_sitofp
+; PRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32_known_integral_sitofp
+; NOPRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y_CAST]])
+; NOPRELINK-NEXT: ret float [[POW]]
;
%y.cast = sitofp i32 %y to float
%pow = tail call float @_Z3powff(float %x, float %y.cast)
@@ -3094,12 +5022,50 @@ define float @test_pow_f32_known_integral_sitofp(float %x, i32 %y) {
}
define float @test_pow_afn_f32_known_integral_sitofp(float %x, i32 %y) {
-; CHECK-LABEL: define float @test_pow_afn_f32_known_integral_sitofp
-; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 [[TMP1]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_known_integral_sitofp
+; PRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 [[TMP1]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_known_integral_sitofp
+; NOPRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float [[Y_CAST]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.log2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul afn float [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn float @llvm.exp2.f32(float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call afn float @llvm.trunc.f32(float [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une float [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP25:%.*]] = or i1 [[TMP23]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP27:%.*]] = xor i1 [[TMP24]], [[TMP26]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = select afn i1 [[TMP27]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP30:%.*]] = call afn float @llvm.copysign.f32(float [[TMP28]], float [[TMP29]])
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP25]], float [[TMP30]], float [[TMP21]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = fcmp afn uno float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP33:%.*]] = select afn i1 [[TMP32]], float 0x7FF8000000000000, float [[TMP31]]
+; NOPRELINK-NEXT: ret float [[TMP33]]
;
%y.cast = sitofp i32 %y to float
%pow = tail call afn float @_Z3powff(float %x, float %y.cast)
@@ -3107,21 +5073,36 @@ define float @test_pow_afn_f32_known_integral_sitofp(float %x, i32 %y) {
}
define float @test_pow_afn_nnan_ninf_f32_known_integral_sitofp(float %x, i32 %y) {
-; CHECK-LABEL: define float @test_pow_afn_nnan_ninf_f32_known_integral_sitofp
-; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
-; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]])
-; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[TMP1]] to float
-; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]]
-; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
-; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[TMP1]], 31
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
-; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[__POW_SIGN]] to float
-; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP3]])
-; CHECK-NEXT: ret float [[__POW_SIGN1]]
+; PRELINK-LABEL: define float @test_pow_afn_nnan_ninf_f32_known_integral_sitofp
+; PRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
+; PRELINK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; PRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]])
+; PRELINK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[TMP1]] to float
+; PRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]]
+; PRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
+; PRELINK-NEXT: [[__YEVEN:%.*]] = shl i32 [[TMP1]], 31
+; PRELINK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
+; PRELINK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
+; PRELINK-NEXT: [[TMP3:%.*]] = bitcast i32 [[__POW_SIGN]] to float
+; PRELINK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP3]])
+; PRELINK-NEXT: ret float [[__POW_SIGN1]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_nnan_ninf_f32_known_integral_sitofp
+; NOPRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]])
+; NOPRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[Y_CAST]]
+; NOPRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
+; NOPRELINK-NEXT: [[__YTOU:%.*]] = fptosi float [[Y_CAST]] to i32
+; NOPRELINK-NEXT: [[__YEVEN:%.*]] = shl i32 [[__YTOU]], 31
+; NOPRELINK-NEXT: [[TMP1:%.*]] = bitcast float [[X]] to i32
+; NOPRELINK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP1]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = bitcast i32 [[__POW_SIGN]] to float
+; NOPRELINK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP2]])
+; NOPRELINK-NEXT: ret float [[__POW_SIGN1]]
;
%y.cast = sitofp i32 %y to float
%pow = tail call afn nnan ninf float @_Z3powff(float %x, float %y.cast)
@@ -3129,12 +5110,48 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_sitofp(float %x, i32 %y)
}
define float @test_pow_afn_nnan_f32_known_integral_sitofp(float %x, i32 %y) {
-; CHECK-LABEL: define float @test_pow_afn_nnan_f32_known_integral_sitofp
-; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
-; CHECK-NEXT: [[POW:%.*]] = tail call nnan afn float @_Z4pownfi(float [[X]], i32 [[TMP1]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_nnan_f32_known_integral_sitofp
+; PRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan afn float @_Z11__pown_fastfi(float [[X]], i32 [[TMP1]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_nnan_f32_known_integral_sitofp
+; NOPRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan afn i1 [[TMP1]], float 1.000000e+00, float [[Y_CAST]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select nnan afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul nnan afn float [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une float [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP25:%.*]] = or i1 [[TMP23]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = fcmp nnan afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP27:%.*]] = xor i1 [[TMP24]], [[TMP26]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = select nnan afn i1 [[TMP27]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP30:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP28]], float [[TMP29]])
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select nnan afn i1 [[TMP25]], float [[TMP30]], float [[TMP21]]
+; NOPRELINK-NEXT: ret float [[TMP31]]
;
%y.cast = sitofp i32 %y to float
%pow = tail call afn nnan float @_Z3powff(float %x, float %y.cast)
@@ -3142,12 +5159,47 @@ define float @test_pow_afn_nnan_f32_known_integral_sitofp(float %x, i32 %y) {
}
define float @test_pow_afn_ninf_f32_known_integral_sitofp(float %x, i32 %y) {
-; CHECK-LABEL: define float @test_pow_afn_ninf_f32_known_integral_sitofp
-; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
-; CHECK-NEXT: [[POW:%.*]] = tail call ninf afn float @_Z4pownfi(float [[X]], i32 [[TMP1]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_ninf_f32_known_integral_sitofp
+; PRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
+; PRELINK-NEXT: [[POW:%.*]] = tail call ninf afn float @_Z11__pown_fastfi(float [[X]], i32 [[TMP1]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_ninf_f32_known_integral_sitofp
+; NOPRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp ninf afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select ninf afn i1 [[TMP1]], float 1.000000e+00, float [[Y_CAST]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp ninf afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select ninf afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call ninf afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call ninf afn float @llvm.log2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul ninf afn float [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call ninf afn float @llvm.exp2.f32(float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call ninf afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp ninf afn oeq float [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan ninf afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call ninf afn float @llvm.trunc.f32(float [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp ninf afn une float [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select ninf afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call ninf afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call ninf afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp ninf afn une float [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp ninf afn olt float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select ninf afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp ninf afn oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp ninf afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP24:%.*]] = xor i1 [[TMP22]], [[TMP23]]
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select ninf afn i1 [[TMP24]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select ninf afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP27:%.*]] = call ninf afn float @llvm.copysign.f32(float [[TMP25]], float [[TMP26]])
+; NOPRELINK-NEXT: [[TMP28:%.*]] = select ninf afn i1 [[TMP22]], float [[TMP27]], float [[TMP21]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = fcmp ninf afn uno float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP30:%.*]] = select ninf afn i1 [[TMP29]], float 0x7FF8000000000000, float [[TMP28]]
+; NOPRELINK-NEXT: ret float [[TMP30]]
;
%y.cast = sitofp i32 %y to float
%pow = tail call afn ninf float @_Z3powff(float %x, float %y.cast)
@@ -3155,12 +5207,18 @@ define float @test_pow_afn_ninf_f32_known_integral_sitofp(float %x, i32 %y) {
}
define float @test_pow_afn_f32_known_integral_sitofp_finite_argument(float %x, i32 %y) {
-; CHECK-LABEL: define float @test_pow_afn_f32_known_integral_sitofp_finite_argument
-; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_known_integral_sitofp_finite_argument
+; PRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_known_integral_sitofp_finite_argument
+; NOPRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float nofpclass(nan inf) [[Y_CAST]])
+; NOPRELINK-NEXT: ret float [[POW]]
;
%y.cast = sitofp i32 %y to float
%pow = tail call float @_Z3powff(float %x, float nofpclass(inf nan) %y.cast)
@@ -3168,12 +5226,18 @@ define float @test_pow_afn_f32_known_integral_sitofp_finite_argument(float %x, i
}
define float @test_pow_f32_known_integral_uitofp(float %x, i32 %y) {
-; CHECK-LABEL: define float @test_pow_f32_known_integral_uitofp
-; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = uitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32_known_integral_uitofp
+; PRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = uitofp i32 [[Y]] to float
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32_known_integral_uitofp
+; NOPRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = uitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y_CAST]])
+; NOPRELINK-NEXT: ret float [[POW]]
;
%y.cast = uitofp i32 %y to float
%pow = tail call float @_Z3powff(float %x, float %y.cast)
@@ -3181,12 +5245,48 @@ define float @test_pow_f32_known_integral_uitofp(float %x, i32 %y) {
}
define float @test_pow_afn_f32_known_integral_uitofp(float %x, i32 %y) {
-; CHECK-LABEL: define float @test_pow_afn_f32_known_integral_uitofp
-; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = uitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 [[TMP1]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_known_integral_uitofp
+; PRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = uitofp i32 [[Y]] to float
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 [[TMP1]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_known_integral_uitofp
+; NOPRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = uitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float [[Y_CAST]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.log2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul afn float [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn float @llvm.exp2.f32(float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call afn float @llvm.trunc.f32(float [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une float [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP25:%.*]] = or i1 [[TMP23]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP24]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn float @llvm.copysign.f32(float [[TMP26]], float [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP25]], float [[TMP28]], float [[TMP21]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP30]], float 0x7FF8000000000000, float [[TMP29]]
+; NOPRELINK-NEXT: ret float [[TMP31]]
;
%y.cast = uitofp i32 %y to float
%pow = tail call afn float @_Z3powff(float %x, float %y.cast)
@@ -3194,21 +5294,36 @@ define float @test_pow_afn_f32_known_integral_uitofp(float %x, i32 %y) {
}
define float @test_pow_afn_nnan_ninf_f32_known_integral_uitofp(float %x, i32 %y) {
-; CHECK-LABEL: define float @test_pow_afn_nnan_ninf_f32_known_integral_uitofp
-; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = uitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
-; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]])
-; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[TMP1]] to float
-; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]]
-; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
-; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[TMP1]], 31
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
-; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[__POW_SIGN]] to float
-; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP3]])
-; CHECK-NEXT: ret float [[__POW_SIGN1]]
+; PRELINK-LABEL: define float @test_pow_afn_nnan_ninf_f32_known_integral_uitofp
+; PRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = uitofp i32 [[Y]] to float
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
+; PRELINK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; PRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]])
+; PRELINK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[TMP1]] to float
+; PRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]]
+; PRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
+; PRELINK-NEXT: [[__YEVEN:%.*]] = shl i32 [[TMP1]], 31
+; PRELINK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
+; PRELINK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
+; PRELINK-NEXT: [[TMP3:%.*]] = bitcast i32 [[__POW_SIGN]] to float
+; PRELINK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP3]])
+; PRELINK-NEXT: ret float [[__POW_SIGN1]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_nnan_ninf_f32_known_integral_uitofp
+; NOPRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = uitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]])
+; NOPRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[Y_CAST]]
+; NOPRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
+; NOPRELINK-NEXT: [[__YTOU:%.*]] = fptosi float [[Y_CAST]] to i32
+; NOPRELINK-NEXT: [[__YEVEN:%.*]] = shl i32 [[__YTOU]], 31
+; NOPRELINK-NEXT: [[TMP1:%.*]] = bitcast float [[X]] to i32
+; NOPRELINK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP1]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = bitcast i32 [[__POW_SIGN]] to float
+; NOPRELINK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP2]])
+; NOPRELINK-NEXT: ret float [[__POW_SIGN1]]
;
%y.cast = uitofp i32 %y to float
%pow = tail call afn nnan ninf float @_Z3powff(float %x, float %y.cast)
@@ -3217,46 +5332,52 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_uitofp(float %x, i32 %y)
; cast from i256 may produce infinity so can't assume integer without ninf
define float @test_pow_afn_nnan_f32_known_integral_uitofp_i256(float %x, i256 %y) {
-; CHECK-LABEL: define float @test_pow_afn_nnan_f32_known_integral_uitofp_i256
-; CHECK-SAME: (float [[X:%.*]], i256 [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = uitofp i256 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp nnan afn oeq float [[X]], 1.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select nnan afn i1 [[TMP1]], float 1.000000e+00, float [[Y_CAST]]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP4:%.*]] = select nnan afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fmul nnan afn float [[TMP2]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[TMP9]], [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
-; CHECK-NEXT: [[TMP12:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP11]])
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une float [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
-; CHECK-NEXT: [[TMP16:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
-; CHECK-NEXT: [[TMP17:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[TMP17]], [[TMP2]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; CHECK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
-; CHECK-NEXT: [[TMP22:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP23:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP24:%.*]] = fcmp nnan afn oeq float [[TMP23]], 1.000000e+00
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp nnan afn olt float [[TMP23]], 1.000000e+00
-; CHECK-NEXT: [[TMP26:%.*]] = select nnan afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP27:%.*]] = select nnan afn i1 [[TMP24]], float 1.000000e+00, float [[TMP26]]
-; CHECK-NEXT: [[TMP28:%.*]] = select nnan afn i1 [[TMP22]], float [[TMP27]], float [[TMP21]]
-; CHECK-NEXT: [[TMP29:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP30:%.*]] = fcmp nnan afn oeq float [[TMP29]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP31:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP32:%.*]] = or i1 [[TMP30]], [[TMP31]]
-; CHECK-NEXT: [[TMP33:%.*]] = select nnan afn i1 [[TMP31]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP34:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
-; CHECK-NEXT: [[TMP35:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP33]], float [[TMP34]])
-; CHECK-NEXT: [[TMP36:%.*]] = select nnan afn i1 [[TMP32]], float [[TMP35]], float [[TMP28]]
-; CHECK-NEXT: ret float [[TMP36]]
+; PRELINK-LABEL: define float @test_pow_afn_nnan_f32_known_integral_uitofp_i256
+; PRELINK-SAME: (float [[X:%.*]], i256 [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = uitofp i256 [[Y]] to float
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan afn float @_Z10__pow_fastff(float [[X]], float [[Y_CAST]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_nnan_f32_known_integral_uitofp_i256
+; NOPRELINK-SAME: (float [[X:%.*]], i256 [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = uitofp i256 [[Y]] to float
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan afn i1 [[TMP1]], float 1.000000e+00, float [[Y_CAST]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select nnan afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul nnan afn float [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une float [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP23:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp nnan afn oeq float [[TMP23]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp nnan afn olt float [[TMP23]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select nnan afn i1 [[TMP25]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select nnan afn i1 [[TMP24]], float 1.000000e+00, float [[TMP26]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = select nnan afn i1 [[TMP22]], float [[TMP27]], float [[TMP21]]
+; NOPRELINK-NEXT: [[TMP29:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp nnan afn oeq float [[TMP29]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP31:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP32:%.*]] = or i1 [[TMP30]], [[TMP31]]
+; NOPRELINK-NEXT: [[TMP33:%.*]] = select nnan afn i1 [[TMP31]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP34:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP35:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP33]], float [[TMP34]])
+; NOPRELINK-NEXT: [[TMP36:%.*]] = select nnan afn i1 [[TMP32]], float [[TMP35]], float [[TMP28]]
+; NOPRELINK-NEXT: ret float [[TMP36]]
;
%y.cast = uitofp i256 %y to float
%pow = tail call afn nnan float @_Z3powff(float %x, float %y.cast)
@@ -3265,52 +5386,58 @@ define float @test_pow_afn_nnan_f32_known_integral_uitofp_i256(float %x, i256 %y
; cast from i256 may produce infinity so can't assume integer without ninf
define float @test_pow_afn_nnan_f32_known_integral_sitofp_i256(float %x, i256 %y) {
-; CHECK-LABEL: define float @test_pow_afn_nnan_f32_known_integral_sitofp_i256
-; CHECK-SAME: (float [[X:%.*]], i256 [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp i256 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp nnan afn oeq float [[X]], 1.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select nnan afn i1 [[TMP1]], float 1.000000e+00, float [[Y_CAST]]
-; CHECK-NEXT: [[TMP3:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP4:%.*]] = select nnan afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fmul nnan afn float [[TMP2]], [[TMP6]]
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[TMP9]], [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
-; CHECK-NEXT: [[TMP12:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP11]])
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une float [[TMP12]], [[TMP11]]
-; CHECK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
-; CHECK-NEXT: [[TMP16:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
-; CHECK-NEXT: [[TMP17:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[TMP17]], [[TMP2]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
-; CHECK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
-; CHECK-NEXT: [[TMP22:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP24:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp nnan afn une float [[TMP2]], [[TMP24]]
-; CHECK-NEXT: [[TMP26:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP27:%.*]] = fcmp nnan afn oeq float [[TMP26]], 1.000000e+00
-; CHECK-NEXT: [[TMP28:%.*]] = fcmp nnan afn olt float [[TMP26]], 1.000000e+00
-; CHECK-NEXT: [[TMP29:%.*]] = xor i1 [[TMP28]], [[TMP25]]
-; CHECK-NEXT: [[TMP30:%.*]] = select nnan afn i1 [[TMP29]], float 0.000000e+00, float [[TMP24]]
-; CHECK-NEXT: [[TMP31:%.*]] = select nnan afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
-; CHECK-NEXT: [[TMP32:%.*]] = select nnan afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
-; CHECK-NEXT: [[TMP33:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq float [[TMP33]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP35:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
-; CHECK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
-; CHECK-NEXT: [[TMP37:%.*]] = fcmp nnan afn olt float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
-; CHECK-NEXT: [[TMP39:%.*]] = select nnan afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP40:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
-; CHECK-NEXT: [[TMP41:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
-; CHECK-NEXT: [[TMP42:%.*]] = select nnan afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
-; CHECK-NEXT: ret float [[TMP42]]
+; PRELINK-LABEL: define float @test_pow_afn_nnan_f32_known_integral_sitofp_i256
+; PRELINK-SAME: (float [[X:%.*]], i256 [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i256 [[Y]] to float
+; PRELINK-NEXT: [[POW:%.*]] = tail call nnan afn float @_Z10__pow_fastff(float [[X]], float [[Y_CAST]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_nnan_f32_known_integral_sitofp_i256
+; NOPRELINK-SAME: (float [[X:%.*]], i256 [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i256 [[Y]] to float
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan afn i1 [[TMP1]], float 1.000000e+00, float [[Y_CAST]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select nnan afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul nnan afn float [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une float [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call nnan afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan afn olt float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp nnan afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp nnan afn une float [[TMP2]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP27:%.*]] = fcmp nnan afn oeq float [[TMP26]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP28:%.*]] = fcmp nnan afn olt float [[TMP26]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP29:%.*]] = xor i1 [[TMP28]], [[TMP25]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = select nnan afn i1 [[TMP29]], float 0.000000e+00, float [[TMP24]]
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select nnan afn i1 [[TMP27]], float 1.000000e+00, float [[TMP30]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = select nnan afn i1 [[TMP23]], float [[TMP31]], float [[TMP21]]
+; NOPRELINK-NEXT: [[TMP33:%.*]] = call nnan afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP34:%.*]] = fcmp nnan afn oeq float [[TMP33]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP35:%.*]] = fcmp nnan afn oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP36:%.*]] = or i1 [[TMP34]], [[TMP35]]
+; NOPRELINK-NEXT: [[TMP37:%.*]] = fcmp nnan afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP38:%.*]] = xor i1 [[TMP35]], [[TMP37]]
+; NOPRELINK-NEXT: [[TMP39:%.*]] = select nnan afn i1 [[TMP38]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP40:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP41:%.*]] = call nnan afn float @llvm.copysign.f32(float [[TMP39]], float [[TMP40]])
+; NOPRELINK-NEXT: [[TMP42:%.*]] = select nnan afn i1 [[TMP36]], float [[TMP41]], float [[TMP32]]
+; NOPRELINK-NEXT: ret float [[TMP42]]
;
%y.cast = sitofp i256 %y to float
%pow = tail call afn nnan float @_Z3powff(float %x, float %y.cast)
@@ -3318,21 +5445,36 @@ define float @test_pow_afn_nnan_f32_known_integral_sitofp_i256(float %x, i256 %y
}
define float @test_pow_afn_nnan_ninf_f32_known_integral_uitofp_i256(float %x, i256 %y) {
-; CHECK-LABEL: define float @test_pow_afn_nnan_ninf_f32_known_integral_uitofp_i256
-; CHECK-SAME: (float [[X:%.*]], i256 [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = uitofp i256 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
-; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]])
-; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[TMP1]] to float
-; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]]
-; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
-; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[TMP1]], 31
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
-; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[__POW_SIGN]] to float
-; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP3]])
-; CHECK-NEXT: ret float [[__POW_SIGN1]]
+; PRELINK-LABEL: define float @test_pow_afn_nnan_ninf_f32_known_integral_uitofp_i256
+; PRELINK-SAME: (float [[X:%.*]], i256 [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = uitofp i256 [[Y]] to float
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
+; PRELINK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; PRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]])
+; PRELINK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[TMP1]] to float
+; PRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]]
+; PRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
+; PRELINK-NEXT: [[__YEVEN:%.*]] = shl i32 [[TMP1]], 31
+; PRELINK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
+; PRELINK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
+; PRELINK-NEXT: [[TMP3:%.*]] = bitcast i32 [[__POW_SIGN]] to float
+; PRELINK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP3]])
+; PRELINK-NEXT: ret float [[__POW_SIGN1]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_nnan_ninf_f32_known_integral_uitofp_i256
+; NOPRELINK-SAME: (float [[X:%.*]], i256 [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = uitofp i256 [[Y]] to float
+; NOPRELINK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]])
+; NOPRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[Y_CAST]]
+; NOPRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
+; NOPRELINK-NEXT: [[__YTOU:%.*]] = fptosi float [[Y_CAST]] to i32
+; NOPRELINK-NEXT: [[__YEVEN:%.*]] = shl i32 [[__YTOU]], 31
+; NOPRELINK-NEXT: [[TMP1:%.*]] = bitcast float [[X]] to i32
+; NOPRELINK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP1]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = bitcast i32 [[__POW_SIGN]] to float
+; NOPRELINK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP2]])
+; NOPRELINK-NEXT: ret float [[__POW_SIGN1]]
;
%y.cast = uitofp i256 %y to float
%pow = tail call afn nnan ninf float @_Z3powff(float %x, float %y.cast)
@@ -3340,21 +5482,36 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_uitofp_i256(float %x, i2
}
define float @test_pow_afn_nnan_ninf_f32_known_integral_sitofp_i256(float %x, i256 %y) {
-; CHECK-LABEL: define float @test_pow_afn_nnan_ninf_f32_known_integral_sitofp_i256
-; CHECK-SAME: (float [[X:%.*]], i256 [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp i256 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
-; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]])
-; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[TMP1]] to float
-; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]]
-; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
-; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[TMP1]], 31
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
-; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[__POW_SIGN]] to float
-; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP3]])
-; CHECK-NEXT: ret float [[__POW_SIGN1]]
+; PRELINK-LABEL: define float @test_pow_afn_nnan_ninf_f32_known_integral_sitofp_i256
+; PRELINK-SAME: (float [[X:%.*]], i256 [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i256 [[Y]] to float
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y_CAST]] to i32
+; PRELINK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; PRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]])
+; PRELINK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[TMP1]] to float
+; PRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]]
+; PRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
+; PRELINK-NEXT: [[__YEVEN:%.*]] = shl i32 [[TMP1]], 31
+; PRELINK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
+; PRELINK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
+; PRELINK-NEXT: [[TMP3:%.*]] = bitcast i32 [[__POW_SIGN]] to float
+; PRELINK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP3]])
+; PRELINK-NEXT: ret float [[__POW_SIGN1]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_nnan_ninf_f32_known_integral_sitofp_i256
+; NOPRELINK-SAME: (float [[X:%.*]], i256 [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i256 [[Y]] to float
+; NOPRELINK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]])
+; NOPRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[Y_CAST]]
+; NOPRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
+; NOPRELINK-NEXT: [[__YTOU:%.*]] = fptosi float [[Y_CAST]] to i32
+; NOPRELINK-NEXT: [[__YEVEN:%.*]] = shl i32 [[__YTOU]], 31
+; NOPRELINK-NEXT: [[TMP1:%.*]] = bitcast float [[X]] to i32
+; NOPRELINK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP1]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = bitcast i32 [[__POW_SIGN]] to float
+; NOPRELINK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP2]])
+; NOPRELINK-NEXT: ret float [[__POW_SIGN1]]
;
%y.cast = sitofp i256 %y to float
%pow = tail call afn nnan ninf float @_Z3powff(float %x, float %y.cast)
@@ -3362,21 +5519,36 @@ define float @test_pow_afn_nnan_ninf_f32_known_integral_sitofp_i256(float %x, i2
}
define <2 x float> @test_pow_afn_nnan_ninf_v2f32_known_integral_sitofp(<2 x float> %x, <2 x i32> %y) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_nnan_ninf_v2f32_known_integral_sitofp
-; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp <2 x i32> [[Y]] to <2 x float>
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi <2 x float> [[Y_CAST]] to <2 x i32>
-; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[__FABS]])
-; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x float>
-; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[__LOG2]], [[POWNI2F]]
-; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]])
-; CHECK-NEXT: [[__YEVEN:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 31)
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[X]] to <2 x i32>
-; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP2]]
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[__POW_SIGN]] to <2 x float>
-; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[__EXP2]], <2 x float> [[TMP3]])
-; CHECK-NEXT: ret <2 x float> [[__POW_SIGN1]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_nnan_ninf_v2f32_known_integral_sitofp
+; PRELINK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = sitofp <2 x i32> [[Y]] to <2 x float>
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi <2 x float> [[Y_CAST]] to <2 x i32>
+; PRELINK-NEXT: [[__FABS:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; PRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[__FABS]])
+; PRELINK-NEXT: [[POWNI2F:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x float>
+; PRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[__LOG2]], [[POWNI2F]]
+; PRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]])
+; PRELINK-NEXT: [[__YEVEN:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 31)
+; PRELINK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[X]] to <2 x i32>
+; PRELINK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP2]]
+; PRELINK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[__POW_SIGN]] to <2 x float>
+; PRELINK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[__EXP2]], <2 x float> [[TMP3]])
+; PRELINK-NEXT: ret <2 x float> [[__POW_SIGN1]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_nnan_ninf_v2f32_known_integral_sitofp
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = sitofp <2 x i32> [[Y]] to <2 x float>
+; NOPRELINK-NEXT: [[__FABS:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[__FABS]])
+; NOPRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[__LOG2]], [[Y_CAST]]
+; NOPRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]])
+; NOPRELINK-NEXT: [[__YTOU:%.*]] = fptosi <2 x float> [[Y_CAST]] to <2 x i32>
+; NOPRELINK-NEXT: [[__YEVEN:%.*]] = shl <2 x i32> [[__YTOU]], splat (i32 31)
+; NOPRELINK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[X]] to <2 x i32>
+; NOPRELINK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP1]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[__POW_SIGN]] to <2 x float>
+; NOPRELINK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[__EXP2]], <2 x float> [[TMP2]])
+; NOPRELINK-NEXT: ret <2 x float> [[__POW_SIGN1]]
;
%y.cast = sitofp <2 x i32> %y to <2 x float>
%pow = tail call afn nnan ninf <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y.cast)
@@ -3384,12 +5556,18 @@ define <2 x float> @test_pow_afn_nnan_ninf_v2f32_known_integral_sitofp(<2 x floa
}
define <2 x float> @test_pow_v2f32_known_integral_uitofp(<2 x float> %x, <2 x i32> %y) {
-; CHECK-LABEL: define <2 x float> @test_pow_v2f32_known_integral_uitofp
-; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = uitofp <2 x i32> [[Y]] to <2 x float>
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi <2 x float> [[Y_CAST]] to <2 x i32>
-; CHECK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[TMP1]])
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_v2f32_known_integral_uitofp
+; PRELINK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = uitofp <2 x i32> [[Y]] to <2 x float>
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi <2 x float> [[Y_CAST]] to <2 x i32>
+; PRELINK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[TMP1]])
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_v2f32_known_integral_uitofp
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = uitofp <2 x i32> [[Y]] to <2 x float>
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z3powDv2_fS_(<2 x float> [[X]], <2 x float> [[Y_CAST]])
+; NOPRELINK-NEXT: ret <2 x float> [[POW]]
;
%y.cast = uitofp <2 x i32> %y to <2 x float>
%pow = tail call <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y.cast)
@@ -3397,12 +5575,48 @@ define <2 x float> @test_pow_v2f32_known_integral_uitofp(<2 x float> %x, <2 x i3
}
define <2 x float> @test_pow_afn_v2f32_known_integral_uitofp(<2 x float> %x, <2 x i32> %y) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_v2f32_known_integral_uitofp
-; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = uitofp <2 x i32> [[Y]] to <2 x float>
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi <2 x float> [[Y_CAST]] to <2 x i32>
-; CHECK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[TMP1]])
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_known_integral_uitofp
+; PRELINK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = uitofp <2 x i32> [[Y]] to <2 x float>
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi <2 x float> [[Y_CAST]] to <2 x i32>
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[TMP1]])
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_v2f32_known_integral_uitofp
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = uitofp <2 x i32> [[Y]] to <2 x float>
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 1.000000e+00), <2 x float> [[Y_CAST]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select afn <2 x i1> [[TMP3]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul afn <2 x float> [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan afn <2 x float> [[TMP2]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une <2 x float> [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP8]], <2 x float> [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn <2 x float> @llvm.trunc.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une <2 x float> [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt <2 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <2 x i1> [[TMP20]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq <2 x float> [[TMP22]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn oeq <2 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = or <2 x i1> [[TMP23]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP24]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP27:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP4]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP28:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP26]], <2 x float> [[TMP27]])
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> [[TMP28]], <2 x float> [[TMP21]]
+; NOPRELINK-NEXT: [[TMP30:%.*]] = fcmp afn uno <2 x float> [[TMP4]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn <2 x i1> [[TMP30]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP29]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP31]]
;
%y.cast = uitofp <2 x i32> %y to <2 x float>
%pow = tail call afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y.cast)
@@ -3410,21 +5624,36 @@ define <2 x float> @test_pow_afn_v2f32_known_integral_uitofp(<2 x float> %x, <2
}
define <2 x float> @test_pow_afn_nnan_ninf_v2f32_known_integral_uitofp(<2 x float> %x, <2 x i32> %y) {
-; CHECK-LABEL: define <2 x float> @test_pow_afn_nnan_ninf_v2f32_known_integral_uitofp
-; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = uitofp <2 x i32> [[Y]] to <2 x float>
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi <2 x float> [[Y_CAST]] to <2 x i32>
-; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[__FABS]])
-; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x float>
-; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[__LOG2]], [[POWNI2F]]
-; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]])
-; CHECK-NEXT: [[__YEVEN:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 31)
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[X]] to <2 x i32>
-; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP2]]
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[__POW_SIGN]] to <2 x float>
-; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[__EXP2]], <2 x float> [[TMP3]])
-; CHECK-NEXT: ret <2 x float> [[__POW_SIGN1]]
+; PRELINK-LABEL: define <2 x float> @test_pow_afn_nnan_ninf_v2f32_known_integral_uitofp
+; PRELINK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = uitofp <2 x i32> [[Y]] to <2 x float>
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi <2 x float> [[Y_CAST]] to <2 x i32>
+; PRELINK-NEXT: [[__FABS:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; PRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[__FABS]])
+; PRELINK-NEXT: [[POWNI2F:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x float>
+; PRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[__LOG2]], [[POWNI2F]]
+; PRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]])
+; PRELINK-NEXT: [[__YEVEN:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 31)
+; PRELINK-NEXT: [[TMP2:%.*]] = bitcast <2 x float> [[X]] to <2 x i32>
+; PRELINK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP2]]
+; PRELINK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[__POW_SIGN]] to <2 x float>
+; PRELINK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[__EXP2]], <2 x float> [[TMP3]])
+; PRELINK-NEXT: ret <2 x float> [[__POW_SIGN1]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_afn_nnan_ninf_v2f32_known_integral_uitofp
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = uitofp <2 x i32> [[Y]] to <2 x float>
+; NOPRELINK-NEXT: [[__FABS:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[__FABS]])
+; NOPRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x float> [[__LOG2]], [[Y_CAST]]
+; NOPRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x float> @llvm.exp2.v2f32(<2 x float> [[__YLOGX]])
+; NOPRELINK-NEXT: [[__YTOU:%.*]] = fptosi <2 x float> [[Y_CAST]] to <2 x i32>
+; NOPRELINK-NEXT: [[__YEVEN:%.*]] = shl <2 x i32> [[__YTOU]], splat (i32 31)
+; NOPRELINK-NEXT: [[TMP1:%.*]] = bitcast <2 x float> [[X]] to <2 x i32>
+; NOPRELINK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i32> [[__YEVEN]], [[TMP1]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[__POW_SIGN]] to <2 x float>
+; NOPRELINK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[__EXP2]], <2 x float> [[TMP2]])
+; NOPRELINK-NEXT: ret <2 x float> [[__POW_SIGN1]]
;
%y.cast = uitofp <2 x i32> %y to <2 x float>
%pow = tail call afn nnan ninf <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> %y.cast)
@@ -3433,11 +5662,17 @@ define <2 x float> @test_pow_afn_nnan_ninf_v2f32_known_integral_uitofp(<2 x floa
; Could fold to powr or pown
define float @test_pow_f32_known_positive_x__known_integral_sitofp(float nofpclass(ninf nsub nnorm) %x, i32 %y) {
-; CHECK-LABEL: define float @test_pow_f32_known_positive_x__known_integral_sitofp
-; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y_CAST]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32_known_positive_x__known_integral_sitofp
+; PRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y_CAST]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32_known_positive_x__known_integral_sitofp
+; NOPRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y_CAST]])
+; NOPRELINK-NEXT: ret float [[POW]]
;
%y.cast = sitofp i32 %y to float
%pow = tail call float @_Z3powff(float %x, float %y.cast)
@@ -3445,12 +5680,19 @@ define float @test_pow_f32_known_positive_x__known_integral_sitofp(float nofpcla
}
define float @test_pow_f32__known_positive_x__known_integral_y(float nofpclass(ninf nnorm nsub nzero) %x, i32 %y.int) #0 {
-; CHECK-LABEL: define float @test_pow_f32__known_positive_x__known_integral_y
-; CHECK-SAME: (float nofpclass(ninf nzero nsub nnorm) [[X:%.*]], i32 [[Y_INT:%.*]]) #[[ATTR2]] {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[Y:%.*]] = sitofp i32 [[Y_INT]] to float
-; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y]])
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_pow_f32__known_positive_x__known_integral_y
+; PRELINK-SAME: (float nofpclass(ninf nzero nsub nnorm) [[X:%.*]], i32 [[Y_INT:%.*]]) #[[ATTR2]] {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[Y:%.*]] = sitofp i32 [[Y_INT]] to float
+; PRELINK-NEXT: [[CALL:%.*]] = tail call float @_Z4powrff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32__known_positive_x__known_integral_y
+; NOPRELINK-SAME: (float nofpclass(ninf nzero nsub nnorm) [[X:%.*]], i32 [[Y_INT:%.*]]) #[[ATTR2]] {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[Y:%.*]] = sitofp i32 [[Y_INT]] to float
+; NOPRELINK-NEXT: [[CALL:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y]])
+; NOPRELINK-NEXT: ret float [[CALL]]
;
entry:
%y = sitofp i32 %y.int to float
@@ -3459,11 +5701,44 @@ entry:
}
define float @test_pow_afn_f32_known_positive_x__known_integral_sitofp(float nofpclass(ninf nsub nnorm) %x, i32 %y) {
-; CHECK-LABEL: define float @test_pow_afn_f32_known_positive_x__known_integral_sitofp
-; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4powrff(float [[X]], float [[Y_CAST]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_known_positive_x__known_integral_sitofp
+; PRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float [[Y_CAST]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_known_positive_x__known_integral_sitofp
+; NOPRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float [[Y_CAST]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.log2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul afn float [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn float @llvm.exp2.f32(float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call afn float @llvm.trunc.f32(float [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une float [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn oeq float [[TMP17]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP20:%.*]] = or i1 [[TMP18]], [[TMP19]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP22:%.*]] = xor i1 [[TMP19]], [[TMP21]]
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn i1 [[TMP22]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP25:%.*]] = call afn float @llvm.copysign.f32(float [[TMP23]], float [[TMP24]])
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP20]], float [[TMP25]], float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP27:%.*]] = fcmp afn uno float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP28:%.*]] = select afn i1 [[TMP27]], float 0x7FF8000000000000, float [[TMP26]]
+; NOPRELINK-NEXT: ret float [[TMP28]]
;
%y.cast = sitofp i32 %y to float
%pow = tail call afn float @_Z3powff(float %x, float %y.cast)
@@ -3471,13 +5746,27 @@ define float @test_pow_afn_f32_known_positive_x__known_integral_sitofp(float nof
}
define float @test_pow_afn_nnan_ninf_f32__known_positive_x__known_integral_sitofp(float nofpclass(ninf nsub nnorm) %x, i32 %y) {
-; CHECK-LABEL: define float @test_pow_afn_nnan_ninf_f32__known_positive_x__known_integral_sitofp
-; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
-; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[X]])
-; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[Y_CAST]]
-; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
-; CHECK-NEXT: ret float [[__EXP2]]
+; PRELINK-LABEL: define float @test_pow_afn_nnan_ninf_f32__known_positive_x__known_integral_sitofp
+; PRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; PRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[X]])
+; PRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[Y_CAST]]
+; PRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
+; PRELINK-NEXT: ret float [[__EXP2]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_nnan_ninf_f32__known_positive_x__known_integral_sitofp
+; NOPRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[X]])
+; NOPRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[Y_CAST]]
+; NOPRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
+; NOPRELINK-NEXT: [[__YTOU:%.*]] = fptosi float [[Y_CAST]] to i32
+; NOPRELINK-NEXT: [[__YEVEN:%.*]] = shl i32 [[__YTOU]], 31
+; NOPRELINK-NEXT: [[TMP1:%.*]] = bitcast float [[X]] to i32
+; NOPRELINK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP1]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = bitcast i32 [[__POW_SIGN]] to float
+; NOPRELINK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP2]])
+; NOPRELINK-NEXT: ret float [[__POW_SIGN1]]
;
%y.cast = sitofp i32 %y to float
%pow = tail call afn nnan ninf float @_Z3powff(float %x, float %y.cast)
@@ -3535,21 +5824,36 @@ define float @test_pow_f32__y_known_integral_trunc_ninf_use(float %x, float %y.a
}
define float @test_pow_afn_f32_nnan_ninf__y_known_integral_trunc(float %x, float %y.arg) {
-; CHECK-LABEL: define float @test_pow_afn_f32_nnan_ninf__y_known_integral_trunc
-; CHECK-SAME: (float [[X:%.*]], float [[Y_ARG:%.*]]) {
-; CHECK-NEXT: [[Y:%.*]] = call float @llvm.trunc.f32(float [[Y_ARG]])
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
-; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]])
-; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[TMP1]] to float
-; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]]
-; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
-; CHECK-NEXT: [[__YEVEN:%.*]] = shl i32 [[TMP1]], 31
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
-; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast i32 [[__POW_SIGN]] to float
-; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP3]])
-; CHECK-NEXT: ret float [[__POW_SIGN1]]
+; PRELINK-LABEL: define float @test_pow_afn_f32_nnan_ninf__y_known_integral_trunc
+; PRELINK-SAME: (float [[X:%.*]], float [[Y_ARG:%.*]]) {
+; PRELINK-NEXT: [[Y:%.*]] = call float @llvm.trunc.f32(float [[Y_ARG]])
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
+; PRELINK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; PRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]])
+; PRELINK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[TMP1]] to float
+; PRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[__LOG2]], [[POWNI2F]]
+; PRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
+; PRELINK-NEXT: [[__YEVEN:%.*]] = shl i32 [[TMP1]], 31
+; PRELINK-NEXT: [[TMP2:%.*]] = bitcast float [[X]] to i32
+; PRELINK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP2]]
+; PRELINK-NEXT: [[TMP3:%.*]] = bitcast i32 [[__POW_SIGN]] to float
+; PRELINK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP3]])
+; PRELINK-NEXT: ret float [[__POW_SIGN1]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32_nnan_ninf__y_known_integral_trunc
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y_ARG:%.*]]) {
+; NOPRELINK-NEXT: [[Y:%.*]] = call float @llvm.trunc.f32(float [[Y_ARG]])
+; NOPRELINK-NEXT: [[__FABS:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[__FABS]])
+; NOPRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn float [[Y]], [[__LOG2]]
+; NOPRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) float @llvm.exp2.f32(float [[__YLOGX]])
+; NOPRELINK-NEXT: [[__YTOU:%.*]] = fptosi float [[Y]] to i32
+; NOPRELINK-NEXT: [[__YEVEN:%.*]] = shl i32 [[__YTOU]], 31
+; NOPRELINK-NEXT: [[TMP1:%.*]] = bitcast float [[X]] to i32
+; NOPRELINK-NEXT: [[__POW_SIGN:%.*]] = and i32 [[__YEVEN]], [[TMP1]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = bitcast i32 [[__POW_SIGN]] to float
+; NOPRELINK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[__EXP2]], float [[TMP2]])
+; NOPRELINK-NEXT: ret float [[__POW_SIGN1]]
;
%y = call float @llvm.trunc.f32(float %y.arg)
%pow = tail call afn nnan ninf float @_Z3powff(float %x, float %y)
@@ -3557,12 +5861,50 @@ define float @test_pow_afn_f32_nnan_ninf__y_known_integral_trunc(float %x, float
}
define float @test_pow_afn_f32__y_known_integral_trunc(float %x, float nofpclass(inf nan) %y.arg) {
-; CHECK-LABEL: define float @test_pow_afn_f32__y_known_integral_trunc
-; CHECK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
-; CHECK-NEXT: [[Y:%.*]] = call float @llvm.trunc.f32(float [[Y_ARG]])
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
-; CHECK-NEXT: [[POW:%.*]] = tail call afn float @_Z4pownfi(float [[X]], i32 [[TMP1]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_afn_f32__y_known_integral_trunc
+; PRELINK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
+; PRELINK-NEXT: [[Y:%.*]] = call float @llvm.trunc.f32(float [[Y_ARG]])
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
+; PRELINK-NEXT: [[POW:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 [[TMP1]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_afn_f32__y_known_integral_trunc
+; NOPRELINK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
+; NOPRELINK-NEXT: [[Y:%.*]] = call float @llvm.trunc.f32(float [[Y_ARG]])
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn oeq float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 1.000000e+00, float [[Y]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP4:%.*]] = select afn i1 [[TMP3]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.log2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fmul afn float [[TMP2]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn float @llvm.exp2.f32(float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fmul nnan afn float [[TMP2]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP12:%.*]] = call afn float @llvm.trunc.f32(float [[TMP11]])
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une float [[TMP12]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP10]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 1.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn float @llvm.copysign.f32(float [[TMP8]], float [[TMP15]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn float @llvm.trunc.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[TMP17]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float 0x7FF8000000000000, float [[TMP16]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = call afn float @llvm.fabs.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn oeq float [[TMP22]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp afn oeq float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP25:%.*]] = or i1 [[TMP23]], [[TMP24]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = fcmp afn olt float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP27:%.*]] = xor i1 [[TMP24]], [[TMP26]]
+; NOPRELINK-NEXT: [[TMP28:%.*]] = select afn i1 [[TMP27]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP29:%.*]] = select afn i1 [[TMP14]], float [[TMP4]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP30:%.*]] = call afn float @llvm.copysign.f32(float [[TMP28]], float [[TMP29]])
+; NOPRELINK-NEXT: [[TMP31:%.*]] = select afn i1 [[TMP25]], float [[TMP30]], float [[TMP21]]
+; NOPRELINK-NEXT: [[TMP32:%.*]] = fcmp afn uno float [[TMP4]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP33:%.*]] = select afn i1 [[TMP32]], float 0x7FF8000000000000, float [[TMP31]]
+; NOPRELINK-NEXT: ret float [[TMP33]]
;
%y = call float @llvm.trunc.f32(float %y.arg)
%pow = tail call afn float @_Z3powff(float %x, float %y)
@@ -3570,12 +5912,18 @@ define float @test_pow_afn_f32__y_known_integral_trunc(float %x, float nofpclass
}
define float @test_pow_f32__y_known_integral_floor(float %x, float nofpclass(inf nan) %y.arg) {
-; CHECK-LABEL: define float @test_pow_f32__y_known_integral_floor
-; CHECK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
-; CHECK-NEXT: [[Y:%.*]] = call float @llvm.floor.f32(float [[Y_ARG]])
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32__y_known_integral_floor
+; PRELINK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
+; PRELINK-NEXT: [[Y:%.*]] = call float @llvm.floor.f32(float [[Y_ARG]])
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32__y_known_integral_floor
+; NOPRELINK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
+; NOPRELINK-NEXT: [[Y:%.*]] = call float @llvm.floor.f32(float [[Y_ARG]])
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y]])
+; NOPRELINK-NEXT: ret float [[POW]]
;
%y = call float @llvm.floor.f32(float %y.arg)
%pow = tail call float @_Z3powff(float %x, float %y)
@@ -3583,12 +5931,18 @@ define float @test_pow_f32__y_known_integral_floor(float %x, float nofpclass(inf
}
define float @test_pow_f32__y_known_integral_ceil(float %x, float nofpclass(inf nan) %y.arg) {
-; CHECK-LABEL: define float @test_pow_f32__y_known_integral_ceil
-; CHECK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
-; CHECK-NEXT: [[Y:%.*]] = call float @llvm.floor.f32(float [[Y_ARG]])
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32__y_known_integral_ceil
+; PRELINK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
+; PRELINK-NEXT: [[Y:%.*]] = call float @llvm.floor.f32(float [[Y_ARG]])
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32__y_known_integral_ceil
+; NOPRELINK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
+; NOPRELINK-NEXT: [[Y:%.*]] = call float @llvm.floor.f32(float [[Y_ARG]])
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y]])
+; NOPRELINK-NEXT: ret float [[POW]]
;
%y = call float @llvm.floor.f32(float %y.arg)
%pow = tail call float @_Z3powff(float %x, float %y)
@@ -3596,12 +5950,18 @@ define float @test_pow_f32__y_known_integral_ceil(float %x, float nofpclass(inf
}
define float @test_pow_f32__y_known_integral_trunc(float %x, float nofpclass(inf nan) %y.arg) {
-; CHECK-LABEL: define float @test_pow_f32__y_known_integral_trunc
-; CHECK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
-; CHECK-NEXT: [[Y:%.*]] = call float @llvm.trunc.f32(float [[Y_ARG]])
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32__y_known_integral_trunc
+; PRELINK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
+; PRELINK-NEXT: [[Y:%.*]] = call float @llvm.trunc.f32(float [[Y_ARG]])
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32__y_known_integral_trunc
+; NOPRELINK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
+; NOPRELINK-NEXT: [[Y:%.*]] = call float @llvm.trunc.f32(float [[Y_ARG]])
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y]])
+; NOPRELINK-NEXT: ret float [[POW]]
;
%y = call float @llvm.trunc.f32(float %y.arg)
%pow = tail call float @_Z3powff(float %x, float %y)
@@ -3609,12 +5969,18 @@ define float @test_pow_f32__y_known_integral_trunc(float %x, float nofpclass(inf
}
define float @test_pow_f32__y_known_integral_rint(float %x, float nofpclass(inf nan) %y.arg) {
-; CHECK-LABEL: define float @test_pow_f32__y_known_integral_rint
-; CHECK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
-; CHECK-NEXT: [[Y:%.*]] = call float @llvm.rint.f32(float [[Y_ARG]])
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32__y_known_integral_rint
+; PRELINK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
+; PRELINK-NEXT: [[Y:%.*]] = call float @llvm.rint.f32(float [[Y_ARG]])
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32__y_known_integral_rint
+; NOPRELINK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
+; NOPRELINK-NEXT: [[Y:%.*]] = call float @llvm.rint.f32(float [[Y_ARG]])
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y]])
+; NOPRELINK-NEXT: ret float [[POW]]
;
%y = call float @llvm.rint.f32(float %y.arg)
%pow = tail call float @_Z3powff(float %x, float %y)
@@ -3622,12 +5988,18 @@ define float @test_pow_f32__y_known_integral_rint(float %x, float nofpclass(inf
}
define float @test_pow_f32__y_known_integral_nearbyint(float %x, float nofpclass(inf nan) %y.arg) {
-; CHECK-LABEL: define float @test_pow_f32__y_known_integral_nearbyint
-; CHECK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
-; CHECK-NEXT: [[Y:%.*]] = call float @llvm.nearbyint.f32(float [[Y_ARG]])
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32__y_known_integral_nearbyint
+; PRELINK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
+; PRELINK-NEXT: [[Y:%.*]] = call float @llvm.nearbyint.f32(float [[Y_ARG]])
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32__y_known_integral_nearbyint
+; NOPRELINK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
+; NOPRELINK-NEXT: [[Y:%.*]] = call float @llvm.nearbyint.f32(float [[Y_ARG]])
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y]])
+; NOPRELINK-NEXT: ret float [[POW]]
;
%y = call float @llvm.nearbyint.f32(float %y.arg)
%pow = tail call float @_Z3powff(float %x, float %y)
@@ -3635,15 +6007,24 @@ define float @test_pow_f32__y_known_integral_nearbyint(float %x, float nofpclass
}
define float @test_pow_f32__y_known_integral_nearbyint_assume(float %x, float %y.arg) {
-; CHECK-LABEL: define float @test_pow_f32__y_known_integral_nearbyint_assume
-; CHECK-SAME: (float [[X:%.*]], float [[Y_ARG:%.*]]) {
-; CHECK-NEXT: [[Y:%.*]] = call float @llvm.nearbyint.f32(float [[Y_ARG]])
-; CHECK-NEXT: [[Y_FABS:%.*]] = call float @llvm.fabs.f32(float [[Y]])
-; CHECK-NEXT: [[Y_IS_FINITE:%.*]] = fcmp one float [[Y_FABS]], 0x7FF0000000000000
-; CHECK-NEXT: call void @llvm.assume(i1 [[Y_IS_FINITE]])
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32__y_known_integral_nearbyint_assume
+; PRELINK-SAME: (float [[X:%.*]], float [[Y_ARG:%.*]]) {
+; PRELINK-NEXT: [[Y:%.*]] = call float @llvm.nearbyint.f32(float [[Y_ARG]])
+; PRELINK-NEXT: [[Y_FABS:%.*]] = call float @llvm.fabs.f32(float [[Y]])
+; PRELINK-NEXT: [[Y_IS_FINITE:%.*]] = fcmp one float [[Y_FABS]], 0x7FF0000000000000
+; PRELINK-NEXT: call void @llvm.assume(i1 [[Y_IS_FINITE]])
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32__y_known_integral_nearbyint_assume
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y_ARG:%.*]]) {
+; NOPRELINK-NEXT: [[Y:%.*]] = call float @llvm.nearbyint.f32(float [[Y_ARG]])
+; NOPRELINK-NEXT: [[Y_FABS:%.*]] = call float @llvm.fabs.f32(float [[Y]])
+; NOPRELINK-NEXT: [[Y_IS_FINITE:%.*]] = fcmp one float [[Y_FABS]], 0x7FF0000000000000
+; NOPRELINK-NEXT: call void @llvm.assume(i1 [[Y_IS_FINITE]])
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y]])
+; NOPRELINK-NEXT: ret float [[POW]]
;
%y = call float @llvm.nearbyint.f32(float %y.arg)
%y.fabs = call float @llvm.fabs.f32(float %y)
@@ -3654,15 +6035,24 @@ define float @test_pow_f32__y_known_integral_nearbyint_assume(float %x, float %y
}
define float @test_pow_f32__y_known_integral_nearbyint_assume_arg_input(float %x, float %y.arg) {
-; CHECK-LABEL: define float @test_pow_f32__y_known_integral_nearbyint_assume_arg_input
-; CHECK-SAME: (float [[X:%.*]], float [[Y_ARG:%.*]]) {
-; CHECK-NEXT: [[Y_ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[Y_ARG]])
-; CHECK-NEXT: [[IS_FINITE:%.*]] = fcmp one float [[Y_ARG_FABS]], 0x7FF0000000000000
-; CHECK-NEXT: call void @llvm.assume(i1 [[IS_FINITE]])
-; CHECK-NEXT: [[Y:%.*]] = call float @llvm.nearbyint.f32(float [[Y_ARG]])
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32__y_known_integral_nearbyint_assume_arg_input
+; PRELINK-SAME: (float [[X:%.*]], float [[Y_ARG:%.*]]) {
+; PRELINK-NEXT: [[Y_ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[Y_ARG]])
+; PRELINK-NEXT: [[IS_FINITE:%.*]] = fcmp one float [[Y_ARG_FABS]], 0x7FF0000000000000
+; PRELINK-NEXT: call void @llvm.assume(i1 [[IS_FINITE]])
+; PRELINK-NEXT: [[Y:%.*]] = call float @llvm.nearbyint.f32(float [[Y_ARG]])
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32__y_known_integral_nearbyint_assume_arg_input
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y_ARG:%.*]]) {
+; NOPRELINK-NEXT: [[Y_ARG_FABS:%.*]] = call float @llvm.fabs.f32(float [[Y_ARG]])
+; NOPRELINK-NEXT: [[IS_FINITE:%.*]] = fcmp one float [[Y_ARG_FABS]], 0x7FF0000000000000
+; NOPRELINK-NEXT: call void @llvm.assume(i1 [[IS_FINITE]])
+; NOPRELINK-NEXT: [[Y:%.*]] = call float @llvm.nearbyint.f32(float [[Y_ARG]])
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y]])
+; NOPRELINK-NEXT: ret float [[POW]]
;
%y.arg.fabs = call float @llvm.fabs.f32(float %y.arg)
%is.finite = fcmp one float %y.arg.fabs, 0x7FF0000000000000
@@ -3673,12 +6063,18 @@ define float @test_pow_f32__y_known_integral_nearbyint_assume_arg_input(float %x
}
define float @test_pow_f32__y_known_integral_round(float %x, float nofpclass(inf nan) %y.arg) {
-; CHECK-LABEL: define float @test_pow_f32__y_known_integral_round
-; CHECK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
-; CHECK-NEXT: [[Y:%.*]] = call float @llvm.round.f32(float [[Y_ARG]])
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32__y_known_integral_round
+; PRELINK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
+; PRELINK-NEXT: [[Y:%.*]] = call float @llvm.round.f32(float [[Y_ARG]])
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32__y_known_integral_round
+; NOPRELINK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
+; NOPRELINK-NEXT: [[Y:%.*]] = call float @llvm.round.f32(float [[Y_ARG]])
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y]])
+; NOPRELINK-NEXT: ret float [[POW]]
;
%y = call float @llvm.round.f32(float %y.arg)
%pow = tail call float @_Z3powff(float %x, float %y)
@@ -3686,12 +6082,18 @@ define float @test_pow_f32__y_known_integral_round(float %x, float nofpclass(inf
}
define float @test_pow_f32__y_known_integral_roundeven(float %x, float nofpclass(inf nan) %y.arg) {
-; CHECK-LABEL: define float @test_pow_f32__y_known_integral_roundeven
-; CHECK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
-; CHECK-NEXT: [[Y:%.*]] = call float @llvm.roundeven.f32(float [[Y_ARG]])
-; CHECK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32__y_known_integral_roundeven
+; PRELINK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
+; PRELINK-NEXT: [[Y:%.*]] = call float @llvm.roundeven.f32(float [[Y_ARG]])
+; PRELINK-NEXT: [[TMP1:%.*]] = fptosi float [[Y]] to i32
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 [[TMP1]])
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32__y_known_integral_roundeven
+; NOPRELINK-SAME: (float [[X:%.*]], float nofpclass(nan inf) [[Y_ARG:%.*]]) {
+; NOPRELINK-NEXT: [[Y:%.*]] = call float @llvm.roundeven.f32(float [[Y_ARG]])
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float [[Y]])
+; NOPRELINK-NEXT: ret float [[POW]]
;
%y = call float @llvm.roundeven.f32(float %y.arg)
%pow = tail call float @_Z3powff(float %x, float %y)
@@ -3709,10 +6111,15 @@ define float @test_pow_f32_known_integral_undef(float %x) {
}
define float @test_pow_f32_known_integral_poison(float %x) {
-; CHECK-LABEL: define float @test_pow_f32_known_integral_poison
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 poison)
-; CHECK-NEXT: ret float [[POW]]
+; PRELINK-LABEL: define float @test_pow_f32_known_integral_poison
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call float @_Z4pownfi(float [[X]], i32 poison)
+; PRELINK-NEXT: ret float [[POW]]
+;
+; NOPRELINK-LABEL: define float @test_pow_f32_known_integral_poison
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call float @_Z3powff(float [[X]], float poison)
+; NOPRELINK-NEXT: ret float [[POW]]
;
%pow = tail call float @_Z3powff(float %x, float poison)
ret float %pow
@@ -3729,10 +6136,15 @@ define <2 x float> @test_pow_v2f32_known_integral_constant_vector_undef_elt(<2 x
}
define <2 x float> @test_pow_v2f32_known_integral_constant_vector_poison_elt(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_pow_v2f32_known_integral_constant_vector_poison_elt
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 4, i32 poison>)
-; CHECK-NEXT: ret <2 x float> [[POW]]
+; PRELINK-LABEL: define <2 x float> @test_pow_v2f32_known_integral_constant_vector_poison_elt
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> [[X]], <2 x i32> <i32 4, i32 poison>)
+; PRELINK-NEXT: ret <2 x float> [[POW]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pow_v2f32_known_integral_constant_vector_poison_elt
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[POW:%.*]] = tail call <2 x float> @_Z3powDv2_fS_(<2 x float> [[X]], <2 x float> <float 4.000000e+00, float poison>)
+; NOPRELINK-NEXT: ret <2 x float> [[POW]]
;
%pow = tail call <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 4.0, float poison>)
ret <2 x float> %pow
@@ -3742,3 +6154,6 @@ attributes #0 = { minsize }
attributes #1 = { noinline }
attributes #2 = { strictfp }
attributes #3 = { nobuiltin }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu-libcall-have-fast-pow", i32 1}
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown-fast.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown-fast.ll
new file mode 100644
index 0000000000000..70b3f48728b13
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown-fast.ll
@@ -0,0 +1,566 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink %s | FileCheck %s
+
+define float @test_pown_afn_f32(float %x, i32 %y) #0 {
+; CHECK-LABEL: define float @test_pown_afn_f32(
+; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 [[Y]])
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call afn float @_Z4pownfi(float %x, i32 %y)
+ ret float %call
+}
+
+declare float @_Z4pownfi(float, i32) #1
+
+define <2 x float> @test_pown_afn_v2f32(<2 x float> %x, <2 x i32> %y) #0 {
+; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32(
+; CHECK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[Y]])
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> %y)
+ ret <2 x float> %call
+}
+
+declare <2 x float> @_Z4pownDv2_fDv2_i(<2 x float>, <2 x i32>) #1
+
+define <3 x float> @test_pown_afn_v3f32(<3 x float> %x, <3 x i32> %y) #0 {
+; CHECK-LABEL: define <3 x float> @test_pown_afn_v3f32(
+; CHECK-SAME: <3 x float> [[X:%.*]], <3 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <3 x float> @_Z11__pown_fastDv3_fDv3_i(<3 x float> [[X]], <3 x i32> [[Y]])
+; CHECK-NEXT: ret <3 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <3 x float> @_Z4pownDv3_fDv3_i(<3 x float> %x, <3 x i32> %y)
+ ret <3 x float> %call
+}
+
+declare <3 x float> @_Z4pownDv3_fDv3_i(<3 x float>, <3 x i32>) #1
+
+define <4 x float> @test_pown_afn_v4f32(<4 x float> %x, <4 x i32> %y) #0 {
+; CHECK-LABEL: define <4 x float> @test_pown_afn_v4f32(
+; CHECK-SAME: <4 x float> [[X:%.*]], <4 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <4 x float> @_Z11__pown_fastDv4_fDv4_i(<4 x float> [[X]], <4 x i32> [[Y]])
+; CHECK-NEXT: ret <4 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <4 x float> @_Z4pownDv4_fDv4_i(<4 x float> %x, <4 x i32> %y)
+ ret <4 x float> %call
+}
+
+declare <4 x float> @_Z4pownDv4_fDv4_i(<4 x float>, <4 x i32>) #1
+
+define <8 x float> @test_pown_afn_v8f32(<8 x float> %x, <8 x i32> %y) #0 {
+; CHECK-LABEL: define <8 x float> @test_pown_afn_v8f32(
+; CHECK-SAME: <8 x float> [[X:%.*]], <8 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <8 x float> @_Z11__pown_fastDv8_fDv8_i(<8 x float> [[X]], <8 x i32> [[Y]])
+; CHECK-NEXT: ret <8 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <8 x float> @_Z4pownDv8_fDv8_i(<8 x float> %x, <8 x i32> %y)
+ ret <8 x float> %call
+}
+
+declare <8 x float> @_Z4pownDv8_fDv8_i(<8 x float>, <8 x i32>) #1
+
+define <16 x float> @test_pown_afn_v16f32(<16 x float> %x, <16 x i32> %y) #0 {
+; CHECK-LABEL: define <16 x float> @test_pown_afn_v16f32(
+; CHECK-SAME: <16 x float> [[X:%.*]], <16 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <16 x float> @_Z11__pown_fastDv16_fDv16_i(<16 x float> [[X]], <16 x i32> [[Y]])
+; CHECK-NEXT: ret <16 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <16 x float> @_Z4pownDv16_fDv16_i(<16 x float> %x, <16 x i32> %y)
+ ret <16 x float> %call
+}
+
+declare <16 x float> @_Z4pownDv16_fDv16_i(<16 x float>, <16 x i32>) #1
+
+define float @test_pown_afn_f32__0(float %x) #0 {
+; CHECK-LABEL: define float @test_pown_afn_f32__0(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret float 1.000000e+00
+;
+entry:
+ %call = tail call afn float @_Z4pownfi(float %x, i32 0)
+ ret float %call
+}
+
+define float @test_pown_afn_f32__1(float %x) #0 {
+; CHECK-LABEL: define float @test_pown_afn_f32__1(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret float [[X]]
+;
+entry:
+ %call = tail call afn float @_Z4pownfi(float %x, i32 1)
+ ret float %call
+}
+
+define float @test_pown_afn_f32__2(float %x) #0 {
+; CHECK-LABEL: define float @test_pown_afn_f32__2(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2:%.*]] = fmul afn float [[X]], [[X]]
+; CHECK-NEXT: ret float [[__POW2]]
+;
+entry:
+ %call = tail call afn float @_Z4pownfi(float %x, i32 2)
+ ret float %call
+}
+
+define float @test_pown_afn_f32__3(float %x) #0 {
+; CHECK-LABEL: define float @test_pown_afn_f32__3(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 3)
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call afn float @_Z4pownfi(float %x, i32 3)
+ ret float %call
+}
+
+define float @test_pown_afn_f32__8(float %x) #0 {
+; CHECK-LABEL: define float @test_pown_afn_f32__8(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 8)
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call afn float @_Z4pownfi(float %x, i32 8)
+ ret float %call
+}
+
+define float @test_pown_afn_f32__neg1(float %x) #0 {
+; CHECK-LABEL: define float @test_pown_afn_f32__neg1(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv afn float 1.000000e+00, [[X]]
+; CHECK-NEXT: ret float [[__POWRECIP]]
+;
+entry:
+ %call = tail call afn float @_Z4pownfi(float %x, i32 -1)
+ ret float %call
+}
+
+define float @test_pown_afn_f32__neg2(float %x) #0 {
+; CHECK-LABEL: define float @test_pown_afn_f32__neg2(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 -2)
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call afn float @_Z4pownfi(float %x, i32 -2)
+ ret float %call
+}
+
+define float @test_pown_afn_f32__neg3(float %x) #0 {
+; CHECK-LABEL: define float @test_pown_afn_f32__neg3(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 -3)
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call afn float @_Z4pownfi(float %x, i32 -3)
+ ret float %call
+}
+
+define float @test_pown_afn_f32__neg8(float %x) #0 {
+; CHECK-LABEL: define float @test_pown_afn_f32__neg8(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 -8)
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call afn float @_Z4pownfi(float %x, i32 -8)
+ ret float %call
+}
+
+define <2 x float> @test_pown_afn_v2f32__0(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32__0(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret <2 x float> splat (float 1.000000e+00)
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> zeroinitializer)
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_pown_afn_v2f32__1(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32__1(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret <2 x float> [[X]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 1))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_pown_afn_v2f32__2(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32__2(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2:%.*]] = fmul afn <2 x float> [[X]], [[X]]
+; CHECK-NEXT: ret <2 x float> [[__POW2]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 2))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_pown_afn_v2f32__3(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32__3(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 3))
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 3))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_pown_afn_v2f32__8(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32__8(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 8))
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 8))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_pown_afn_v2f32__neg1(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32__neg1(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv afn <2 x float> splat (float 1.000000e+00), [[X]]
+; CHECK-NEXT: ret <2 x float> [[__POWRECIP]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 -1))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_pown_afn_v2f32__neg2(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32__neg2(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -2))
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 -2))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_pown_afn_v2f32__neg3(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32__neg3(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -3))
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 -3))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_pown_afn_v2f32__neg8(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32__neg8(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -8))
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 -8))
+ ret <2 x float> %call
+}
+
+define float @test__pown_fast_f32(float %x, i32 %y) #0 {
+; CHECK-LABEL: define float @test__pown_fast_f32(
+; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z11__pown_fastfi(float [[X]], i32 [[Y]])
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call float @_Z11__pown_fastfi(float %x, i32 %y)
+ ret float %call
+}
+
+declare float @_Z11__pown_fastfi(float, i32) #1
+
+define <2 x float> @test__pown_fast_v2f32(<2 x float> %x, <2 x i32> %y) #0 {
+; CHECK-LABEL: define <2 x float> @test__pown_fast_v2f32(
+; CHECK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[Y]])
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> %x, <2 x i32> %y)
+ ret <2 x float> %call
+}
+
+declare <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float>, <2 x i32>) #1
+
+define <3 x float> @test__pown_fast_v3f32(<3 x float> %x, <3 x i32> %y) #0 {
+; CHECK-LABEL: define <3 x float> @test__pown_fast_v3f32(
+; CHECK-SAME: <3 x float> [[X:%.*]], <3 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <3 x float> @_Z11__pown_fastDv3_fDv3_i(<3 x float> [[X]], <3 x i32> [[Y]])
+; CHECK-NEXT: ret <3 x float> [[CALL]]
+;
+entry:
+ %call = tail call <3 x float> @_Z11__pown_fastDv3_fDv3_i(<3 x float> %x, <3 x i32> %y)
+ ret <3 x float> %call
+}
+
+declare <3 x float> @_Z11__pown_fastDv3_fDv3_i(<3 x float>, <3 x i32>) #1
+
+define <4 x float> @test__pown_fast_v4f32(<4 x float> %x, <4 x i32> %y) #0 {
+; CHECK-LABEL: define <4 x float> @test__pown_fast_v4f32(
+; CHECK-SAME: <4 x float> [[X:%.*]], <4 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <4 x float> @_Z11__pown_fastDv4_fDv4_i(<4 x float> [[X]], <4 x i32> [[Y]])
+; CHECK-NEXT: ret <4 x float> [[CALL]]
+;
+entry:
+ %call = tail call <4 x float> @_Z11__pown_fastDv4_fDv4_i(<4 x float> %x, <4 x i32> %y)
+ ret <4 x float> %call
+}
+
+declare <4 x float> @_Z11__pown_fastDv4_fDv4_i(<4 x float>, <4 x i32>) #1
+
+define <8 x float> @test__pown_fast_v8f32(<8 x float> %x, <8 x i32> %y) #0 {
+; CHECK-LABEL: define <8 x float> @test__pown_fast_v8f32(
+; CHECK-SAME: <8 x float> [[X:%.*]], <8 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <8 x float> @_Z11__pown_fastDv8_fDv8_i(<8 x float> [[X]], <8 x i32> [[Y]])
+; CHECK-NEXT: ret <8 x float> [[CALL]]
+;
+entry:
+ %call = tail call <8 x float> @_Z11__pown_fastDv8_fDv8_i(<8 x float> %x, <8 x i32> %y)
+ ret <8 x float> %call
+}
+
+declare <8 x float> @_Z11__pown_fastDv8_fDv8_i(<8 x float>, <8 x i32>) #1
+
+define <16 x float> @test__pown_fast_v16f32(<16 x float> %x, <16 x i32> %y) #0 {
+; CHECK-LABEL: define <16 x float> @test__pown_fast_v16f32(
+; CHECK-SAME: <16 x float> [[X:%.*]], <16 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <16 x float> @_Z11__pown_fastDv16_fDv16_i(<16 x float> [[X]], <16 x i32> [[Y]])
+; CHECK-NEXT: ret <16 x float> [[CALL]]
+;
+entry:
+ %call = tail call <16 x float> @_Z11__pown_fastDv16_fDv16_i(<16 x float> %x, <16 x i32> %y)
+ ret <16 x float> %call
+}
+
+declare <16 x float> @_Z11__pown_fastDv16_fDv16_i(<16 x float>, <16 x i32>) #1
+
+define float @test__pown_fast_f32__0(float %x) #0 {
+; CHECK-LABEL: define float @test__pown_fast_f32__0(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret float 1.000000e+00
+;
+entry:
+ %call = tail call float @_Z11__pown_fastfi(float %x, i32 0)
+ ret float %call
+}
+
+define float @test__pown_fast_afn_f32__0(float %x) #0 {
+; CHECK-LABEL: define float @test__pown_fast_afn_f32__0(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret float 1.000000e+00
+;
+entry:
+ %call = tail call afn float @_Z11__pown_fastfi(float %x, i32 0)
+ ret float %call
+}
+
+define float @test__pown_fast_f32__1(float %x) #0 {
+; CHECK-LABEL: define float @test__pown_fast_f32__1(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret float [[X]]
+;
+entry:
+ %call = tail call float @_Z11__pown_fastfi(float %x, i32 1)
+ ret float %call
+}
+
+define float @test__pown_fast_afn_f32__1(float %x) #0 {
+; CHECK-LABEL: define float @test__pown_fast_afn_f32__1(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret float [[X]]
+;
+entry:
+ %call = tail call afn float @_Z11__pown_fastfi(float %x, i32 1)
+ ret float %call
+}
+
+define float @test__pown_fast_f32__neg1(float %x) #0 {
+; CHECK-LABEL: define float @test__pown_fast_f32__neg1(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv float 1.000000e+00, [[X]]
+; CHECK-NEXT: ret float [[__POWRECIP]]
+;
+entry:
+ %call = tail call float @_Z11__pown_fastfi(float %x, i32 -1)
+ ret float %call
+}
+
+define float @test__pown_fast_afn_f32__neg1(float %x) #0 {
+; CHECK-LABEL: define float @test__pown_fast_afn_f32__neg1(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv afn float 1.000000e+00, [[X]]
+; CHECK-NEXT: ret float [[__POWRECIP]]
+;
+entry:
+ %call = tail call afn float @_Z11__pown_fastfi(float %x, i32 -1)
+ ret float %call
+}
+
+define float @test__pown_fast_f32__2(float %x) #0 {
+; CHECK-LABEL: define float @test__pown_fast_f32__2(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2:%.*]] = fmul float [[X]], [[X]]
+; CHECK-NEXT: ret float [[__POW2]]
+;
+entry:
+ %call = tail call float @_Z11__pown_fastfi(float %x, i32 2)
+ ret float %call
+}
+
+define float @test__pown_fast_afn_f32__2(float %x) #0 {
+; CHECK-LABEL: define float @test__pown_fast_afn_f32__2(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2:%.*]] = fmul afn float [[X]], [[X]]
+; CHECK-NEXT: ret float [[__POW2]]
+;
+entry:
+ %call = tail call afn float @_Z11__pown_fastfi(float %x, i32 2)
+ ret float %call
+}
+
+define float @test__pown_fast_f32__neg2(float %x) #0 {
+; CHECK-LABEL: define float @test__pown_fast_f32__neg2(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z11__pown_fastfi(float [[X]], i32 -2)
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call float @_Z11__pown_fastfi(float %x, i32 -2)
+ ret float %call
+}
+
+define float @test__pown_fast_afn_f32__neg2(float %x) #0 {
+; CHECK-LABEL: define float @test__pown_fast_afn_f32__neg2(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = call afn float @llvm.log2.f32(float [[TMP0]])
+; CHECK-NEXT: [[TMP2:%.*]] = fmul afn float [[TMP1]], -2.000000e+00
+; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.exp2.f32(float [[TMP2]])
+; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.fabs.f32(float [[TMP3]])
+; CHECK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; CHECK-NEXT: [[TMP6:%.*]] = fcmp afn oeq float [[TMP5]], 0x7FF0000000000000
+; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; CHECK-NEXT: [[TMP8:%.*]] = select i1 [[TMP6]], float 0.000000e+00, float [[TMP4]]
+; CHECK-NEXT: [[CALL:%.*]] = select i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP8]]
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call afn float @_Z11__pown_fastfi(float %x, i32 -2)
+ ret float %call
+}
+
+define double @test_pown_afn_f64(double %x, i32 %y) #0 {
+; CHECK-LABEL: define double @test_pown_afn_f64(
+; CHECK-SAME: double [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn double @_Z4powndi(double [[X]], i32 [[Y]])
+; CHECK-NEXT: ret double [[CALL]]
+;
+entry:
+ %call = tail call afn double @_Z4powndi(double %x, i32 %y)
+ ret double %call
+}
+
+declare double @_Z4powndi(double, i32) #0
+
+define <2 x double> @test_pown_afn_v2f64(<2 x double> %x, <2 x i32> %y) #0 {
+; CHECK-LABEL: define <2 x double> @test_pown_afn_v2f64(
+; CHECK-SAME: <2 x double> [[X:%.*]], <2 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x double> @_Z4pownDv2_dDv2_i(<2 x double> [[X]], <2 x i32> [[Y]])
+; CHECK-NEXT: ret <2 x double> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x double> @_Z4pownDv2_dDv2_i(<2 x double> %x, <2 x i32> %y)
+ ret <2 x double> %call
+}
+
+declare <2 x double> @_Z4pownDv2_dDv2_i(<2 x double>, <2 x i32>) #0
+
+define half @test_pown_afn_f16(half %x, i32 %y) #0 {
+; CHECK-LABEL: define half @test_pown_afn_f16(
+; CHECK-SAME: half [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn half @_Z4pownDhi(half [[X]], i32 [[Y]])
+; CHECK-NEXT: ret half [[CALL]]
+;
+entry:
+ %call = tail call afn half @_Z4pownDhi(half %x, i32 %y)
+ ret half %call
+}
+
+declare half @_Z4pownDhi(half, i32) #0
+
+define <2 x half> @test_pown_afn_v2f16(<2 x half> %x, <2 x i32> %y) #0 {
+; CHECK-LABEL: define <2 x half> @test_pown_afn_v2f16(
+; CHECK-SAME: <2 x half> [[X:%.*]], <2 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half> [[X]], <2 x i32> [[Y]])
+; CHECK-NEXT: ret <2 x half> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half> %x, <2 x i32> %y)
+ ret <2 x half> %call
+}
+
+declare <2 x half> @_Z4pownDv2_DhDv2_i(<2 x half>, <2 x i32>) #0
+
+attributes #0 = { mustprogress nofree norecurse nounwind willreturn memory(none) }
+attributes #1 = { mustprogress nofree nounwind willreturn memory(none) }
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll
index b0d0d44cf266f..b4182ccbf77a4 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pown.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
-; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink %s | FileCheck %s
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink %s | FileCheck -check-prefixes=CHECK,PRELINK %s
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine %s | FileCheck -check-prefixes=CHECK,NOPRELINK %s
declare float @_Z4pownfi(float, i32)
declare <2 x float> @_Z4pownDv2_fDv2_i(<2 x float>, <2 x i32>)
@@ -594,31 +595,37 @@ entry:
}
define float @test_pown_afn_f32(float %x, i32 %y) {
-; CHECK-LABEL: define float @test_pown_afn_f32
-; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[Y]], 0
-; CHECK-NEXT: [[TMP1:%.*]] = select afn i1 [[TMP0]], float 1.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP2:%.*]] = sitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], [[TMP2]]
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[Y]], 1
-; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP7]], 0
-; CHECK-NEXT: [[TMP8:%.*]] = select afn i1 [[DOTNOT]], float 1.000000e+00, float [[TMP1]]
-; CHECK-NEXT: [[TMP9:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP8]])
-; CHECK-NEXT: [[TMP10:%.*]] = call afn float @llvm.fabs.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[TMP10]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[TMP1]], 0.000000e+00
-; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP11]], [[TMP12]]
-; CHECK-NEXT: [[TMP14:%.*]] = icmp slt i32 [[Y]], 0
-; CHECK-NEXT: [[TMP15:%.*]] = xor i1 [[TMP12]], [[TMP14]]
-; CHECK-NEXT: [[TMP16:%.*]] = select afn i1 [[TMP15]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP17:%.*]] = select afn i1 [[DOTNOT]], float 0.000000e+00, float [[TMP1]]
-; CHECK-NEXT: [[TMP18:%.*]] = call afn float @llvm.copysign.f32(float [[TMP16]], float [[TMP17]])
-; CHECK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP13]], float [[TMP18]], float [[TMP9]]
-; CHECK-NEXT: ret float [[TMP19]]
+; PRELINK-LABEL: define float @test_pown_afn_f32
+; PRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[CALL:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 [[Y]])
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_pown_afn_f32
+; NOPRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP1:%.*]] = select afn i1 [[TMP0]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = sitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = and i32 [[Y]], 1
+; NOPRELINK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP7]], 0
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[DOTNOT]], float 1.000000e+00, float [[TMP1]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP8]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.fabs.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[TMP10]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[TMP1]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP13:%.*]] = or i1 [[TMP11]], [[TMP12]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = icmp slt i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP15:%.*]] = xor i1 [[TMP12]], [[TMP14]]
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[TMP15]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn i1 [[DOTNOT]], float 0.000000e+00, float [[TMP1]]
+; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn float @llvm.copysign.f32(float [[TMP16]], float [[TMP17]])
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP13]], float [[TMP18]], float [[TMP9]]
+; NOPRELINK-NEXT: ret float [[TMP19]]
;
entry:
%call = tail call afn float @_Z4pownfi(float %x, i32 %y)
@@ -626,31 +633,37 @@ entry:
}
define <2 x float> @test_pown_afn_v2f32(<2 x float> %x, <2 x i32> %y) {
-; CHECK-LABEL: define <2 x float> @test_pown_afn_v2f32
-; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = icmp eq <2 x i32> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP1:%.*]] = select afn <2 x i1> [[TMP0]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP2:%.*]] = sitofp <2 x i32> [[Y]] to <2 x float>
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP1]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], [[TMP2]]
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = and <2 x i32> [[Y]], splat (i32 1)
-; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq <2 x i32> [[TMP7]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[DOTNOT]], <2 x float> splat (float 1.000000e+00), <2 x float> [[TMP1]]
-; CHECK-NEXT: [[TMP9:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP8]])
-; CHECK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP1]])
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn oeq <2 x float> [[TMP10]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <2 x float> [[TMP1]], zeroinitializer
-; CHECK-NEXT: [[TMP13:%.*]] = or <2 x i1> [[TMP11]], [[TMP12]]
-; CHECK-NEXT: [[TMP14:%.*]] = icmp slt <2 x i32> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP15:%.*]] = xor <2 x i1> [[TMP12]], [[TMP14]]
-; CHECK-NEXT: [[TMP16:%.*]] = select afn <2 x i1> [[TMP15]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP17:%.*]] = select afn <2 x i1> [[DOTNOT]], <2 x float> zeroinitializer, <2 x float> [[TMP1]]
-; CHECK-NEXT: [[TMP18:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP16]], <2 x float> [[TMP17]])
-; CHECK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP13]], <2 x float> [[TMP18]], <2 x float> [[TMP9]]
-; CHECK-NEXT: ret <2 x float> [[TMP19]]
+; PRELINK-LABEL: define <2 x float> @test_pown_afn_v2f32
+; PRELINK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z11__pown_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[Y]])
+; PRELINK-NEXT: ret <2 x float> [[CALL]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_pown_afn_v2f32
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[TMP0:%.*]] = icmp eq <2 x i32> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP1:%.*]] = select afn <2 x i1> [[TMP0]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = sitofp <2 x i32> [[Y]] to <2 x float>
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP1]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = and <2 x i32> [[Y]], splat (i32 1)
+; NOPRELINK-NEXT: [[DOTNOT:%.*]] = icmp eq <2 x i32> [[TMP7]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[DOTNOT]], <2 x float> splat (float 1.000000e+00), <2 x float> [[TMP1]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP6]], <2 x float> [[TMP8]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP1]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq <2 x float> [[TMP10]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <2 x float> [[TMP1]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP13:%.*]] = or <2 x i1> [[TMP11]], [[TMP12]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = icmp slt <2 x i32> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP15:%.*]] = xor <2 x i1> [[TMP12]], [[TMP14]]
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn <2 x i1> [[TMP15]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn <2 x i1> [[DOTNOT]], <2 x float> zeroinitializer, <2 x float> [[TMP1]]
+; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP16]], <2 x float> [[TMP17]])
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn <2 x i1> [[TMP13]], <2 x float> [[TMP18]], <2 x float> [[TMP9]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP19]]
;
entry:
%call = tail call afn <2 x float> @_Z4pownDv2_fDv2_i(<2 x float> %x, <2 x i32> %y)
@@ -748,21 +761,27 @@ entry:
}
define double @test_pown_afn_nnan_ninf_f64(double %x, i32 %y) {
-; CHECK-LABEL: define double @test_pown_afn_nnan_ninf_f64
-; CHECK-SAME: (double [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn double @llvm.fabs.f64(double [[X]])
-; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn double @_Z4log2d(double [[__FABS]])
-; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to double
-; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn double [[__LOG2]], [[POWNI2F]]
-; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) double @_Z4exp2d(double [[__YLOGX]])
-; CHECK-NEXT: [[__YTOU:%.*]] = zext i32 [[Y]] to i64
-; CHECK-NEXT: [[__YEVEN:%.*]] = shl i64 [[__YTOU]], 63
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast double [[X]] to i64
-; CHECK-NEXT: [[__POW_SIGN:%.*]] = and i64 [[__YEVEN]], [[TMP0]]
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[__POW_SIGN]] to double
-; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn double @llvm.copysign.f64(double [[__EXP2]], double [[TMP1]])
-; CHECK-NEXT: ret double [[__POW_SIGN1]]
+; PRELINK-LABEL: define double @test_pown_afn_nnan_ninf_f64
+; PRELINK-SAME: (double [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[__FABS:%.*]] = call nnan ninf afn double @llvm.fabs.f64(double [[X]])
+; PRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn double @_Z4log2d(double [[__FABS]])
+; PRELINK-NEXT: [[POWNI2F:%.*]] = sitofp i32 [[Y]] to double
+; PRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn double [[__LOG2]], [[POWNI2F]]
+; PRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) double @_Z4exp2d(double [[__YLOGX]])
+; PRELINK-NEXT: [[__YTOU:%.*]] = zext i32 [[Y]] to i64
+; PRELINK-NEXT: [[__YEVEN:%.*]] = shl i64 [[__YTOU]], 63
+; PRELINK-NEXT: [[TMP0:%.*]] = bitcast double [[X]] to i64
+; PRELINK-NEXT: [[__POW_SIGN:%.*]] = and i64 [[__YEVEN]], [[TMP0]]
+; PRELINK-NEXT: [[TMP1:%.*]] = bitcast i64 [[__POW_SIGN]] to double
+; PRELINK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn double @llvm.copysign.f64(double [[__EXP2]], double [[TMP1]])
+; PRELINK-NEXT: ret double [[__POW_SIGN1]]
+;
+; NOPRELINK-LABEL: define double @test_pown_afn_nnan_ninf_f64
+; NOPRELINK-SAME: (double [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn double @_Z4powndi(double [[X]], i32 [[Y]])
+; NOPRELINK-NEXT: ret double [[CALL]]
;
entry:
%call = tail call nnan ninf afn double @_Z4powndi(double %x, i32 %y)
@@ -770,21 +789,27 @@ entry:
}
define <2 x double> @test_pown_afn_nnan_ninf_v2f64(<2 x double> %x, <2 x i32> %y) {
-; CHECK-LABEL: define <2 x double> @test_pown_afn_nnan_ninf_v2f64
-; CHECK-SAME: (<2 x double> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[__FABS:%.*]] = call nnan ninf afn <2 x double> @llvm.fabs.v2f64(<2 x double> [[X]])
-; CHECK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x double> @_Z4log2Dv2_d(<2 x double> [[__FABS]])
-; CHECK-NEXT: [[POWNI2F:%.*]] = sitofp <2 x i32> [[Y]] to <2 x double>
-; CHECK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x double> [[__LOG2]], [[POWNI2F]]
-; CHECK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x double> @_Z4exp2Dv2_d(<2 x double> [[__YLOGX]])
-; CHECK-NEXT: [[__YTOU:%.*]] = zext <2 x i32> [[Y]] to <2 x i64>
-; CHECK-NEXT: [[__YEVEN:%.*]] = shl <2 x i64> [[__YTOU]], splat (i64 63)
-; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[X]] to <2 x i64>
-; CHECK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i64> [[__YEVEN]], [[TMP0]]
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[__POW_SIGN]] to <2 x double>
-; CHECK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn <2 x double> @llvm.copysign.v2f64(<2 x double> [[__EXP2]], <2 x double> [[TMP1]])
-; CHECK-NEXT: ret <2 x double> [[__POW_SIGN1]]
+; PRELINK-LABEL: define <2 x double> @test_pown_afn_nnan_ninf_v2f64
+; PRELINK-SAME: (<2 x double> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[__FABS:%.*]] = call nnan ninf afn <2 x double> @llvm.fabs.v2f64(<2 x double> [[X]])
+; PRELINK-NEXT: [[__LOG2:%.*]] = call nnan ninf afn <2 x double> @_Z4log2Dv2_d(<2 x double> [[__FABS]])
+; PRELINK-NEXT: [[POWNI2F:%.*]] = sitofp <2 x i32> [[Y]] to <2 x double>
+; PRELINK-NEXT: [[__YLOGX:%.*]] = fmul nnan ninf afn <2 x double> [[__LOG2]], [[POWNI2F]]
+; PRELINK-NEXT: [[__EXP2:%.*]] = call nnan ninf afn nofpclass(nan ninf nzero nsub nnorm) <2 x double> @_Z4exp2Dv2_d(<2 x double> [[__YLOGX]])
+; PRELINK-NEXT: [[__YTOU:%.*]] = zext <2 x i32> [[Y]] to <2 x i64>
+; PRELINK-NEXT: [[__YEVEN:%.*]] = shl <2 x i64> [[__YTOU]], splat (i64 63)
+; PRELINK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[X]] to <2 x i64>
+; PRELINK-NEXT: [[__POW_SIGN:%.*]] = and <2 x i64> [[__YEVEN]], [[TMP0]]
+; PRELINK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[__POW_SIGN]] to <2 x double>
+; PRELINK-NEXT: [[__POW_SIGN1:%.*]] = call nnan ninf afn <2 x double> @llvm.copysign.v2f64(<2 x double> [[__EXP2]], <2 x double> [[TMP1]])
+; PRELINK-NEXT: ret <2 x double> [[__POW_SIGN1]]
+;
+; NOPRELINK-LABEL: define <2 x double> @test_pown_afn_nnan_ninf_v2f64
+; NOPRELINK-SAME: (<2 x double> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn <2 x double> @_Z4pownDv2_dDv2_i(<2 x double> [[X]], <2 x i32> [[Y]])
+; NOPRELINK-NEXT: ret <2 x double> [[CALL]]
;
entry:
%call = tail call nnan ninf afn <2 x double> @_Z4pownDv2_dDv2_i(<2 x double> %x, <2 x i32> %y)
@@ -836,11 +861,17 @@ entry:
}
define float @test_pown_fast_f32_nobuiltin(float %x, i32 %y) {
-; CHECK-LABEL: define float @test_pown_fast_f32_nobuiltin
-; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CALL:%.*]] = tail call fast float @_Z4pownfi(float [[X]], i32 [[Y]]) #[[ATTR4:[0-9]+]]
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_pown_fast_f32_nobuiltin
+; PRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[CALL:%.*]] = tail call fast float @_Z4pownfi(float [[X]], i32 [[Y]]) #[[ATTR4:[0-9]+]]
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_pown_fast_f32_nobuiltin
+; NOPRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[CALL:%.*]] = tail call fast float @_Z4pownfi(float [[X]], i32 [[Y]]) #[[ATTR3:[0-9]+]]
+; NOPRELINK-NEXT: ret float [[CALL]]
;
entry:
%call = tail call fast float @_Z4pownfi(float %x, i32 %y) #0
@@ -1081,31 +1112,37 @@ entry:
}
define float @test_pown_afn_f32__x_known_positive(float nofpclass(ninf nsub nnorm) %x, i32 %y) {
-; CHECK-LABEL: define float @test_pown_afn_f32__x_known_positive
-; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[Y]], 0
-; CHECK-NEXT: [[TMP1:%.*]] = select afn i1 [[TMP0]], float 1.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP2:%.*]] = sitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], [[TMP2]]
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[Y]], 1
-; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP7]], 0
-; CHECK-NEXT: [[TMP8:%.*]] = select afn i1 [[DOTNOT]], float 1.000000e+00, float [[TMP1]]
-; CHECK-NEXT: [[TMP9:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP8]])
-; CHECK-NEXT: [[TMP10:%.*]] = call afn float @llvm.fabs.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[TMP10]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[TMP1]], 0.000000e+00
-; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP11]], [[TMP12]]
-; CHECK-NEXT: [[TMP14:%.*]] = icmp slt i32 [[Y]], 0
-; CHECK-NEXT: [[TMP15:%.*]] = xor i1 [[TMP12]], [[TMP14]]
-; CHECK-NEXT: [[TMP16:%.*]] = select afn i1 [[TMP15]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP17:%.*]] = select afn i1 [[DOTNOT]], float 0.000000e+00, float [[TMP1]]
-; CHECK-NEXT: [[TMP18:%.*]] = call afn float @llvm.copysign.f32(float [[TMP16]], float [[TMP17]])
-; CHECK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP13]], float [[TMP18]], float [[TMP9]]
-; CHECK-NEXT: ret float [[TMP19]]
+; PRELINK-LABEL: define float @test_pown_afn_f32__x_known_positive
+; PRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[CALL:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 [[Y]])
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_pown_afn_f32__x_known_positive
+; NOPRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP1:%.*]] = select afn i1 [[TMP0]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = sitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = and i32 [[Y]], 1
+; NOPRELINK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP7]], 0
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[DOTNOT]], float 1.000000e+00, float [[TMP1]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.copysign.f32(float [[TMP6]], float [[TMP8]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call afn float @llvm.fabs.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[TMP10]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[TMP1]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP13:%.*]] = or i1 [[TMP11]], [[TMP12]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = icmp slt i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP15:%.*]] = xor i1 [[TMP12]], [[TMP14]]
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[TMP15]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn i1 [[DOTNOT]], float 0.000000e+00, float [[TMP1]]
+; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn float @llvm.copysign.f32(float [[TMP16]], float [[TMP17]])
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP13]], float [[TMP18]], float [[TMP9]]
+; NOPRELINK-NEXT: ret float [[TMP19]]
;
entry:
%call = tail call afn float @_Z4pownfi(float %x, i32 %y)
@@ -1133,20 +1170,26 @@ entry:
}
define float @test_pown_afn_f32__x_known_positive__y_4(float nofpclass(ninf nsub nnorm) %x) {
-; CHECK-LABEL: define float @test_pown_afn_f32__x_known_positive__y_4
-; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP1:%.*]] = call afn float @llvm.log2.f32(float [[TMP0]])
-; CHECK-NEXT: [[TMP2:%.*]] = fmul afn float [[TMP1]], 4.000000e+00
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.exp2.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.fabs.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP6:%.*]] = fcmp afn oeq float [[TMP5]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP8:%.*]] = select i1 [[TMP6]], float 0x7FF0000000000000, float [[TMP4]]
-; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP7]], float 0.000000e+00, float [[TMP8]]
-; CHECK-NEXT: ret float [[TMP9]]
+; PRELINK-LABEL: define float @test_pown_afn_f32__x_known_positive__y_4
+; PRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[CALL:%.*]] = tail call afn float @_Z11__pown_fastfi(float [[X]], i32 4)
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_pown_afn_f32__x_known_positive__y_4
+; NOPRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[TMP0:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call afn float @llvm.log2.f32(float [[TMP0]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = fmul afn float [[TMP1]], 4.000000e+00
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.exp2.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.fabs.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp afn oeq float [[TMP5]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select i1 [[TMP6]], float 0x7FF0000000000000, float [[TMP4]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP7]], float 0.000000e+00, float [[TMP8]]
+; NOPRELINK-NEXT: ret float [[TMP9]]
;
entry:
%call = tail call afn float @_Z4pownfi(float %x, i32 4)
@@ -1216,3 +1259,6 @@ entry:
attributes #0 = { nobuiltin }
attributes #1 = { strictfp }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu-libcall-have-fast-pow", i32 1}
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr-fast.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr-fast.ll
new file mode 100644
index 0000000000000..20ad490bdf0f8
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr-fast.ll
@@ -0,0 +1,487 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink %s | FileCheck %s
+
+define float @test_powr_afn_f32(float %x, float %y) #0 {
+; CHECK-LABEL: define float @test_powr_afn_f32(
+; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float [[Y]])
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call afn float @_Z4powrff(float %x, float %y)
+ ret float %call
+}
+
+declare float @_Z4powrff(float, float) #1
+
+define <2 x float> @test_powr_afn_v2f32(<2 x float> %x, <2 x float> %y) #0 {
+; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32(
+; CHECK-SAME: <2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y)
+ ret <2 x float> %call
+}
+
+declare <2 x float> @_Z4powrDv2_fS_(<2 x float>, <2 x float>) #1
+
+define <3 x float> @test_powr_afn_v3f32(<3 x float> %x, <3 x float> %y) #0 {
+; CHECK-LABEL: define <3 x float> @test_powr_afn_v3f32(
+; CHECK-SAME: <3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <3 x float> @_Z11__powr_fastDv3_fS_(<3 x float> [[X]], <3 x float> [[Y]])
+; CHECK-NEXT: ret <3 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <3 x float> @_Z4powrDv3_fS_(<3 x float> %x, <3 x float> %y)
+ ret <3 x float> %call
+}
+
+declare <3 x float> @_Z4powrDv3_fS_(<3 x float>, <3 x float>) #1
+
+define <4 x float> @test_powr_afn_v4f32(<4 x float> %x, <4 x float> %y) #0 {
+; CHECK-LABEL: define <4 x float> @test_powr_afn_v4f32(
+; CHECK-SAME: <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <4 x float> @_Z11__powr_fastDv4_fS_(<4 x float> [[X]], <4 x float> [[Y]])
+; CHECK-NEXT: ret <4 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <4 x float> @_Z4powrDv4_fS_(<4 x float> %x, <4 x float> %y)
+ ret <4 x float> %call
+}
+
+declare <4 x float> @_Z4powrDv4_fS_(<4 x float>, <4 x float>) #1
+
+define <8 x float> @test_powr_afn_v8f32(<8 x float> %x, <8 x float> %y) #0 {
+; CHECK-LABEL: define <8 x float> @test_powr_afn_v8f32(
+; CHECK-SAME: <8 x float> [[X:%.*]], <8 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <8 x float> @_Z11__powr_fastDv8_fS_(<8 x float> [[X]], <8 x float> [[Y]])
+; CHECK-NEXT: ret <8 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <8 x float> @_Z4powrDv8_fS_(<8 x float> %x, <8 x float> %y)
+ ret <8 x float> %call
+}
+
+declare <8 x float> @_Z4powrDv8_fS_(<8 x float>, <8 x float>) #1
+
+define <16 x float> @test_powr_afn_v16f32(<16 x float> %x, <16 x float> %y) #0 {
+; CHECK-LABEL: define <16 x float> @test_powr_afn_v16f32(
+; CHECK-SAME: <16 x float> [[X:%.*]], <16 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <16 x float> @_Z11__powr_fastDv16_fS_(<16 x float> [[X]], <16 x float> [[Y]])
+; CHECK-NEXT: ret <16 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <16 x float> @_Z4powrDv16_fS_(<16 x float> %x, <16 x float> %y)
+ ret <16 x float> %call
+}
+
+declare <16 x float> @_Z4powrDv16_fS_(<16 x float>, <16 x float>) #1
+
+define float @test_powr_afn_f32_known_integral_sitofp(float %x, i32 %y) {
+; CHECK-LABEL: define float @test_powr_afn_f32_known_integral_sitofp(
+; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float [[Y_CAST]])
+; CHECK-NEXT: ret float [[CALL]]
+;
+ %y.cast = sitofp i32 %y to float
+ %call = tail call afn float @_Z4powrff(float %x, float %y.cast)
+ ret float %call
+}
+
+define float @test_powr_afn_f32__0(float %x) #0 {
+; CHECK-LABEL: define float @test_powr_afn_f32__0(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret float 1.000000e+00
+;
+entry:
+ %call = tail call afn float @_Z4powrff(float %x, float 0.0)
+ ret float %call
+}
+
+define float @test_powr_afn_f32__1(float %x) #0 {
+; CHECK-LABEL: define float @test_powr_afn_f32__1(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret float [[X]]
+;
+entry:
+ %call = tail call afn float @_Z4powrff(float %x, float 1.0)
+ ret float %call
+}
+
+define float @test_powr_afn_f32__2(float %x) #0 {
+; CHECK-LABEL: define float @test_powr_afn_f32__2(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2:%.*]] = fmul afn float [[X]], [[X]]
+; CHECK-NEXT: ret float [[__POW2]]
+;
+entry:
+ %call = tail call afn float @_Z4powrff(float %x, float 2.0)
+ ret float %call
+}
+
+define float @test_powr_afn_f32__3(float %x) #0 {
+; CHECK-LABEL: define float @test_powr_afn_f32__3(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float 3.000000e+00)
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call afn float @_Z4powrff(float %x, float 3.0)
+ ret float %call
+}
+
+define float @test_powr_afn_f32__8(float %x) #0 {
+; CHECK-LABEL: define float @test_powr_afn_f32__8(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float 8.000000e+00)
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call afn float @_Z4powrff(float %x, float 8.0)
+ ret float %call
+}
+
+define float @test_powr_afn_f32__neg1(float %x) #0 {
+; CHECK-LABEL: define float @test_powr_afn_f32__neg1(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv afn float 1.000000e+00, [[X]]
+; CHECK-NEXT: ret float [[__POWRECIP]]
+;
+entry:
+ %call = tail call afn float @_Z4powrff(float %x, float -1.0)
+ ret float %call
+}
+
+define float @test_powr_afn_f32__half(float %x) #0 {
+; CHECK-LABEL: define float @test_powr_afn_f32__half(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2SQRT:%.*]] = call afn float @_Z4sqrtf(float [[X]])
+; CHECK-NEXT: ret float [[__POW2SQRT]]
+;
+entry:
+ %call = tail call afn float @_Z4powrff(float %x, float 0.5)
+ ret float %call
+}
+
+define float @test_powr_afn_f32__neghalf(float %x) #0 {
+; CHECK-LABEL: define float @test_powr_afn_f32__neghalf(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2RSQRT:%.*]] = call afn float @_Z5rsqrtf(float [[X]])
+; CHECK-NEXT: ret float [[__POW2RSQRT]]
+;
+entry:
+ %call = tail call afn float @_Z4powrff(float %x, float -0.5)
+ ret float %call
+}
+
+define <2 x float> @test_powr_afn_v2f32__0(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32__0(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret <2 x float> splat (float 1.000000e+00)
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> zeroinitializer)
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_powr_afn_v2f32__1(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32__1(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret <2 x float> [[X]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> splat (float 1.0))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_powr_afn_v2f32__2(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32__2(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2:%.*]] = fmul afn <2 x float> [[X]], [[X]]
+; CHECK-NEXT: ret <2 x float> [[__POW2]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> splat (float 2.0))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_powr_afn_v2f32__3(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32__3(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 3.000000e+00))
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> splat (float 3.0))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_powr_afn_v2f32__8(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32__8(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 8.000000e+00))
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> splat (float 8.0))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_powr_afn_v2f32__neg1(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32__neg1(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POWRECIP:%.*]] = fdiv afn <2 x float> splat (float 1.000000e+00), [[X]]
+; CHECK-NEXT: ret <2 x float> [[__POWRECIP]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> splat (float -1.0))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_powr_afn_v2f32__half(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32__half(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2SQRT:%.*]] = call afn <2 x float> @_Z4sqrtDv2_f(<2 x float> [[X]])
+; CHECK-NEXT: ret <2 x float> [[__POW2SQRT]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> splat (float 0.5))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_powr_afn_v2f32__neghalf(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32__neghalf(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2RSQRT:%.*]] = call afn <2 x float> @_Z5rsqrtDv2_f(<2 x float> [[X]])
+; CHECK-NEXT: ret <2 x float> [[__POW2RSQRT]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> splat (float -0.5))
+ ret <2 x float> %call
+}
+
+define float @test__powr_fast_f32(float %x, float %y) #0 {
+; CHECK-LABEL: define float @test__powr_fast_f32(
+; CHECK-SAME: float [[X:%.*]], float [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z11__powr_fastff(float [[X]], float [[Y]])
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call float @_Z11__powr_fastff(float %x, float %y)
+ ret float %call
+}
+
+declare float @_Z11__powr_fastff(float, float) #1
+
+define <2 x float> @test__powr_fast_v2f32(<2 x float> %x, <2 x float> %y) #0 {
+; CHECK-LABEL: define <2 x float> @test__powr_fast_v2f32(
+; CHECK-SAME: <2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> %x, <2 x float> %y)
+ ret <2 x float> %call
+}
+
+declare <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float>, <2 x float>) #1
+
+define <3 x float> @test__powr_fast_v3f32(<3 x float> %x, <3 x float> %y) #0 {
+; CHECK-LABEL: define <3 x float> @test__powr_fast_v3f32(
+; CHECK-SAME: <3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <3 x float> @_Z11__powr_fastDv3_fS_(<3 x float> [[X]], <3 x float> [[Y]])
+; CHECK-NEXT: ret <3 x float> [[CALL]]
+;
+entry:
+ %call = tail call <3 x float> @_Z11__powr_fastDv3_fS_(<3 x float> %x, <3 x float> %y)
+ ret <3 x float> %call
+}
+
+declare <3 x float> @_Z11__powr_fastDv3_fS_(<3 x float>, <3 x float>) #1
+
+define <4 x float> @test__powr_fast_v4f32(<4 x float> %x, <4 x float> %y) #0 {
+; CHECK-LABEL: define <4 x float> @test__powr_fast_v4f32(
+; CHECK-SAME: <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <4 x float> @_Z11__powr_fastDv4_fS_(<4 x float> [[X]], <4 x float> [[Y]])
+; CHECK-NEXT: ret <4 x float> [[CALL]]
+;
+entry:
+ %call = tail call <4 x float> @_Z11__powr_fastDv4_fS_(<4 x float> %x, <4 x float> %y)
+ ret <4 x float> %call
+}
+
+declare <4 x float> @_Z11__powr_fastDv4_fS_(<4 x float>, <4 x float>) #1
+
+define <8 x float> @test__powr_fast_v8f32(<8 x float> %x, <8 x float> %y) #0 {
+; CHECK-LABEL: define <8 x float> @test__powr_fast_v8f32(
+; CHECK-SAME: <8 x float> [[X:%.*]], <8 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <8 x float> @_Z11__powr_fastDv8_fS_(<8 x float> [[X]], <8 x float> [[Y]])
+; CHECK-NEXT: ret <8 x float> [[CALL]]
+;
+entry:
+ %call = tail call <8 x float> @_Z11__powr_fastDv8_fS_(<8 x float> %x, <8 x float> %y)
+ ret <8 x float> %call
+}
+
+declare <8 x float> @_Z11__powr_fastDv8_fS_(<8 x float>, <8 x float>) #1
+
+define <16 x float> @test__powr_fast_v16f32(<16 x float> %x, <16 x float> %y) #0 {
+; CHECK-LABEL: define <16 x float> @test__powr_fast_v16f32(
+; CHECK-SAME: <16 x float> [[X:%.*]], <16 x float> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <16 x float> @_Z11__powr_fastDv16_fS_(<16 x float> [[X]], <16 x float> [[Y]])
+; CHECK-NEXT: ret <16 x float> [[CALL]]
+;
+entry:
+ %call = tail call <16 x float> @_Z11__powr_fastDv16_fS_(<16 x float> %x, <16 x float> %y)
+ ret <16 x float> %call
+}
+
+declare <16 x float> @_Z11__powr_fastDv16_fS_(<16 x float>, <16 x float>) #1
+
+define float @test__powr_fast_f32_known_integral_sitofp(float %x, i32 %y) {
+; CHECK-LABEL: define float @test__powr_fast_f32_known_integral_sitofp(
+; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
+; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z11__powr_fastff(float [[X]], float [[Y_CAST]])
+; CHECK-NEXT: ret float [[CALL]]
+;
+ %y.cast = sitofp i32 %y to float
+ %call = tail call float @_Z11__powr_fastff(float %x, float %y.cast)
+ ret float %call
+}
+
+define float @test__powr_fast_f32_0(float %x) #0 {
+; CHECK-LABEL: define float @test__powr_fast_f32_0(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret float 1.000000e+00
+;
+entry:
+ %call = tail call float @_Z11__powr_fastff(float %x, float 0.0)
+ ret float %call
+}
+
+define float @test__powr_fast_afn_f32_0(float %x) #0 {
+; CHECK-LABEL: define float @test__powr_fast_afn_f32_0(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret float 1.000000e+00
+;
+entry:
+ %call = tail call afn float @_Z11__powr_fastff(float %x, float 0.0)
+ ret float %call
+}
+
+define float @test__powr_fast_f32_2(float %x) #0 {
+; CHECK-LABEL: define float @test__powr_fast_f32_2(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2:%.*]] = fmul float [[X]], [[X]]
+; CHECK-NEXT: ret float [[__POW2]]
+;
+entry:
+ %call = tail call float @_Z11__powr_fastff(float %x, float 2.0)
+ ret float %call
+}
+
+define float @test__powr_fast_afn_f32_2(float %x) #0 {
+; CHECK-LABEL: define float @test__powr_fast_afn_f32_2(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__POW2:%.*]] = fmul afn float [[X]], [[X]]
+; CHECK-NEXT: ret float [[__POW2]]
+;
+entry:
+ %call = tail call afn float @_Z11__powr_fastff(float %x, float 2.0)
+ ret float %call
+}
+
+define double @test_powr_afn_f64(double %x, double %y) #0 {
+; CHECK-LABEL: define double @test_powr_afn_f64(
+; CHECK-SAME: double [[X:%.*]], double [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn double @_Z4powrdd(double [[X]], double [[Y]])
+; CHECK-NEXT: ret double [[CALL]]
+;
+entry:
+ %call = tail call afn double @_Z4powrdd(double %x, double %y)
+ ret double %call
+}
+
+declare double @_Z4powrdd(double, double) #0
+
+define <2 x double> @test_powr_afn_v2f64(<2 x double> %x, <2 x double> %y) #0 {
+; CHECK-LABEL: define <2 x double> @test_powr_afn_v2f64(
+; CHECK-SAME: <2 x double> [[X:%.*]], <2 x double> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x double> @_Z4powrDv2_dS_(<2 x double> [[X]], <2 x double> [[Y]])
+; CHECK-NEXT: ret <2 x double> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x double> @_Z4powrDv2_dS_(<2 x double> %x, <2 x double> %y)
+ ret <2 x double> %call
+}
+
+declare <2 x double> @_Z4powrDv2_dS_(<2 x double>, <2 x double>) #0
+
+define half @test_powr_afn_f16(half %x, half %y) #0 {
+; CHECK-LABEL: define half @test_powr_afn_f16(
+; CHECK-SAME: half [[X:%.*]], half [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn half @_Z4powrDhDh(half [[X]], half [[Y]])
+; CHECK-NEXT: ret half [[CALL]]
+;
+entry:
+ %call = tail call afn half @_Z4powrDhDh(half %x, half %y)
+ ret half %call
+}
+
+declare half @_Z4powrDhDh(half, half) #0
+
+define <2 x half> @test_powr_afn_v2f16(<2 x half> %x, <2 x half> %y) #0 {
+; CHECK-LABEL: define <2 x half> @test_powr_afn_v2f16(
+; CHECK-SAME: <2 x half> [[X:%.*]], <2 x half> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x half> @_Z4powrDv2_DhS_(<2 x half> [[X]], <2 x half> [[Y]])
+; CHECK-NEXT: ret <2 x half> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x half> @_Z4powrDv2_DhS_(<2 x half> %x, <2 x half> %y)
+ ret <2 x half> %call
+}
+
+declare <2 x half> @_Z4powrDv2_DhS_(<2 x half>, <2 x half>) #0
+
+attributes #0 = { mustprogress nofree norecurse nounwind willreturn memory(none) }
+attributes #1 = { mustprogress nofree nounwind willreturn memory(none) }
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll
index 4c6dbcc30ca35..d65fcdcc4d3fe 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-powr.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
-; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink %s | FileCheck %s
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink %s | FileCheck -check-prefixes=CHECK,PRELINK %s
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine %s | FileCheck -check-prefixes=CHECK,NOPRELINK %s
declare float @_Z4powrff(float, float)
declare <2 x float> @_Z4powrDv2_fS_(<2 x float>, <2 x float>)
@@ -45,243 +46,278 @@ define <2 x float> @test_powr_fast_v2f32(<2 x float> %x, <2 x float> %y) {
}
define float @test_powr_afn_f32(float %x, float %y) {
-; CHECK-LABEL: define float @test_powr_afn_f32
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn float [[Y]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn olt float [[Y]], 0.000000e+00
-; CHECK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float 0.000000e+00
-; CHECK-NEXT: [[TMP9:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[Y]], 0.000000e+00
-; CHECK-NEXT: [[TMP11:%.*]] = select afn i1 [[TMP10]], float 0x7FF8000000000000, float [[TMP8]]
-; CHECK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[TMP11]], float [[TMP6]]
-; CHECK-NEXT: [[TMP14:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP15:%.*]] = fcmp afn une float [[Y]], 0.000000e+00
-; CHECK-NEXT: [[TMP16:%.*]] = and i1 [[TMP14]], [[TMP15]]
-; CHECK-NEXT: [[TMP17:%.*]] = select afn i1 [[TMP16]], float [[TMP9]], float [[TMP13]]
-; CHECK-NEXT: [[TMP18:%.*]] = call afn float @llvm.fabs.f32(float [[Y]])
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp afn oeq float [[TMP18]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP20:%.*]] = fcmp afn une float [[TMP2]], 1.000000e+00
-; CHECK-NEXT: [[TMP21:%.*]] = and i1 [[TMP19]], [[TMP20]]
-; CHECK-NEXT: [[TMP22:%.*]] = fcmp afn olt float [[TMP2]], 1.000000e+00
-; CHECK-NEXT: [[TMP23:%.*]] = select afn i1 [[TMP22]], float [[TMP8]], float [[TMP9]]
-; CHECK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP21]], float [[TMP23]], float [[TMP17]]
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp afn uno float [[TMP2]], [[Y]]
-; CHECK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0x7FF8000000000000, float [[TMP24]]
-; CHECK-NEXT: ret float [[TMP26]]
+; PRELINK-LABEL: define float @test_powr_afn_f32
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[Y]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn olt float [[Y]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[Y]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn i1 [[TMP10]], float 0x7FF8000000000000, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[TMP11]], float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn une float [[Y]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = and i1 [[TMP14]], [[TMP15]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn i1 [[TMP16]], float [[TMP9]], float [[TMP13]]
+; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn float @llvm.fabs.f32(float [[Y]])
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq float [[TMP18]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une float [[TMP2]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP21:%.*]] = and i1 [[TMP19]], [[TMP20]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn olt float [[TMP2]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn i1 [[TMP22]], float [[TMP8]], float [[TMP9]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP21]], float [[TMP23]], float [[TMP17]]
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn uno float [[TMP2]], [[Y]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn i1 [[TMP25]], float 0x7FF8000000000000, float [[TMP24]]
+; NOPRELINK-NEXT: ret float [[TMP26]]
;
%powr = tail call afn float @_Z4powrff(float %x, float %y)
ret float %powr
}
define float @test_powr_afn_f32_nnan(float %x, float %y) {
-; CHECK-LABEL: define float @test_powr_afn_f32_nnan
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp nnan afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select nnan afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call nnan afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul nnan afn float [[Y]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp nnan afn olt float [[Y]], 0.000000e+00
-; CHECK-NEXT: [[TMP8:%.*]] = select nnan afn i1 [[TMP7]], float 0x7FF0000000000000, float 0.000000e+00
-; CHECK-NEXT: [[TMP9:%.*]] = select nnan afn i1 [[TMP7]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[Y]], 0.000000e+00
-; CHECK-NEXT: [[TMP11:%.*]] = select nnan afn i1 [[TMP10]], float 0x7FF8000000000000, float [[TMP8]]
-; CHECK-NEXT: [[TMP12:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP13:%.*]] = select nnan afn i1 [[TMP12]], float [[TMP11]], float [[TMP6]]
-; CHECK-NEXT: [[TMP14:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP15:%.*]] = fcmp nnan afn une float [[Y]], 0.000000e+00
-; CHECK-NEXT: [[TMP16:%.*]] = and i1 [[TMP14]], [[TMP15]]
-; CHECK-NEXT: [[TMP17:%.*]] = select nnan afn i1 [[TMP16]], float [[TMP9]], float [[TMP13]]
-; CHECK-NEXT: [[TMP18:%.*]] = call nnan afn float @llvm.fabs.f32(float [[Y]])
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp nnan afn oeq float [[TMP18]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP20:%.*]] = fcmp nnan afn une float [[TMP2]], 1.000000e+00
-; CHECK-NEXT: [[TMP21:%.*]] = and i1 [[TMP19]], [[TMP20]]
-; CHECK-NEXT: [[TMP22:%.*]] = fcmp nnan afn olt float [[TMP2]], 1.000000e+00
-; CHECK-NEXT: [[TMP23:%.*]] = select nnan afn i1 [[TMP22]], float [[TMP8]], float [[TMP9]]
-; CHECK-NEXT: [[TMP24:%.*]] = select nnan afn i1 [[TMP21]], float [[TMP23]], float [[TMP17]]
-; CHECK-NEXT: ret float [[TMP24]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_nnan
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call nnan afn float @_Z11__powr_fastff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_nnan
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp nnan afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select nnan afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call nnan afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul nnan afn float [[Y]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp nnan afn olt float [[Y]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan afn i1 [[TMP7]], float 0x7FF0000000000000, float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan afn i1 [[TMP7]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[Y]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select nnan afn i1 [[TMP10]], float 0x7FF8000000000000, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select nnan afn i1 [[TMP12]], float [[TMP11]], float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp nnan afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp nnan afn une float [[Y]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = and i1 [[TMP14]], [[TMP15]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = select nnan afn i1 [[TMP16]], float [[TMP9]], float [[TMP13]]
+; NOPRELINK-NEXT: [[TMP18:%.*]] = call nnan afn float @llvm.fabs.f32(float [[Y]])
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp nnan afn oeq float [[TMP18]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan afn une float [[TMP2]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP21:%.*]] = and i1 [[TMP19]], [[TMP20]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp nnan afn olt float [[TMP2]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select nnan afn i1 [[TMP22]], float [[TMP8]], float [[TMP9]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select nnan afn i1 [[TMP21]], float [[TMP23]], float [[TMP17]]
+; NOPRELINK-NEXT: ret float [[TMP24]]
;
%powr = tail call afn nnan float @_Z4powrff(float %x, float %y)
ret float %powr
}
define <2 x float> @test_powr_afn_v2f32(<2 x float> %x, <2 x float> %y) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32
-; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[Y]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn olt <2 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> zeroinitializer
-; CHECK-NEXT: [[TMP9:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP11:%.*]] = select afn <2 x i1> [[TMP10]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[TMP11]], <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP15:%.*]] = fcmp afn une <2 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP16:%.*]] = and <2 x i1> [[TMP14]], [[TMP15]]
-; CHECK-NEXT: [[TMP17:%.*]] = select afn <2 x i1> [[TMP16]], <2 x float> [[TMP9]], <2 x float> [[TMP13]]
-; CHECK-NEXT: [[TMP18:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[Y]])
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <2 x float> [[TMP18]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP20:%.*]] = fcmp afn une <2 x float> [[TMP2]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP21:%.*]] = and <2 x i1> [[TMP19]], [[TMP20]]
-; CHECK-NEXT: [[TMP22:%.*]] = fcmp afn olt <2 x float> [[TMP2]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP23:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> [[TMP8]], <2 x float> [[TMP9]]
-; CHECK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP21]], <2 x float> [[TMP23]], <2 x float> [[TMP17]]
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp afn uno <2 x float> [[TMP2]], [[Y]]
-; CHECK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP24]]
-; CHECK-NEXT: ret <2 x float> [[TMP26]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32
+; PRELINK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[Y]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn olt <2 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <2 x i1> [[TMP10]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[TMP11]], <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn une <2 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP16:%.*]] = and <2 x i1> [[TMP14]], [[TMP15]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn <2 x i1> [[TMP16]], <2 x float> [[TMP9]], <2 x float> [[TMP13]]
+; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[Y]])
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <2 x float> [[TMP18]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une <2 x float> [[TMP2]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = and <2 x i1> [[TMP19]], [[TMP20]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn olt <2 x float> [[TMP2]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> [[TMP8]], <2 x float> [[TMP9]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP21]], <2 x float> [[TMP23]], <2 x float> [[TMP17]]
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn uno <2 x float> [[TMP2]], [[Y]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <2 x i1> [[TMP25]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP24]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP26]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y)
ret <2 x float> %powr
}
define <3 x float> @test_powr_afn_v3f32(<3 x float> %x, <3 x float> %y) {
-; CHECK-LABEL: define <3 x float> @test_powr_afn_v3f32
-; CHECK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <3 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <3 x i1> [[TMP1]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <3 x float> @llvm.log2.v3f32(<3 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <3 x float> [[Y]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <3 x float> @llvm.exp2.v3f32(<3 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn olt <3 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <3 x i1> [[TMP7]], <3 x float> splat (float 0x7FF0000000000000), <3 x float> zeroinitializer
-; CHECK-NEXT: [[TMP9:%.*]] = select afn <3 x i1> [[TMP7]], <3 x float> zeroinitializer, <3 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <3 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP11:%.*]] = select afn <3 x i1> [[TMP10]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP13:%.*]] = select afn <3 x i1> [[TMP12]], <3 x float> [[TMP11]], <3 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP15:%.*]] = fcmp afn une <3 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP16:%.*]] = and <3 x i1> [[TMP14]], [[TMP15]]
-; CHECK-NEXT: [[TMP17:%.*]] = select afn <3 x i1> [[TMP16]], <3 x float> [[TMP9]], <3 x float> [[TMP13]]
-; CHECK-NEXT: [[TMP18:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[Y]])
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <3 x float> [[TMP18]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP20:%.*]] = fcmp afn une <3 x float> [[TMP2]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP21:%.*]] = and <3 x i1> [[TMP19]], [[TMP20]]
-; CHECK-NEXT: [[TMP22:%.*]] = fcmp afn olt <3 x float> [[TMP2]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP23:%.*]] = select afn <3 x i1> [[TMP22]], <3 x float> [[TMP8]], <3 x float> [[TMP9]]
-; CHECK-NEXT: [[TMP24:%.*]] = select afn <3 x i1> [[TMP21]], <3 x float> [[TMP23]], <3 x float> [[TMP17]]
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp afn uno <3 x float> [[TMP2]], [[Y]]
-; CHECK-NEXT: [[TMP26:%.*]] = select afn <3 x i1> [[TMP25]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP24]]
-; CHECK-NEXT: ret <3 x float> [[TMP26]]
+; PRELINK-LABEL: define <3 x float> @test_powr_afn_v3f32
+; PRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <3 x float> @_Z11__powr_fastDv3_fS_(<3 x float> [[X]], <3 x float> [[Y]])
+; PRELINK-NEXT: ret <3 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <3 x float> @test_powr_afn_v3f32
+; NOPRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <3 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <3 x i1> [[TMP1]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <3 x float> @llvm.log2.v3f32(<3 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <3 x float> [[Y]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <3 x float> @llvm.exp2.v3f32(<3 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn olt <3 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <3 x i1> [[TMP7]], <3 x float> splat (float 0x7FF0000000000000), <3 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <3 x i1> [[TMP7]], <3 x float> zeroinitializer, <3 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <3 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <3 x i1> [[TMP10]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <3 x i1> [[TMP12]], <3 x float> [[TMP11]], <3 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn une <3 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP16:%.*]] = and <3 x i1> [[TMP14]], [[TMP15]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn <3 x i1> [[TMP16]], <3 x float> [[TMP9]], <3 x float> [[TMP13]]
+; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[Y]])
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <3 x float> [[TMP18]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une <3 x float> [[TMP2]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = and <3 x i1> [[TMP19]], [[TMP20]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn olt <3 x float> [[TMP2]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn <3 x i1> [[TMP22]], <3 x float> [[TMP8]], <3 x float> [[TMP9]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <3 x i1> [[TMP21]], <3 x float> [[TMP23]], <3 x float> [[TMP17]]
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn uno <3 x float> [[TMP2]], [[Y]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <3 x i1> [[TMP25]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP24]]
+; NOPRELINK-NEXT: ret <3 x float> [[TMP26]]
;
%powr = tail call afn <3 x float> @_Z4powrDv3_fS_(<3 x float> %x, <3 x float> %y)
ret <3 x float> %powr
}
define <4 x float> @test_powr_afn_v4f32(<4 x float> %x, <4 x float> %y) {
-; CHECK-LABEL: define <4 x float> @test_powr_afn_v4f32
-; CHECK-SAME: (<4 x float> [[X:%.*]], <4 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <4 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <4 x i1> [[TMP1]], <4 x float> splat (float 0x7FF8000000000000), <4 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <4 x float> @llvm.log2.v4f32(<4 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <4 x float> [[Y]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <4 x float> @llvm.exp2.v4f32(<4 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn olt <4 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <4 x i1> [[TMP7]], <4 x float> splat (float 0x7FF0000000000000), <4 x float> zeroinitializer
-; CHECK-NEXT: [[TMP9:%.*]] = select afn <4 x i1> [[TMP7]], <4 x float> zeroinitializer, <4 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <4 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP11:%.*]] = select afn <4 x i1> [[TMP10]], <4 x float> splat (float 0x7FF8000000000000), <4 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <4 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP13:%.*]] = select afn <4 x i1> [[TMP12]], <4 x float> [[TMP11]], <4 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <4 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP15:%.*]] = fcmp afn une <4 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP16:%.*]] = and <4 x i1> [[TMP14]], [[TMP15]]
-; CHECK-NEXT: [[TMP17:%.*]] = select afn <4 x i1> [[TMP16]], <4 x float> [[TMP9]], <4 x float> [[TMP13]]
-; CHECK-NEXT: [[TMP18:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[Y]])
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <4 x float> [[TMP18]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP20:%.*]] = fcmp afn une <4 x float> [[TMP2]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP21:%.*]] = and <4 x i1> [[TMP19]], [[TMP20]]
-; CHECK-NEXT: [[TMP22:%.*]] = fcmp afn olt <4 x float> [[TMP2]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP23:%.*]] = select afn <4 x i1> [[TMP22]], <4 x float> [[TMP8]], <4 x float> [[TMP9]]
-; CHECK-NEXT: [[TMP24:%.*]] = select afn <4 x i1> [[TMP21]], <4 x float> [[TMP23]], <4 x float> [[TMP17]]
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp afn uno <4 x float> [[TMP2]], [[Y]]
-; CHECK-NEXT: [[TMP26:%.*]] = select afn <4 x i1> [[TMP25]], <4 x float> splat (float 0x7FF8000000000000), <4 x float> [[TMP24]]
-; CHECK-NEXT: ret <4 x float> [[TMP26]]
+; PRELINK-LABEL: define <4 x float> @test_powr_afn_v4f32
+; PRELINK-SAME: (<4 x float> [[X:%.*]], <4 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <4 x float> @_Z11__powr_fastDv4_fS_(<4 x float> [[X]], <4 x float> [[Y]])
+; PRELINK-NEXT: ret <4 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <4 x float> @test_powr_afn_v4f32
+; NOPRELINK-SAME: (<4 x float> [[X:%.*]], <4 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <4 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <4 x i1> [[TMP1]], <4 x float> splat (float 0x7FF8000000000000), <4 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <4 x float> @llvm.log2.v4f32(<4 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <4 x float> [[Y]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <4 x float> @llvm.exp2.v4f32(<4 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn olt <4 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <4 x i1> [[TMP7]], <4 x float> splat (float 0x7FF0000000000000), <4 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <4 x i1> [[TMP7]], <4 x float> zeroinitializer, <4 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <4 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <4 x i1> [[TMP10]], <4 x float> splat (float 0x7FF8000000000000), <4 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <4 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <4 x i1> [[TMP12]], <4 x float> [[TMP11]], <4 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <4 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn une <4 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP16:%.*]] = and <4 x i1> [[TMP14]], [[TMP15]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn <4 x i1> [[TMP16]], <4 x float> [[TMP9]], <4 x float> [[TMP13]]
+; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn <4 x float> @llvm.fabs.v4f32(<4 x float> [[Y]])
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <4 x float> [[TMP18]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une <4 x float> [[TMP2]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = and <4 x i1> [[TMP19]], [[TMP20]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn olt <4 x float> [[TMP2]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn <4 x i1> [[TMP22]], <4 x float> [[TMP8]], <4 x float> [[TMP9]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <4 x i1> [[TMP21]], <4 x float> [[TMP23]], <4 x float> [[TMP17]]
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn uno <4 x float> [[TMP2]], [[Y]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <4 x i1> [[TMP25]], <4 x float> splat (float 0x7FF8000000000000), <4 x float> [[TMP24]]
+; NOPRELINK-NEXT: ret <4 x float> [[TMP26]]
;
%powr = tail call afn <4 x float> @_Z4powrDv4_fS_(<4 x float> %x, <4 x float> %y)
ret <4 x float> %powr
}
define <8 x float> @test_powr_afn_v8f32(<8 x float> %x, <8 x float> %y) {
-; CHECK-LABEL: define <8 x float> @test_powr_afn_v8f32
-; CHECK-SAME: (<8 x float> [[X:%.*]], <8 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <8 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <8 x i1> [[TMP1]], <8 x float> splat (float 0x7FF8000000000000), <8 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <8 x float> @llvm.log2.v8f32(<8 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <8 x float> [[Y]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <8 x float> @llvm.exp2.v8f32(<8 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn olt <8 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <8 x i1> [[TMP7]], <8 x float> splat (float 0x7FF0000000000000), <8 x float> zeroinitializer
-; CHECK-NEXT: [[TMP9:%.*]] = select afn <8 x i1> [[TMP7]], <8 x float> zeroinitializer, <8 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <8 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP11:%.*]] = select afn <8 x i1> [[TMP10]], <8 x float> splat (float 0x7FF8000000000000), <8 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <8 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP13:%.*]] = select afn <8 x i1> [[TMP12]], <8 x float> [[TMP11]], <8 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <8 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP15:%.*]] = fcmp afn une <8 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP16:%.*]] = and <8 x i1> [[TMP14]], [[TMP15]]
-; CHECK-NEXT: [[TMP17:%.*]] = select afn <8 x i1> [[TMP16]], <8 x float> [[TMP9]], <8 x float> [[TMP13]]
-; CHECK-NEXT: [[TMP18:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[Y]])
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <8 x float> [[TMP18]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP20:%.*]] = fcmp afn une <8 x float> [[TMP2]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP21:%.*]] = and <8 x i1> [[TMP19]], [[TMP20]]
-; CHECK-NEXT: [[TMP22:%.*]] = fcmp afn olt <8 x float> [[TMP2]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP23:%.*]] = select afn <8 x i1> [[TMP22]], <8 x float> [[TMP8]], <8 x float> [[TMP9]]
-; CHECK-NEXT: [[TMP24:%.*]] = select afn <8 x i1> [[TMP21]], <8 x float> [[TMP23]], <8 x float> [[TMP17]]
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp afn uno <8 x float> [[TMP2]], [[Y]]
-; CHECK-NEXT: [[TMP26:%.*]] = select afn <8 x i1> [[TMP25]], <8 x float> splat (float 0x7FF8000000000000), <8 x float> [[TMP24]]
-; CHECK-NEXT: ret <8 x float> [[TMP26]]
+; PRELINK-LABEL: define <8 x float> @test_powr_afn_v8f32
+; PRELINK-SAME: (<8 x float> [[X:%.*]], <8 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <8 x float> @_Z11__powr_fastDv8_fS_(<8 x float> [[X]], <8 x float> [[Y]])
+; PRELINK-NEXT: ret <8 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <8 x float> @test_powr_afn_v8f32
+; NOPRELINK-SAME: (<8 x float> [[X:%.*]], <8 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <8 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <8 x i1> [[TMP1]], <8 x float> splat (float 0x7FF8000000000000), <8 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <8 x float> @llvm.log2.v8f32(<8 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <8 x float> [[Y]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <8 x float> @llvm.exp2.v8f32(<8 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn olt <8 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <8 x i1> [[TMP7]], <8 x float> splat (float 0x7FF0000000000000), <8 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <8 x i1> [[TMP7]], <8 x float> zeroinitializer, <8 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <8 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <8 x i1> [[TMP10]], <8 x float> splat (float 0x7FF8000000000000), <8 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <8 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <8 x i1> [[TMP12]], <8 x float> [[TMP11]], <8 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <8 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn une <8 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP16:%.*]] = and <8 x i1> [[TMP14]], [[TMP15]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn <8 x i1> [[TMP16]], <8 x float> [[TMP9]], <8 x float> [[TMP13]]
+; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn <8 x float> @llvm.fabs.v8f32(<8 x float> [[Y]])
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <8 x float> [[TMP18]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une <8 x float> [[TMP2]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = and <8 x i1> [[TMP19]], [[TMP20]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn olt <8 x float> [[TMP2]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn <8 x i1> [[TMP22]], <8 x float> [[TMP8]], <8 x float> [[TMP9]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <8 x i1> [[TMP21]], <8 x float> [[TMP23]], <8 x float> [[TMP17]]
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn uno <8 x float> [[TMP2]], [[Y]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <8 x i1> [[TMP25]], <8 x float> splat (float 0x7FF8000000000000), <8 x float> [[TMP24]]
+; NOPRELINK-NEXT: ret <8 x float> [[TMP26]]
;
%powr = tail call afn <8 x float> @_Z4powrDv8_fS_(<8 x float> %x, <8 x float> %y)
ret <8 x float> %powr
}
define <16 x float> @test_powr_afn_v16f32(<16 x float> %x, <16 x float> %y) {
-; CHECK-LABEL: define <16 x float> @test_powr_afn_v16f32
-; CHECK-SAME: (<16 x float> [[X:%.*]], <16 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <16 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <16 x i1> [[TMP1]], <16 x float> splat (float 0x7FF8000000000000), <16 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <16 x float> @llvm.log2.v16f32(<16 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <16 x float> [[Y]], [[TMP4]]
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <16 x float> @llvm.exp2.v16f32(<16 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn olt <16 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <16 x i1> [[TMP7]], <16 x float> splat (float 0x7FF0000000000000), <16 x float> zeroinitializer
-; CHECK-NEXT: [[TMP9:%.*]] = select afn <16 x i1> [[TMP7]], <16 x float> zeroinitializer, <16 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <16 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP11:%.*]] = select afn <16 x i1> [[TMP10]], <16 x float> splat (float 0x7FF8000000000000), <16 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <16 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP13:%.*]] = select afn <16 x i1> [[TMP12]], <16 x float> [[TMP11]], <16 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <16 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP15:%.*]] = fcmp afn une <16 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP16:%.*]] = and <16 x i1> [[TMP14]], [[TMP15]]
-; CHECK-NEXT: [[TMP17:%.*]] = select afn <16 x i1> [[TMP16]], <16 x float> [[TMP9]], <16 x float> [[TMP13]]
-; CHECK-NEXT: [[TMP18:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[Y]])
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <16 x float> [[TMP18]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP20:%.*]] = fcmp afn une <16 x float> [[TMP2]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP21:%.*]] = and <16 x i1> [[TMP19]], [[TMP20]]
-; CHECK-NEXT: [[TMP22:%.*]] = fcmp afn olt <16 x float> [[TMP2]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP23:%.*]] = select afn <16 x i1> [[TMP22]], <16 x float> [[TMP8]], <16 x float> [[TMP9]]
-; CHECK-NEXT: [[TMP24:%.*]] = select afn <16 x i1> [[TMP21]], <16 x float> [[TMP23]], <16 x float> [[TMP17]]
-; CHECK-NEXT: [[TMP25:%.*]] = fcmp afn uno <16 x float> [[TMP2]], [[Y]]
-; CHECK-NEXT: [[TMP26:%.*]] = select afn <16 x i1> [[TMP25]], <16 x float> splat (float 0x7FF8000000000000), <16 x float> [[TMP24]]
-; CHECK-NEXT: ret <16 x float> [[TMP26]]
+; PRELINK-LABEL: define <16 x float> @test_powr_afn_v16f32
+; PRELINK-SAME: (<16 x float> [[X:%.*]], <16 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <16 x float> @_Z11__powr_fastDv16_fS_(<16 x float> [[X]], <16 x float> [[Y]])
+; PRELINK-NEXT: ret <16 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <16 x float> @test_powr_afn_v16f32
+; NOPRELINK-SAME: (<16 x float> [[X:%.*]], <16 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <16 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <16 x i1> [[TMP1]], <16 x float> splat (float 0x7FF8000000000000), <16 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <16 x float> @llvm.log2.v16f32(<16 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <16 x float> [[Y]], [[TMP4]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <16 x float> @llvm.exp2.v16f32(<16 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn olt <16 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <16 x i1> [[TMP7]], <16 x float> splat (float 0x7FF0000000000000), <16 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <16 x i1> [[TMP7]], <16 x float> zeroinitializer, <16 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <16 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <16 x i1> [[TMP10]], <16 x float> splat (float 0x7FF8000000000000), <16 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <16 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn <16 x i1> [[TMP12]], <16 x float> [[TMP11]], <16 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq <16 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn une <16 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP16:%.*]] = and <16 x i1> [[TMP14]], [[TMP15]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn <16 x i1> [[TMP16]], <16 x float> [[TMP9]], <16 x float> [[TMP13]]
+; NOPRELINK-NEXT: [[TMP18:%.*]] = call afn <16 x float> @llvm.fabs.v16f32(<16 x float> [[Y]])
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn oeq <16 x float> [[TMP18]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn une <16 x float> [[TMP2]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = and <16 x i1> [[TMP19]], [[TMP20]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = fcmp afn olt <16 x float> [[TMP2]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn <16 x i1> [[TMP22]], <16 x float> [[TMP8]], <16 x float> [[TMP9]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <16 x i1> [[TMP21]], <16 x float> [[TMP23]], <16 x float> [[TMP17]]
+; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp afn uno <16 x float> [[TMP2]], [[Y]]
+; NOPRELINK-NEXT: [[TMP26:%.*]] = select afn <16 x i1> [[TMP25]], <16 x float> splat (float 0x7FF8000000000000), <16 x float> [[TMP24]]
+; NOPRELINK-NEXT: ret <16 x float> [[TMP26]]
;
%powr = tail call afn <16 x float> @_Z4powrDv16_fS_(<16 x float> %x, <16 x float> %y)
ret <16 x float> %powr
@@ -598,69 +634,104 @@ define <16 x half> @test_powr_v16f16(<16 x half> %x, <16 x half> %y) {
}
define float @test_powr_afn_f32_minsize(float %x, float %y) #0 {
-; CHECK-LABEL: define float @test_powr_afn_f32_minsize
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: [[POWR:%.*]] = tail call afn float @_Z4powrff(float [[X]], float [[Y]])
-; CHECK-NEXT: ret float [[POWR]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_minsize
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_minsize
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
+; NOPRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z4powrff(float [[X]], float [[Y]])
+; NOPRELINK-NEXT: ret float [[POWR]]
;
%powr = tail call afn float @_Z4powrff(float %x, float %y)
ret float %powr
}
define float @test_powr_afn_f32_nnan_minsize(float %x, float %y) #0 {
-; CHECK-LABEL: define float @test_powr_afn_f32_nnan_minsize
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: [[POWR:%.*]] = tail call nnan afn float @_Z4powrff(float [[X]], float [[Y]])
-; CHECK-NEXT: ret float [[POWR]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_nnan_minsize
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR0]] {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call nnan afn float @_Z11__powr_fastff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_nnan_minsize
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR0]] {
+; NOPRELINK-NEXT: [[POWR:%.*]] = tail call nnan afn float @_Z4powrff(float [[X]], float [[Y]])
+; NOPRELINK-NEXT: ret float [[POWR]]
;
%powr = tail call afn nnan float @_Z4powrff(float %x, float %y)
ret float %powr
}
define float @test_powr_afn_f32_noinline(float %x, float %y) {
-; CHECK-LABEL: define float @test_powr_afn_f32_noinline
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[POWR:%.*]] = tail call afn float @_Z4powrff(float [[X]], float [[Y]]) #[[ATTR4:[0-9]+]]
-; CHECK-NEXT: ret float [[POWR]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_noinline
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float [[Y]]) #[[ATTR4:[0-9]+]]
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_noinline
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z4powrff(float [[X]], float [[Y]]) #[[ATTR3:[0-9]+]]
+; NOPRELINK-NEXT: ret float [[POWR]]
;
%powr = tail call afn float @_Z4powrff(float %x, float %y) #1
ret float %powr
}
define float @test_powr_afn_f32_nnan_noinline(float %x, float %y) {
-; CHECK-LABEL: define float @test_powr_afn_f32_nnan_noinline
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[POWR:%.*]] = tail call nnan afn float @_Z4powrff(float [[X]], float [[Y]]) #[[ATTR4]]
-; CHECK-NEXT: ret float [[POWR]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_nnan_noinline
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call nnan afn float @_Z11__powr_fastff(float [[X]], float [[Y]]) #[[ATTR4]]
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_nnan_noinline
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POWR:%.*]] = tail call nnan afn float @_Z4powrff(float [[X]], float [[Y]]) #[[ATTR3]]
+; NOPRELINK-NEXT: ret float [[POWR]]
;
%powr = tail call afn nnan float @_Z4powrff(float %x, float %y) #1
ret float %powr
}
define float @test_powr_afn_f32_strictfp(float %x, float %y) #2 {
-; CHECK-LABEL: define float @test_powr_afn_f32_strictfp
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR1:[0-9]+]] {
-; CHECK-NEXT: [[POWR:%.*]] = tail call nnan nsz afn float @_Z4powrff(float [[X]], float [[Y]]) #[[ATTR1]]
-; CHECK-NEXT: ret float [[POWR]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_strictfp
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR1:[0-9]+]] {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call nnan nsz afn float @_Z11__powr_fastff(float [[X]], float [[Y]]) #[[ATTR1]]
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_strictfp
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) #[[ATTR1:[0-9]+]] {
+; NOPRELINK-NEXT: [[POWR:%.*]] = tail call nnan nsz afn float @_Z4powrff(float [[X]], float [[Y]]) #[[ATTR1]]
+; NOPRELINK-NEXT: ret float [[POWR]]
;
%powr = tail call afn nsz nnan float @_Z4powrff(float %x, float %y) #2
ret float %powr
}
define float @test_powr_fast_f32_nobuiltin(float %x, float %y) {
-; CHECK-LABEL: define float @test_powr_fast_f32_nobuiltin
-; CHECK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[POWR:%.*]] = tail call fast float @_Z4powrff(float [[X]], float [[Y]]) #[[ATTR5:[0-9]+]]
-; CHECK-NEXT: ret float [[POWR]]
+; PRELINK-LABEL: define float @test_powr_fast_f32_nobuiltin
+; PRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call fast float @_Z4powrff(float [[X]], float [[Y]]) #[[ATTR5:[0-9]+]]
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_fast_f32_nobuiltin
+; NOPRELINK-SAME: (float [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[POWR:%.*]] = tail call fast float @_Z4powrff(float [[X]], float [[Y]]) #[[ATTR4:[0-9]+]]
+; NOPRELINK-NEXT: ret float [[POWR]]
;
%powr = tail call fast float @_Z4powrff(float %x, float %y) #3
ret float %powr
}
define float @test_powr_afn_f32_poison(float %x) {
-; CHECK-LABEL: define float @test_powr_afn_f32_poison
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: ret float poison
+; PRELINK-LABEL: define float @test_powr_afn_f32_poison
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float poison)
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_poison
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: ret float poison
;
%powr = tail call afn float @_Z4powrff(float %x, float poison)
ret float %powr
@@ -703,17 +774,22 @@ define <2 x float> @test_powr_afn_v2f32_neg0.0(<2 x float> %x) {
}
define <2 x float> @test_powr_afn_v2f32_plus_minus_0.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_0.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 0.000000e+00, float -0.000000e+00>
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn ueq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP6]]
-; CHECK-NEXT: ret <2 x float> [[TMP8]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_0.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 0.000000e+00, float -0.000000e+00>)
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_0.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 0.000000e+00, float -0.000000e+00>
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn ueq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP8]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0.0, float -0.0>)
ret <2 x float> %powr
@@ -738,81 +814,182 @@ define <3 x float> @test_powr_afn_v3f32_neg0.0_splat_undef(<3 x float> %x, <3 x
}
define float @test_powr_afn_f32_0.5(float %x) {
-; CHECK-LABEL: define float @test_powr_afn_f32_0.5
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[__POW2SQRT:%.*]] = call afn float @_Z4sqrtf(float [[X]])
-; CHECK-NEXT: ret float [[__POW2SQRT]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_0.5
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[__POW2SQRT:%.*]] = call afn float @_Z4sqrtf(float [[X]])
+; PRELINK-NEXT: ret float [[__POW2SQRT]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_0.5
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 5.000000e-01
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 0.5)
ret float %powr
}
define float @test_powr_afn_f32_neg0.5(float %x) {
-; CHECK-LABEL: define float @test_powr_afn_f32_neg0.5
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[__POW2RSQRT:%.*]] = call afn float @_Z5rsqrtf(float [[X]])
-; CHECK-NEXT: ret float [[__POW2RSQRT]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_neg0.5
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[__POW2RSQRT:%.*]] = call afn float @_Z5rsqrtf(float [[X]])
+; PRELINK-NEXT: ret float [[__POW2RSQRT]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg0.5
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -5.000000e-01
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -0.5)
ret float %powr
}
define <2 x float> @test_powr_afn_v2f32_0.5(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_0.5
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[__POW2SQRT:%.*]] = call afn <2 x float> @_Z4sqrtDv2_f(<2 x float> [[X]])
-; CHECK-NEXT: ret <2 x float> [[__POW2SQRT]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_0.5
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[__POW2SQRT:%.*]] = call afn <2 x float> @_Z4sqrtDv2_f(<2 x float> [[X]])
+; PRELINK-NEXT: ret <2 x float> [[__POW2SQRT]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_0.5
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 5.000000e-01)
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0.5, float 0.5>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_neg0.5(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg0.5
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[__POW2RSQRT:%.*]] = call afn <2 x float> @_Z5rsqrtDv2_f(<2 x float> [[X]])
-; CHECK-NEXT: ret <2 x float> [[__POW2RSQRT]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg0.5
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[__POW2RSQRT:%.*]] = call afn <2 x float> @_Z5rsqrtDv2_f(<2 x float> [[X]])
+; PRELINK-NEXT: ret <2 x float> [[__POW2RSQRT]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg0.5
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -5.000000e-01)
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -0.5, float -0.5>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_plus_minus_0.5(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_0.5
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 5.000000e-01, float -5.000000e-01>
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_0.5
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 5.000000e-01, float -5.000000e-01>)
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_0.5
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 5.000000e-01, float -5.000000e-01>
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0.5, float -0.5>)
ret <2 x float> %powr
}
define <3 x float> @test_powr_afn_v3f32_0.5_splat_undef(<3 x float> %x, <3 x float> %y) {
-; CHECK-LABEL: define <3 x float> @test_powr_afn_v3f32_0.5_splat_undef
-; CHECK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[__POW2SQRT:%.*]] = call afn <3 x float> @_Z4sqrtDv3_f(<3 x float> [[X]])
-; CHECK-NEXT: ret <3 x float> [[__POW2SQRT]]
+; PRELINK-LABEL: define <3 x float> @test_powr_afn_v3f32_0.5_splat_undef
+; PRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[__POW2SQRT:%.*]] = call afn <3 x float> @_Z4sqrtDv3_f(<3 x float> [[X]])
+; PRELINK-NEXT: ret <3 x float> [[__POW2SQRT]]
+;
+; NOPRELINK-LABEL: define <3 x float> @test_powr_afn_v3f32_0.5_splat_undef
+; NOPRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <3 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <3 x i1> [[TMP1]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <3 x float> @llvm.log2.v3f32(<3 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <3 x float> [[TMP4]], <float 5.000000e-01, float poison, float 5.000000e-01>
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <3 x float> @llvm.exp2.v3f32(<3 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <3 x i1> [[TMP7]], <3 x float> <float 0.000000e+00, float poison, float 0.000000e+00>, <3 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <3 x i1> [[TMP9]], <3 x float> <float 0x7FF0000000000000, float poison, float 0x7FF0000000000000>, <3 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <3 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <3 x i1> [[TMP11]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <3 x float> [[TMP12]]
;
%powr = tail call afn <3 x float> @_Z4powrDv3_fS_(<3 x float> %x, <3 x float> <float 0.5, float poison, float 0.5>)
ret <3 x float> %powr
}
define <3 x float> @test_powr_afn_v3f32_neg0.5_splat_undef(<3 x float> %x, <3 x float> %y) {
-; CHECK-LABEL: define <3 x float> @test_powr_afn_v3f32_neg0.5_splat_undef
-; CHECK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[__POW2RSQRT:%.*]] = call afn <3 x float> @_Z5rsqrtDv3_f(<3 x float> [[X]])
-; CHECK-NEXT: ret <3 x float> [[__POW2RSQRT]]
+; PRELINK-LABEL: define <3 x float> @test_powr_afn_v3f32_neg0.5_splat_undef
+; PRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[__POW2RSQRT:%.*]] = call afn <3 x float> @_Z5rsqrtDv3_f(<3 x float> [[X]])
+; PRELINK-NEXT: ret <3 x float> [[__POW2RSQRT]]
+;
+; NOPRELINK-LABEL: define <3 x float> @test_powr_afn_v3f32_neg0.5_splat_undef
+; NOPRELINK-SAME: (<3 x float> [[X:%.*]], <3 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <3 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <3 x i1> [[TMP1]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <3 x float> @llvm.fabs.v3f32(<3 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <3 x float> @llvm.log2.v3f32(<3 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <3 x float> [[TMP4]], <float -5.000000e-01, float poison, float -5.000000e-01>
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <3 x float> @llvm.exp2.v3f32(<3 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <3 x i1> [[TMP7]], <3 x float> <float 0x7FF0000000000000, float poison, float 0x7FF0000000000000>, <3 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <3 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <3 x i1> [[TMP9]], <3 x float> <float 0.000000e+00, float poison, float 0.000000e+00>, <3 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <3 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <3 x i1> [[TMP11]], <3 x float> splat (float 0x7FF8000000000000), <3 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <3 x float> [[TMP12]]
;
%powr = tail call afn <3 x float> @_Z4powrDv3_fS_(<3 x float> %x, <3 x float> <float -0.5, float poison, float -0.5>)
ret <3 x float> %powr
@@ -857,21 +1034,26 @@ define <2 x float> @test_powr_afn_v2f32_neg1.0(<2 x float> %x) {
}
define <2 x float> @test_powr_afn_v2f32_plus_minus_1.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_1.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 1.000000e+00, float -1.000000e+00>
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_1.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 1.000000e+00, float -1.000000e+00>)
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_1.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 1.000000e+00, float -1.000000e+00>
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 1.0, float -1.0>)
ret <2 x float> %powr
@@ -907,21 +1089,26 @@ define float @test_powr_afn_f32_2.0(float %x) {
}
define float @test_powr_afn_f32_neg2.0(float %x) {
-; CHECK-LABEL: define float @test_powr_afn_f32_neg2.0
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -2.000000e+00
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
-; CHECK-NEXT: ret float [[TMP12]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_neg2.0
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float -2.000000e+00)
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg2.0
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -2.000000e+00
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -2.0)
ret float %powr
@@ -938,598 +1125,738 @@ define <2 x float> @test_powr_afn_v2f32_2.0(<2 x float> %x) {
}
define <2 x float> @test_powr_afn_v2f32_neg2.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg2.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -2.000000e+00)
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg2.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float -2.000000e+00))
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg2.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -2.000000e+00)
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -2.0, float -2.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_plus_minus_2.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_2.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 2.000000e+00, float -2.000000e+00>
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_2.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 2.000000e+00, float -2.000000e+00>)
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_2.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 2.000000e+00, float -2.000000e+00>
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 2.0, float -2.0>)
ret <2 x float> %powr
}
define float @test_powr_afn_f32_3.0(float %x) {
-; CHECK-LABEL: define float @test_powr_afn_f32_3.0
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 3.000000e+00
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
-; CHECK-NEXT: ret float [[TMP12]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_3.0
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float 3.000000e+00)
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_3.0
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 3.000000e+00
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 3.0)
ret float %powr
}
define float @test_powr_afn_f32_neg3.0(float %x) {
-; CHECK-LABEL: define float @test_powr_afn_f32_neg3.0
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -3.000000e+00
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
-; CHECK-NEXT: ret float [[TMP12]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_neg3.0
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float -3.000000e+00)
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg3.0
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -3.000000e+00
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -3.0)
ret float %powr
}
define <2 x float> @test_powr_afn_v2f32_3.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_3.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 3.000000e+00)
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_3.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 3.000000e+00))
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_3.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 3.000000e+00)
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 3.0, float 3.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_neg3.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg3.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -3.000000e+00)
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg3.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float -3.000000e+00))
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg3.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -3.000000e+00)
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -3.0, float -3.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_plus_minus_3.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_3.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 3.000000e+00, float -3.000000e+00>
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_3.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 3.000000e+00, float -3.000000e+00>)
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_3.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 3.000000e+00, float -3.000000e+00>
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 3.0, float -3.0>)
ret <2 x float> %powr
}
define float @test_powr_afn_f32_3.99(float %x) {
-; CHECK-LABEL: define float @test_powr_afn_f32_3.99
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 0x400FEB8520000000
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
-; CHECK-NEXT: ret float [[TMP12]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_3.99
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float 0x400FEB8520000000)
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_3.99
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 0x400FEB8520000000
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 0x400FEB8520000000)
ret float %powr
}
define float @test_powr_afn_f32_neg3.99(float %x) {
-; CHECK-LABEL: define float @test_powr_afn_f32_neg3.99
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 0xC00FEB8520000000
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
-; CHECK-NEXT: ret float [[TMP12]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_neg3.99
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float 0xC00FEB8520000000)
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg3.99
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 0xC00FEB8520000000
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 0xC00FEB8520000000)
ret float %powr
}
define <2 x float> @test_powr_afn_v2f32_3.99(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_3.99
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 0x400FEB8520000000)
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_3.99
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 0x400FEB8520000000))
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_3.99
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 0x400FEB8520000000)
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0x400FEB8520000000, float 0x400FEB8520000000>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_neg3.99(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg3.99
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 0xC00FEB8520000000)
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg3.99
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 0xC00FEB8520000000))
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg3.99
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 0xC00FEB8520000000)
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0xC00FEB8520000000, float 0xC00FEB8520000000>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_plus_minus_3.99(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_3.99
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 0x400FEB8520000000, float 0xC00FEB8520000000>
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_3.99
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 0x400FEB8520000000, float 0xC00FEB8520000000>)
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_3.99
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 0x400FEB8520000000, float 0xC00FEB8520000000>
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 0x400FEB8520000000, float 0xC00FEB8520000000>)
ret <2 x float> %powr
}
define float @test_powr_afn_f32_8.0(float %x) {
-; CHECK-LABEL: define float @test_powr_afn_f32_8.0
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 8.000000e+00
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
-; CHECK-NEXT: ret float [[TMP12]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_8.0
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float 8.000000e+00)
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_8.0
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 8.000000e+00
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 8.0)
ret float %powr
}
define float @test_powr_afn_f32_neg8.0(float %x) {
-; CHECK-LABEL: define float @test_powr_afn_f32_neg8.0
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -8.000000e+00
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
-; CHECK-NEXT: ret float [[TMP12]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_neg8.0
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float -8.000000e+00)
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg8.0
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -8.000000e+00
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -8.0)
ret float %powr
}
define <2 x float> @test_powr_afn_v2f32_8.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_8.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 8.000000e+00)
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_8.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 8.000000e+00))
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_8.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 8.000000e+00)
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 8.0, float 8.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_neg8.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg8.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -8.000000e+00)
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg8.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float -8.000000e+00))
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg8.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -8.000000e+00)
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -8.0, float -8.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_plus_minus_8.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_8.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 8.000000e+00, float -8.000000e+00>
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_8.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 8.000000e+00, float -8.000000e+00>)
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_8.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 8.000000e+00, float -8.000000e+00>
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 8.0, float -8.0>)
ret <2 x float> %powr
}
define float @test_powr_afn_f32_12.0(float %x) {
-; CHECK-LABEL: define float @test_powr_afn_f32_12.0
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 1.200000e+01
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
-; CHECK-NEXT: ret float [[TMP12]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_12.0
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float 1.200000e+01)
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_12.0
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 1.200000e+01
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 12.0)
ret float %powr
}
define float @test_powr_afn_f32_neg12.0(float %x) {
-; CHECK-LABEL: define float @test_powr_afn_f32_neg12.0
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -1.200000e+01
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
-; CHECK-NEXT: ret float [[TMP12]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_neg12.0
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float -1.200000e+01)
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg12.0
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -1.200000e+01
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -12.0)
ret float %powr
}
define <2 x float> @test_powr_afn_v2f32_12.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_12.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 1.200000e+01)
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_12.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 1.200000e+01))
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_12.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 1.200000e+01)
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 12.0, float 12.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_neg12.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg12.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -1.200000e+01)
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg12.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float -1.200000e+01))
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg12.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -1.200000e+01)
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -12.0, float -12.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_plus_minus_12.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_12.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 1.200000e+01, float -1.200000e+01>
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_12.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 1.200000e+01, float -1.200000e+01>)
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_12.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 1.200000e+01, float -1.200000e+01>
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 12.0, float -12.0>)
ret <2 x float> %powr
}
define float @test_powr_afn_f32_13.0(float %x) {
-; CHECK-LABEL: define float @test_powr_afn_f32_13.0
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 1.300000e+01
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
-; CHECK-NEXT: ret float [[TMP12]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_13.0
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float 1.300000e+01)
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_13.0
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], 1.300000e+01
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0x7FF0000000000000, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float 13.0)
ret float %powr
}
define float @test_powr_afn_f32_neg13.0(float %x) {
-; CHECK-LABEL: define float @test_powr_afn_f32_neg13.0
-; CHECK-SAME: (float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -1.300000e+01
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
-; CHECK-NEXT: ret float [[TMP12]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_neg13.0
+; PRELINK-SAME: (float [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float -1.300000e+01)
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_neg13.0
+; NOPRELINK-SAME: (float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], -1.300000e+01
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float 0.000000e+00, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: ret float [[TMP12]]
;
%powr = tail call afn float @_Z4powrff(float %x, float -13.0)
ret float %powr
}
define <2 x float> @test_powr_afn_v2f32_13.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_13.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 1.300000e+01)
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_13.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float 1.300000e+01))
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_13.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float 1.300000e+01)
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> zeroinitializer, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 13.0, float 13.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_neg13.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg13.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -1.300000e+01)
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg13.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> splat (float -1.300000e+01))
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_neg13.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], splat (float -1.300000e+01)
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> zeroinitializer, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float -13.0, float -13.0>)
ret <2 x float> %powr
}
define <2 x float> @test_powr_afn_v2f32_plus_minus_13.0(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_13.0
-; CHECK-SAME: (<2 x float> [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 1.300000e+01, float -1.300000e+01>
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: ret <2 x float> [[TMP12]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_13.0
+; PRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> <float 1.300000e+01, float -1.300000e+01>)
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_plus_minus_13.0
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], <float 1.300000e+01, float -1.300000e+01>
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> <float 0.000000e+00, float 0x7FF0000000000000>, <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> <float 0x7FF0000000000000, float 0.000000e+00>, <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select afn <2 x i1> [[TMP11]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP12]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> <float 13.0, float -13.0>)
ret <2 x float> %powr
}
define float @test_powr_afn_f32_nnan_x_known_positive(float nofpclass(ninf nnorm nsub) %x, float %y) {
-; CHECK-LABEL: define float @test_powr_afn_f32_nnan_x_known_positive
-; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul nnan afn float [[Y]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fcmp nnan afn olt float [[Y]], 0.000000e+00
-; CHECK-NEXT: [[TMP6:%.*]] = select nnan afn i1 [[TMP5]], float 0x7FF0000000000000, float 0.000000e+00
-; CHECK-NEXT: [[TMP7:%.*]] = select nnan afn i1 [[TMP5]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp nnan afn oeq float [[Y]], 0.000000e+00
-; CHECK-NEXT: [[TMP9:%.*]] = select nnan afn i1 [[TMP8]], float 0x7FF8000000000000, float [[TMP6]]
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP11:%.*]] = select nnan afn i1 [[TMP10]], float [[TMP9]], float [[TMP4]]
-; CHECK-NEXT: [[TMP12:%.*]] = fcmp nnan afn oeq float [[X]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une float [[Y]], 0.000000e+00
-; CHECK-NEXT: [[TMP14:%.*]] = and i1 [[TMP12]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP7]], float [[TMP11]]
-; CHECK-NEXT: [[TMP16:%.*]] = call nnan afn float @llvm.fabs.f32(float [[Y]])
-; CHECK-NEXT: [[TMP17:%.*]] = fcmp nnan afn oeq float [[TMP16]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[X]], 1.000000e+00
-; CHECK-NEXT: [[TMP19:%.*]] = and i1 [[TMP17]], [[TMP18]]
-; CHECK-NEXT: [[TMP20:%.*]] = fcmp nnan afn olt float [[X]], 1.000000e+00
-; CHECK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float [[TMP6]], float [[TMP7]]
-; CHECK-NEXT: [[TMP22:%.*]] = select nnan afn i1 [[TMP19]], float [[TMP21]], float [[TMP15]]
-; CHECK-NEXT: ret float [[TMP22]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_nnan_x_known_positive
+; PRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call nnan afn float @_Z11__powr_fastff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_nnan_x_known_positive
+; NOPRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan afn float @llvm.log2.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan afn float [[Y]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan afn float @llvm.exp2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan afn olt float [[Y]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan afn i1 [[TMP5]], float 0x7FF0000000000000, float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan afn i1 [[TMP5]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp nnan afn oeq float [[Y]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan afn i1 [[TMP8]], float 0x7FF8000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select nnan afn i1 [[TMP10]], float [[TMP9]], float [[TMP4]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp nnan afn oeq float [[X]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une float [[Y]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP12]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan afn i1 [[TMP14]], float [[TMP7]], float [[TMP11]]
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan afn float @llvm.fabs.f32(float [[Y]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp nnan afn oeq float [[TMP16]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP19:%.*]] = and i1 [[TMP17]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan afn olt float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn i1 [[TMP20]], float [[TMP6]], float [[TMP7]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = select nnan afn i1 [[TMP19]], float [[TMP21]], float [[TMP15]]
+; NOPRELINK-NEXT: ret float [[TMP22]]
;
%powr = tail call afn nnan float @_Z4powrff(float %x, float %y)
ret float %powr
@@ -1548,31 +1875,36 @@ define float @test_powr_afn_f32_nnan_ninf_x_known_positive(float nofpclass(ninf
}
define <2 x float> @test_powr_afn_v2f32_nnan_x_known_positive(<2 x float> nofpclass(ninf nnorm nsub) %x, <2 x float> %y) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_nnan_x_known_positive
-; CHECK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call nnan afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul nnan afn <2 x float> [[Y]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fcmp nnan afn olt <2 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP6:%.*]] = select nnan afn <2 x i1> [[TMP5]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> zeroinitializer
-; CHECK-NEXT: [[TMP7:%.*]] = select nnan afn <2 x i1> [[TMP5]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp nnan afn oeq <2 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP9:%.*]] = select nnan afn <2 x i1> [[TMP8]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP11:%.*]] = select nnan afn <2 x i1> [[TMP10]], <2 x float> [[TMP9]], <2 x float> [[TMP4]]
-; CHECK-NEXT: [[TMP12:%.*]] = fcmp nnan afn oeq <2 x float> [[X]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une <2 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP12]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select nnan afn <2 x i1> [[TMP14]], <2 x float> [[TMP7]], <2 x float> [[TMP11]]
-; CHECK-NEXT: [[TMP16:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[Y]])
-; CHECK-NEXT: [[TMP17:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP16]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une <2 x float> [[X]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP19:%.*]] = and <2 x i1> [[TMP17]], [[TMP18]]
-; CHECK-NEXT: [[TMP20:%.*]] = fcmp nnan afn olt <2 x float> [[X]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP21:%.*]] = select nnan afn <2 x i1> [[TMP20]], <2 x float> [[TMP6]], <2 x float> [[TMP7]]
-; CHECK-NEXT: [[TMP22:%.*]] = select nnan afn <2 x i1> [[TMP19]], <2 x float> [[TMP21]], <2 x float> [[TMP15]]
-; CHECK-NEXT: ret <2 x float> [[TMP22]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_nnan_x_known_positive
+; PRELINK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call nnan afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_nnan_x_known_positive
+; NOPRELINK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan afn <2 x float> [[Y]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan afn olt <2 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan afn <2 x i1> [[TMP5]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan afn <2 x i1> [[TMP5]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp nnan afn oeq <2 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan afn <2 x i1> [[TMP8]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp nnan afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select nnan afn <2 x i1> [[TMP10]], <2 x float> [[TMP9]], <2 x float> [[TMP4]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp nnan afn oeq <2 x float> [[X]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp nnan afn une <2 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP12]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan afn <2 x i1> [[TMP14]], <2 x float> [[TMP7]], <2 x float> [[TMP11]]
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call nnan afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[Y]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp nnan afn oeq <2 x float> [[TMP16]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp nnan afn une <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP19:%.*]] = and <2 x i1> [[TMP17]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan afn olt <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan afn <2 x i1> [[TMP20]], <2 x float> [[TMP6]], <2 x float> [[TMP7]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = select nnan afn <2 x i1> [[TMP19]], <2 x float> [[TMP21]], <2 x float> [[TMP15]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP22]]
;
%powr = tail call afn nnan <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y)
ret <2 x float> %powr
@@ -1601,33 +1933,38 @@ define float @test_powr_f32_x_known_positive(float nofpclass(ninf nnorm nsub) %x
}
define float @test_powr_afn_f32_x_known_positive(float nofpclass(ninf nnorm nsub) %x, float %y) {
-; CHECK-LABEL: define float @test_powr_afn_f32_x_known_positive
-; CHECK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call afn float @llvm.log2.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul afn float [[Y]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.exp2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fcmp afn olt float [[Y]], 0.000000e+00
-; CHECK-NEXT: [[TMP6:%.*]] = select afn i1 [[TMP5]], float 0x7FF0000000000000, float 0.000000e+00
-; CHECK-NEXT: [[TMP7:%.*]] = select afn i1 [[TMP5]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[Y]], 0.000000e+00
-; CHECK-NEXT: [[TMP9:%.*]] = select afn i1 [[TMP8]], float 0x7FF8000000000000, float [[TMP6]]
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP11:%.*]] = select afn i1 [[TMP10]], float [[TMP9]], float [[TMP4]]
-; CHECK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[X]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp afn une float [[Y]], 0.000000e+00
-; CHECK-NEXT: [[TMP14:%.*]] = and i1 [[TMP12]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float [[TMP7]], float [[TMP11]]
-; CHECK-NEXT: [[TMP16:%.*]] = call afn float @llvm.fabs.f32(float [[Y]])
-; CHECK-NEXT: [[TMP17:%.*]] = fcmp afn oeq float [[TMP16]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[X]], 1.000000e+00
-; CHECK-NEXT: [[TMP19:%.*]] = and i1 [[TMP17]], [[TMP18]]
-; CHECK-NEXT: [[TMP20:%.*]] = fcmp afn olt float [[X]], 1.000000e+00
-; CHECK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float [[TMP6]], float [[TMP7]]
-; CHECK-NEXT: [[TMP22:%.*]] = select afn i1 [[TMP19]], float [[TMP21]], float [[TMP15]]
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp afn uno float [[X]], [[Y]]
-; CHECK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP23]], float 0x7FF8000000000000, float [[TMP22]]
-; CHECK-NEXT: ret float [[TMP24]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_x_known_positive
+; PRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float [[Y]])
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_x_known_positive
+; NOPRELINK-SAME: (float nofpclass(ninf nsub nnorm) [[X:%.*]], float [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call afn float @llvm.log2.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul afn float [[Y]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.exp2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp afn olt float [[Y]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select afn i1 [[TMP5]], float 0x7FF0000000000000, float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn i1 [[TMP5]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq float [[Y]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn i1 [[TMP8]], float 0x7FF8000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn i1 [[TMP10]], float [[TMP9]], float [[TMP4]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[X]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une float [[Y]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and i1 [[TMP12]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float [[TMP7]], float [[TMP11]]
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn float @llvm.fabs.f32(float [[Y]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn oeq float [[TMP16]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP19:%.*]] = and i1 [[TMP17]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn olt float [[X]], 1.000000e+00
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn i1 [[TMP20]], float [[TMP6]], float [[TMP7]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = select afn i1 [[TMP19]], float [[TMP21]], float [[TMP15]]
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn uno float [[X]], [[Y]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn i1 [[TMP23]], float 0x7FF8000000000000, float [[TMP22]]
+; NOPRELINK-NEXT: ret float [[TMP24]]
;
%powr = tail call afn float @_Z4powrff(float %x, float %y)
ret float %powr
@@ -1644,33 +1981,38 @@ define <2 x float> @test_powr_v2f32_x_known_positive(<2 x float> nofpclass(ninf
}
define <2 x float> @test_powr_afn_v2f32_x_known_positive(<2 x float> nofpclass(ninf nnorm nsub) %x, <2 x float> %y) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_x_known_positive
-; CHECK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul afn <2 x float> [[Y]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fcmp afn olt <2 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP6:%.*]] = select afn <2 x i1> [[TMP5]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> zeroinitializer
-; CHECK-NEXT: [[TMP7:%.*]] = select afn <2 x i1> [[TMP5]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP9:%.*]] = select afn <2 x i1> [[TMP8]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP11:%.*]] = select afn <2 x i1> [[TMP10]], <2 x float> [[TMP9]], <2 x float> [[TMP4]]
-; CHECK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP13:%.*]] = fcmp afn une <2 x float> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP12]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP7]], <2 x float> [[TMP11]]
-; CHECK-NEXT: [[TMP16:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[Y]])
-; CHECK-NEXT: [[TMP17:%.*]] = fcmp afn oeq <2 x float> [[TMP16]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp afn une <2 x float> [[X]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP19:%.*]] = and <2 x i1> [[TMP17]], [[TMP18]]
-; CHECK-NEXT: [[TMP20:%.*]] = fcmp afn olt <2 x float> [[X]], splat (float 1.000000e+00)
-; CHECK-NEXT: [[TMP21:%.*]] = select afn <2 x i1> [[TMP20]], <2 x float> [[TMP6]], <2 x float> [[TMP7]]
-; CHECK-NEXT: [[TMP22:%.*]] = select afn <2 x i1> [[TMP19]], <2 x float> [[TMP21]], <2 x float> [[TMP15]]
-; CHECK-NEXT: [[TMP23:%.*]] = fcmp afn uno <2 x float> [[X]], [[Y]]
-; CHECK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP22]]
-; CHECK-NEXT: ret <2 x float> [[TMP24]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_x_known_positive
+; PRELINK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y]])
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_x_known_positive
+; NOPRELINK-SAME: (<2 x float> nofpclass(ninf nsub nnorm) [[X:%.*]], <2 x float> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul afn <2 x float> [[Y]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp afn olt <2 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select afn <2 x i1> [[TMP5]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn <2 x i1> [[TMP5]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp afn oeq <2 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn <2 x i1> [[TMP8]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn <2 x i1> [[TMP10]], <2 x float> [[TMP9]], <2 x float> [[TMP4]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq <2 x float> [[X]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP13:%.*]] = fcmp afn une <2 x float> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP14:%.*]] = and <2 x i1> [[TMP12]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> [[TMP7]], <2 x float> [[TMP11]]
+; NOPRELINK-NEXT: [[TMP16:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[Y]])
+; NOPRELINK-NEXT: [[TMP17:%.*]] = fcmp afn oeq <2 x float> [[TMP16]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn une <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP19:%.*]] = and <2 x i1> [[TMP17]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp afn olt <2 x float> [[X]], splat (float 1.000000e+00)
+; NOPRELINK-NEXT: [[TMP21:%.*]] = select afn <2 x i1> [[TMP20]], <2 x float> [[TMP6]], <2 x float> [[TMP7]]
+; NOPRELINK-NEXT: [[TMP22:%.*]] = select afn <2 x i1> [[TMP19]], <2 x float> [[TMP21]], <2 x float> [[TMP15]]
+; NOPRELINK-NEXT: [[TMP23:%.*]] = fcmp afn uno <2 x float> [[X]], [[Y]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = select afn <2 x i1> [[TMP23]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP22]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP24]]
;
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y)
ret <2 x float> %powr
@@ -1689,29 +2031,35 @@ define float @test_powr_f32_known_integral_sitofp(float %x, i32 %y) {
}
define float @test_powr_afn_f32_known_integral_sitofp(float %x, i32 %y) {
-; CHECK-LABEL: define float @test_powr_afn_f32_known_integral_sitofp
-; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], [[Y_CAST]]
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = icmp slt i32 [[Y]], 0
-; CHECK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float 0.000000e+00
-; CHECK-NEXT: [[TMP9:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[Y]], 0
-; CHECK-NEXT: [[TMP11:%.*]] = select afn i1 [[TMP10]], float 0x7FF8000000000000, float [[TMP8]]
-; CHECK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[TMP11]], float [[TMP6]]
-; CHECK-NEXT: [[TMP14:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i32 [[Y]], 0
-; CHECK-NEXT: [[TMP16:%.*]] = and i1 [[TMP14]], [[TMP15]]
-; CHECK-NEXT: [[TMP17:%.*]] = select afn i1 [[TMP16]], float [[TMP9]], float [[TMP13]]
-; CHECK-NEXT: [[TMP18:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP17]]
-; CHECK-NEXT: ret float [[TMP19]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_known_integral_sitofp
+; PRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float [[Y_CAST]])
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_known_integral_sitofp
+; NOPRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = sitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], [[Y_CAST]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = icmp slt i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF0000000000000, float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select afn i1 [[TMP7]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select afn i1 [[TMP10]], float 0x7FF8000000000000, float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select afn i1 [[TMP12]], float [[TMP11]], float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP15:%.*]] = icmp ne i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP16:%.*]] = and i1 [[TMP14]], [[TMP15]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = select afn i1 [[TMP16]], float [[TMP9]], float [[TMP13]]
+; NOPRELINK-NEXT: [[TMP18:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP19:%.*]] = select afn i1 [[TMP18]], float 0x7FF8000000000000, float [[TMP17]]
+; NOPRELINK-NEXT: ret float [[TMP19]]
;
%y.cast = sitofp i32 %y to float
%powr = tail call afn float @_Z4powrff(float %x, float %y.cast)
@@ -1745,26 +2093,32 @@ define float @test_powr_f32_known_integral_uitofp(float %x, i32 %y) {
}
define float @test_powr_afn_f32_known_integral_uitofp(float %x, i32 %y) {
-; CHECK-LABEL: define float @test_powr_afn_f32_known_integral_uitofp
-; CHECK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = uitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], [[Y_CAST]]
-; CHECK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[Y]], 0
-; CHECK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF8000000000000, float 0.000000e+00
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float [[TMP8]], float [[TMP6]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i32 [[Y]], 0
-; CHECK-NEXT: [[TMP13:%.*]] = and i1 [[TMP11]], [[TMP12]]
-; CHECK-NEXT: [[TMP14:%.*]] = select afn i1 [[TMP13]], float 0x7FF0000000000000, float [[TMP10]]
-; CHECK-NEXT: [[TMP15:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
-; CHECK-NEXT: [[TMP16:%.*]] = select afn i1 [[TMP15]], float 0x7FF8000000000000, float [[TMP14]]
-; CHECK-NEXT: ret float [[TMP16]]
+; PRELINK-LABEL: define float @test_powr_afn_f32_known_integral_uitofp
+; PRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = uitofp i32 [[Y]] to float
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn float @_Z11__powr_fastff(float [[X]], float [[Y_CAST]])
+; PRELINK-NEXT: ret float [[POWR]]
+;
+; NOPRELINK-LABEL: define float @test_powr_afn_f32_known_integral_uitofp
+; NOPRELINK-SAME: (float [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = uitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn i1 [[TMP1]], float 0x7FF8000000000000, float [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.fabs.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.log2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn float [[TMP4]], [[Y_CAST]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn float @llvm.exp2.f32(float [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn i1 [[TMP7]], float 0x7FF8000000000000, float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn i1 [[TMP9]], float [[TMP8]], float [[TMP6]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[TMP2]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP12:%.*]] = icmp ne i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP13:%.*]] = and i1 [[TMP11]], [[TMP12]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = select afn i1 [[TMP13]], float 0x7FF0000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn uno float [[TMP2]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[TMP15]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: ret float [[TMP16]]
;
%y.cast = uitofp i32 %y to float
%powr = tail call afn float @_Z4powrff(float %x, float %y.cast)
@@ -1812,26 +2166,32 @@ define <2 x float> @test_powr_v2f32_known_integral_uitofp(<2 x float> %x, <2 x i
}
define <2 x float> @test_powr_afn_v2f32_known_integral_uitofp(<2 x float> %x, <2 x i32> %y) {
-; CHECK-LABEL: define <2 x float> @test_powr_afn_v2f32_known_integral_uitofp
-; CHECK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
-; CHECK-NEXT: [[Y_CAST:%.*]] = uitofp <2 x i32> [[Y]] to <2 x float>
-; CHECK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], [[Y_CAST]]
-; CHECK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
-; CHECK-NEXT: [[TMP7:%.*]] = icmp eq <2 x i32> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> zeroinitializer
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> [[TMP8]], <2 x float> [[TMP6]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP12:%.*]] = icmp ne <2 x i32> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP13:%.*]] = and <2 x i1> [[TMP11]], [[TMP12]]
-; CHECK-NEXT: [[TMP14:%.*]] = select afn <2 x i1> [[TMP13]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP10]]
-; CHECK-NEXT: [[TMP15:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
-; CHECK-NEXT: [[TMP16:%.*]] = select afn <2 x i1> [[TMP15]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
-; CHECK-NEXT: ret <2 x float> [[TMP16]]
+; PRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_known_integral_uitofp
+; PRELINK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
+; PRELINK-NEXT: [[Y_CAST:%.*]] = uitofp <2 x i32> [[Y]] to <2 x float>
+; PRELINK-NEXT: [[POWR:%.*]] = tail call afn <2 x float> @_Z11__powr_fastDv2_fS_(<2 x float> [[X]], <2 x float> [[Y_CAST]])
+; PRELINK-NEXT: ret <2 x float> [[POWR]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_powr_afn_v2f32_known_integral_uitofp
+; NOPRELINK-SAME: (<2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
+; NOPRELINK-NEXT: [[Y_CAST:%.*]] = uitofp <2 x i32> [[Y]] to <2 x float>
+; NOPRELINK-NEXT: [[TMP1:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP2:%.*]] = select afn <2 x i1> [[TMP1]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fmul afn <2 x float> [[TMP4]], [[Y_CAST]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP5]])
+; NOPRELINK-NEXT: [[TMP7:%.*]] = icmp eq <2 x i32> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select afn <2 x i1> [[TMP9]], <2 x float> [[TMP8]], <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq <2 x float> [[TMP2]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP12:%.*]] = icmp ne <2 x i32> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP13:%.*]] = and <2 x i1> [[TMP11]], [[TMP12]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = select afn <2 x i1> [[TMP13]], <2 x float> splat (float 0x7FF0000000000000), <2 x float> [[TMP10]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = fcmp afn uno <2 x float> [[TMP2]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn <2 x i1> [[TMP15]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP14]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP16]]
;
%y.cast = uitofp <2 x i32> %y to <2 x float>
%powr = tail call afn <2 x float> @_Z4powrDv2_fS_(<2 x float> %x, <2 x float> %y.cast)
@@ -1856,3 +2216,6 @@ attributes #0 = { minsize }
attributes #1 = { noinline }
attributes #2 = { strictfp }
attributes #3 = { nobuiltin }
+
+!llvm.module.flags = !{!0}
+!0 = !{i32 1, !"amdgpu-libcall-have-fast-pow", i32 1}
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-fast.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-fast.ll
new file mode 100644
index 0000000000000..812f56a8d6f64
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn-fast.ll
@@ -0,0 +1,452 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink %s | FileCheck %s
+
+define float @test_rootn_afn_f32(float %x, i32 %y) #0 {
+; CHECK-LABEL: define float @test_rootn_afn_f32(
+; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn float @_Z12__rootn_fastfi(float [[X]], i32 [[Y]])
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call afn float @_Z5rootnfi(float %x, i32 %y)
+ ret float %call
+}
+
+declare float @_Z5rootnfi(float, i32) #1
+
+define <2 x float> @test_rootn_afn_v2f32(<2 x float> %x, <2 x i32> %y) #0 {
+; CHECK-LABEL: define <2 x float> @test_rootn_afn_v2f32(
+; CHECK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z12__rootn_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[Y]])
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> %y)
+ ret <2 x float> %call
+}
+
+declare <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float>, <2 x i32>) #1
+
+define <3 x float> @test_rootn_afn_v3f32(<3 x float> %x, <3 x i32> %y) #0 {
+; CHECK-LABEL: define <3 x float> @test_rootn_afn_v3f32(
+; CHECK-SAME: <3 x float> [[X:%.*]], <3 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <3 x float> @_Z12__rootn_fastDv3_fDv3_i(<3 x float> [[X]], <3 x i32> [[Y]])
+; CHECK-NEXT: ret <3 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <3 x float> @_Z5rootnDv3_fDv3_i(<3 x float> %x, <3 x i32> %y)
+ ret <3 x float> %call
+}
+
+declare <3 x float> @_Z5rootnDv3_fDv3_i(<3 x float>, <3 x i32>) #1
+
+define <4 x float> @test_rootn_afn_v4f32(<4 x float> %x, <4 x i32> %y) #0 {
+; CHECK-LABEL: define <4 x float> @test_rootn_afn_v4f32(
+; CHECK-SAME: <4 x float> [[X:%.*]], <4 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <4 x float> @_Z12__rootn_fastDv4_fDv4_i(<4 x float> [[X]], <4 x i32> [[Y]])
+; CHECK-NEXT: ret <4 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <4 x float> @_Z5rootnDv4_fDv4_i(<4 x float> %x, <4 x i32> %y)
+ ret <4 x float> %call
+}
+
+declare <4 x float> @_Z5rootnDv4_fDv4_i(<4 x float>, <4 x i32>) #1
+
+define <8 x float> @test_rootn_afn_v8f32(<8 x float> %x, <8 x i32> %y) #0 {
+; CHECK-LABEL: define <8 x float> @test_rootn_afn_v8f32(
+; CHECK-SAME: <8 x float> [[X:%.*]], <8 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <8 x float> @_Z12__rootn_fastDv8_fDv8_i(<8 x float> [[X]], <8 x i32> [[Y]])
+; CHECK-NEXT: ret <8 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <8 x float> @_Z5rootnDv8_fDv8_i(<8 x float> %x, <8 x i32> %y)
+ ret <8 x float> %call
+}
+
+declare <8 x float> @_Z5rootnDv8_fDv8_i(<8 x float>, <8 x i32>) #1
+
+define <16 x float> @test_rootn_afn_v16f32(<16 x float> %x, <16 x i32> %y) #0 {
+; CHECK-LABEL: define <16 x float> @test_rootn_afn_v16f32(
+; CHECK-SAME: <16 x float> [[X:%.*]], <16 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <16 x float> @_Z12__rootn_fastDv16_fDv16_i(<16 x float> [[X]], <16 x i32> [[Y]])
+; CHECK-NEXT: ret <16 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <16 x float> @_Z5rootnDv16_fDv16_i(<16 x float> %x, <16 x i32> %y)
+ ret <16 x float> %call
+}
+
+declare <16 x float> @_Z5rootnDv16_fDv16_i(<16 x float>, <16 x i32>) #1
+
+define float @test_rootn_afn_f32__2(float %x) #0 {
+; CHECK-LABEL: define float @test_rootn_afn_f32__2(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = call afn float @llvm.sqrt.f32(float [[X]]), !fpmath [[META0:![0-9]+]]
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call afn float @_Z5rootnfi(float %x, i32 2)
+ ret float %call
+}
+
+define float @test_rootn_afn_f32__3(float %x) #0 {
+; CHECK-LABEL: define float @test_rootn_afn_f32__3(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__ROOTN2CBRT:%.*]] = call afn float @_Z4cbrtf(float [[X]])
+; CHECK-NEXT: ret float [[__ROOTN2CBRT]]
+;
+entry:
+ %call = tail call afn float @_Z5rootnfi(float %x, i32 3)
+ ret float %call
+}
+
+define float @test_rootn_afn_f32__neg1(float %x) #0 {
+; CHECK-LABEL: define float @test_rootn_afn_f32__neg1(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__ROOTN2DIV:%.*]] = fdiv afn float 1.000000e+00, [[X]]
+; CHECK-NEXT: ret float [[__ROOTN2DIV]]
+;
+entry:
+ %call = tail call afn float @_Z5rootnfi(float %x, i32 -1)
+ ret float %call
+}
+
+define float @test_rootn_afn_f32__neg2(float %x) #0 {
+; CHECK-LABEL: define float @test_rootn_afn_f32__neg2(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = call contract afn float @llvm.sqrt.f32(float [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = fdiv contract afn float 1.000000e+00, [[TMP0]], !fpmath [[META0]]
+; CHECK-NEXT: ret float [[TMP1]]
+;
+entry:
+ %call = tail call afn float @_Z5rootnfi(float %x, i32 -2)
+ ret float %call
+}
+
+define <2 x float> @test_rootn_afn_v2f32__2(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_rootn_afn_v2f32__2(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = call afn <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]]), !fpmath [[META0]]
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 2))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_rootn_afn_v2f32__3(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_rootn_afn_v2f32__3(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__ROOTN2CBRT:%.*]] = call afn <2 x float> @_Z4cbrtDv2_f(<2 x float> [[X]])
+; CHECK-NEXT: ret <2 x float> [[__ROOTN2CBRT]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 3))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_rootn_afn_v2f32__neg1(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_rootn_afn_v2f32__neg1(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__ROOTN2DIV:%.*]] = fdiv afn <2 x float> splat (float 1.000000e+00), [[X]]
+; CHECK-NEXT: ret <2 x float> [[__ROOTN2DIV]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 -1))
+ ret <2 x float> %call
+}
+
+define <2 x float> @test_rootn_afn_v2f32__neg2(<2 x float> %x) #0 {
+; CHECK-LABEL: define <2 x float> @test_rootn_afn_v2f32__neg2(
+; CHECK-SAME: <2 x float> [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = call contract afn <2 x float> @llvm.sqrt.v2f32(<2 x float> [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = fdiv contract afn <2 x float> splat (float 1.000000e+00), [[TMP0]], !fpmath [[META0]]
+; CHECK-NEXT: ret <2 x float> [[TMP1]]
+;
+entry:
+ %call = tail call afn <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> splat (i32 -2))
+ ret <2 x float> %call
+}
+
+define float @test__rootn_fast_f32(float %x, i32 %y) #0 {
+; CHECK-LABEL: define float @test__rootn_fast_f32(
+; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z12__rootn_fastfi(float [[X]], i32 [[Y]])
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call float @_Z12__rootn_fastfi(float %x, i32 %y)
+ ret float %call
+}
+
+declare float @_Z12__rootn_fastfi(float, i32) #1
+
+define <2 x float> @test__rootn_fast_v2f32(<2 x float> %x, <2 x i32> %y) #0 {
+; CHECK-LABEL: define <2 x float> @test__rootn_fast_v2f32(
+; CHECK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <2 x float> @_Z12__rootn_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[Y]])
+; CHECK-NEXT: ret <2 x float> [[CALL]]
+;
+entry:
+ %call = tail call <2 x float> @_Z12__rootn_fastDv2_fDv2_i(<2 x float> %x, <2 x i32> %y)
+ ret <2 x float> %call
+}
+
+declare <2 x float> @_Z12__rootn_fastDv2_fDv2_i(<2 x float>, <2 x i32>) #1
+
+define <3 x float> @test__rootn_fast_v3f32(<3 x float> %x, <3 x i32> %y) #0 {
+; CHECK-LABEL: define <3 x float> @test__rootn_fast_v3f32(
+; CHECK-SAME: <3 x float> [[X:%.*]], <3 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <3 x float> @_Z12__rootn_fastDv3_fDv3_i(<3 x float> [[X]], <3 x i32> [[Y]])
+; CHECK-NEXT: ret <3 x float> [[CALL]]
+;
+entry:
+ %call = tail call <3 x float> @_Z12__rootn_fastDv3_fDv3_i(<3 x float> %x, <3 x i32> %y)
+ ret <3 x float> %call
+}
+
+declare <3 x float> @_Z12__rootn_fastDv3_fDv3_i(<3 x float>, <3 x i32>) #1
+
+define <4 x float> @test__rootn_fast_v4f32(<4 x float> %x, <4 x i32> %y) #0 {
+; CHECK-LABEL: define <4 x float> @test__rootn_fast_v4f32(
+; CHECK-SAME: <4 x float> [[X:%.*]], <4 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <4 x float> @_Z12__rootn_fastDv4_fDv4_i(<4 x float> [[X]], <4 x i32> [[Y]])
+; CHECK-NEXT: ret <4 x float> [[CALL]]
+;
+entry:
+ %call = tail call <4 x float> @_Z12__rootn_fastDv4_fDv4_i(<4 x float> %x, <4 x i32> %y)
+ ret <4 x float> %call
+}
+
+declare <4 x float> @_Z12__rootn_fastDv4_fDv4_i(<4 x float>, <4 x i32>) #1
+
+define <8 x float> @test__rootn_fast_v8f32(<8 x float> %x, <8 x i32> %y) #0 {
+; CHECK-LABEL: define <8 x float> @test__rootn_fast_v8f32(
+; CHECK-SAME: <8 x float> [[X:%.*]], <8 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <8 x float> @_Z12__rootn_fastDv8_fDv8_i(<8 x float> [[X]], <8 x i32> [[Y]])
+; CHECK-NEXT: ret <8 x float> [[CALL]]
+;
+entry:
+ %call = tail call <8 x float> @_Z12__rootn_fastDv8_fDv8_i(<8 x float> %x, <8 x i32> %y)
+ ret <8 x float> %call
+}
+
+declare <8 x float> @_Z12__rootn_fastDv8_fDv8_i(<8 x float>, <8 x i32>) #1
+
+define <16 x float> @test__rootn_fast_v16f32(<16 x float> %x, <16 x i32> %y) #0 {
+; CHECK-LABEL: define <16 x float> @test__rootn_fast_v16f32(
+; CHECK-SAME: <16 x float> [[X:%.*]], <16 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call <16 x float> @_Z12__rootn_fastDv16_fDv16_i(<16 x float> [[X]], <16 x i32> [[Y]])
+; CHECK-NEXT: ret <16 x float> [[CALL]]
+;
+entry:
+ %call = tail call <16 x float> @_Z12__rootn_fastDv16_fDv16_i(<16 x float> %x, <16 x i32> %y)
+ ret <16 x float> %call
+}
+
+declare <16 x float> @_Z12__rootn_fastDv16_fDv16_i(<16 x float>, <16 x i32>) #1
+
+define float @test__rootn_fast_f32__1(float %x) #0 {
+; CHECK-LABEL: define float @test__rootn_fast_f32__1(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret float [[X]]
+;
+entry:
+ %call = tail call float @_Z12__rootn_fastfi(float %x, i32 1)
+ ret float %call
+}
+
+define float @test__rootn_fast_afn_f32__1(float %x) #0 {
+; CHECK-LABEL: define float @test__rootn_fast_afn_f32__1(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: ret float [[X]]
+;
+entry:
+ %call = tail call afn float @_Z12__rootn_fastfi(float %x, i32 1)
+ ret float %call
+}
+
+define float @test__rootn_fast_f32__2(float %x) #0 {
+; CHECK-LABEL: define float @test__rootn_fast_f32__2(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = call float @llvm.sqrt.f32(float [[X]]), !fpmath [[META0]]
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call float @_Z12__rootn_fastfi(float %x, i32 2)
+ ret float %call
+}
+
+define float @test__rootn_fast_afn_f32__2(float %x) #0 {
+; CHECK-LABEL: define float @test__rootn_fast_afn_f32__2(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = call afn float @llvm.sqrt.f32(float [[X]]), !fpmath [[META0]]
+; CHECK-NEXT: ret float [[CALL]]
+;
+entry:
+ %call = tail call afn float @_Z12__rootn_fastfi(float %x, i32 2)
+ ret float %call
+}
+
+define float @test__rootn_fast_f32__3(float %x) #0 {
+; CHECK-LABEL: define float @test__rootn_fast_f32__3(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__ROOTN2CBRT:%.*]] = call float @_Z4cbrtf(float [[X]])
+; CHECK-NEXT: ret float [[__ROOTN2CBRT]]
+;
+entry:
+ %call = tail call float @_Z12__rootn_fastfi(float %x, i32 3)
+ ret float %call
+}
+
+define float @test__rootn_fast_afn_f32__3(float %x) #0 {
+; CHECK-LABEL: define float @test__rootn_fast_afn_f32__3(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__ROOTN2CBRT:%.*]] = call afn float @_Z4cbrtf(float [[X]])
+; CHECK-NEXT: ret float [[__ROOTN2CBRT]]
+;
+entry:
+ %call = tail call afn float @_Z12__rootn_fastfi(float %x, i32 3)
+ ret float %call
+}
+
+define float @test__rootn_fast_f32__neg1(float %x) #0 {
+; CHECK-LABEL: define float @test__rootn_fast_f32__neg1(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__ROOTN2DIV:%.*]] = fdiv float 1.000000e+00, [[X]]
+; CHECK-NEXT: ret float [[__ROOTN2DIV]]
+;
+entry:
+ %call = tail call float @_Z12__rootn_fastfi(float %x, i32 -1)
+ ret float %call
+}
+
+define float @test__rootn_fast_afn_f32__neg1(float %x) #0 {
+; CHECK-LABEL: define float @test__rootn_fast_afn_f32__neg1(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[__ROOTN2DIV:%.*]] = fdiv afn float 1.000000e+00, [[X]]
+; CHECK-NEXT: ret float [[__ROOTN2DIV]]
+;
+entry:
+ %call = tail call afn float @_Z12__rootn_fastfi(float %x, i32 -1)
+ ret float %call
+}
+
+define float @test__rootn_fast_f32__neg2(float %x) #0 {
+; CHECK-LABEL: define float @test__rootn_fast_f32__neg2(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = call contract float @llvm.sqrt.f32(float [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = fdiv contract float 1.000000e+00, [[TMP0]], !fpmath [[META0]]
+; CHECK-NEXT: ret float [[TMP1]]
+;
+entry:
+ %call = tail call float @_Z12__rootn_fastfi(float %x, i32 -2)
+ ret float %call
+}
+
+define float @test__rootn_fast_afn_f32__neg2(float %x) #0 {
+; CHECK-LABEL: define float @test__rootn_fast_afn_f32__neg2(
+; CHECK-SAME: float [[X:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = call contract afn float @llvm.sqrt.f32(float [[X]])
+; CHECK-NEXT: [[TMP1:%.*]] = fdiv contract afn float 1.000000e+00, [[TMP0]], !fpmath [[META0]]
+; CHECK-NEXT: ret float [[TMP1]]
+;
+entry:
+ %call = tail call afn float @_Z12__rootn_fastfi(float %x, i32 -2)
+ ret float %call
+}
+
+define double @test_rootn_afn_f64(double %x, i32 %y) #0 {
+; CHECK-LABEL: define double @test_rootn_afn_f64(
+; CHECK-SAME: double [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn double @_Z5rootndi(double [[X]], i32 [[Y]])
+; CHECK-NEXT: ret double [[CALL]]
+;
+entry:
+ %call = tail call afn double @_Z5rootndi(double %x, i32 %y)
+ ret double %call
+}
+
+declare double @_Z5rootndi(double, i32) #0
+
+define <2 x double> @test_rootn_afn_v2f64(<2 x double> %x, <2 x i32> %y) #0 {
+; CHECK-LABEL: define <2 x double> @test_rootn_afn_v2f64(
+; CHECK-SAME: <2 x double> [[X:%.*]], <2 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x double> @_Z5rootnDv2_dDv2_i(<2 x double> [[X]], <2 x i32> [[Y]])
+; CHECK-NEXT: ret <2 x double> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x double> @_Z5rootnDv2_dDv2_i(<2 x double> %x, <2 x i32> %y)
+ ret <2 x double> %call
+}
+
+declare <2 x double> @_Z5rootnDv2_dDv2_i(<2 x double>, <2 x i32>) #0
+
+define half @test_rootn_f16(half noundef %x, i32 %y) #0 {
+; CHECK-LABEL: define half @test_rootn_f16(
+; CHECK-SAME: half noundef [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn half @_Z5rootnDhi(half [[X]], i32 [[Y]])
+; CHECK-NEXT: ret half [[CALL]]
+;
+entry:
+ %call = tail call afn half @_Z5rootnDhi(half %x, i32 %y)
+ ret half %call
+}
+
+declare half @_Z5rootnDhi(half noundef, i32 noundef) #01
+
+define <2 x half> @test_rootn_afn_v2f16(<2 x half> %x, <2 x i32> %y) #0 {
+; CHECK-LABEL: define <2 x half> @test_rootn_afn_v2f16(
+; CHECK-SAME: <2 x half> [[X:%.*]], <2 x i32> [[Y:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call afn <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> [[X]], <2 x i32> [[Y]])
+; CHECK-NEXT: ret <2 x half> [[CALL]]
+;
+entry:
+ %call = tail call afn <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half> %x, <2 x i32> %y)
+ ret <2 x half> %call
+}
+
+declare <2 x half> @_Z5rootnDv2_DhDv2_i(<2 x half>, <2 x i32>) #0
+
+
+attributes #0 = { mustprogress nofree norecurse nounwind willreturn memory(none) }
+attributes #1 = { mustprogress nofree nounwind willreturn memory(none) }
+
+;.
+; CHECK: [[META0]] = !{float 2.000000e+00}
+;.
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
index e3bcad94f1db7..00b4583494c75 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 4
-; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink %s | FileCheck %s
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine -amdgpu-prelink %s | FileCheck -check-prefixes=CHECK,PRELINK %s
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-simplifylib,instcombine %s | FileCheck -check-prefixes=CHECK,NOPRELINK %s
declare float @_Z5rootnfi(float, i32)
declare <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float>, <2 x i32>)
@@ -278,10 +279,15 @@ define half @test_rootn_f16_2(half %x) {
}
define half @test_rootn_f16_3(half %x) {
-; CHECK-LABEL: define half @test_rootn_f16_3(
-; CHECK-SAME: half [[X:%.*]]) {
-; CHECK-NEXT: [[__ROOTN2CBRT:%.*]] = call half @_Z4cbrtDh(half [[X]])
-; CHECK-NEXT: ret half [[__ROOTN2CBRT]]
+; PRELINK-LABEL: define half @test_rootn_f16_3(
+; PRELINK-SAME: half [[X:%.*]]) {
+; PRELINK-NEXT: [[__ROOTN2CBRT:%.*]] = call half @_Z4cbrtDh(half [[X]])
+; PRELINK-NEXT: ret half [[__ROOTN2CBRT]]
+;
+; NOPRELINK-LABEL: define half @test_rootn_f16_3(
+; NOPRELINK-SAME: half [[X:%.*]]) {
+; NOPRELINK-NEXT: [[CALL:%.*]] = tail call half @_Z5rootnDhi(half [[X]], i32 3)
+; NOPRELINK-NEXT: ret half [[CALL]]
;
%call = tail call half @_Z5rootnDhi(half %x, i32 3)
ret half %call
@@ -718,11 +724,17 @@ entry:
}
define float @test_rootn_f32__y_3(float %x) {
-; CHECK-LABEL: define float @test_rootn_f32__y_3(
-; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[__ROOTN2CBRT:%.*]] = call float @_Z4cbrtf(float [[X]])
-; CHECK-NEXT: ret float [[__ROOTN2CBRT]]
+; PRELINK-LABEL: define float @test_rootn_f32__y_3(
+; PRELINK-SAME: float [[X:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[__ROOTN2CBRT:%.*]] = call float @_Z4cbrtf(float [[X]])
+; PRELINK-NEXT: ret float [[__ROOTN2CBRT]]
+;
+; NOPRELINK-LABEL: define float @test_rootn_f32__y_3(
+; NOPRELINK-SAME: float [[X:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 3)
+; NOPRELINK-NEXT: ret float [[CALL]]
;
entry:
%call = tail call float @_Z5rootnfi(float %x, i32 3)
@@ -730,11 +742,17 @@ entry:
}
define <2 x float> @test_rootn_v2f32__y_3(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_rootn_v2f32__y_3(
-; CHECK-SAME: <2 x float> [[X:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[__ROOTN2CBRT:%.*]] = call <2 x float> @_Z4cbrtDv2_f(<2 x float> [[X]])
-; CHECK-NEXT: ret <2 x float> [[__ROOTN2CBRT]]
+; PRELINK-LABEL: define <2 x float> @test_rootn_v2f32__y_3(
+; PRELINK-SAME: <2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[__ROOTN2CBRT:%.*]] = call <2 x float> @_Z4cbrtDv2_f(<2 x float> [[X]])
+; PRELINK-NEXT: ret <2 x float> [[__ROOTN2CBRT]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_rootn_v2f32__y_3(
+; NOPRELINK-SAME: <2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[CALL:%.*]] = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 3))
+; NOPRELINK-NEXT: ret <2 x float> [[CALL]]
;
entry:
%call = tail call <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 3, i32 3>)
@@ -903,7 +921,7 @@ define float @test_rootn_f32__y_neg2__noinline(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_neg2__noinline(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[__ROOTN2RSQRT:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 -2) #[[ATTR4:[0-9]+]]
+; CHECK-NEXT: [[__ROOTN2RSQRT:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 -2) #[[ATTR3:[0-9]+]]
; CHECK-NEXT: ret float [[__ROOTN2RSQRT]]
;
entry:
@@ -915,7 +933,7 @@ define float @test_rootn_f32__y_neg2__nobuiltin(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_neg2__nobuiltin(
; CHECK-SAME: float [[X:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 -2) #[[ATTR5:[0-9]+]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 -2) #[[ATTR4:[0-9]+]]
; CHECK-NEXT: ret float [[CALL]]
;
entry:
@@ -982,35 +1000,41 @@ define float @test_rootn_f32__y_neg4(float %x) {
}
define float @test_rootn_afn_f32(float %x, i32 %y) {
-; CHECK-LABEL: define float @test_rootn_afn_f32(
-; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = sitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = call afn float @llvm.amdgcn.rcp.f32(float [[TMP0]])
-; CHECK-NEXT: [[TMP2:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.log2.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = fmul afn float [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = call afn float @llvm.exp2.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[Y]], 1
-; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP6]], 0
-; CHECK-NEXT: [[TMP7:%.*]] = select afn i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP8:%.*]] = call afn float @llvm.copysign.f32(float [[TMP5]], float [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP12:%.*]] = or i1 [[TMP10]], [[TMP11]]
-; CHECK-NEXT: [[TMP13:%.*]] = icmp slt i32 [[Y]], 0
-; CHECK-NEXT: [[TMP14:%.*]] = xor i1 [[TMP11]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP16:%.*]] = select afn i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP17:%.*]] = call afn float @llvm.copysign.f32(float [[TMP15]], float [[TMP16]])
-; CHECK-NEXT: [[TMP18:%.*]] = select afn i1 [[TMP12]], float [[TMP17]], float [[TMP8]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[DOTNOT]]
-; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i32 [[Y]], 0
-; CHECK-NEXT: [[TMP22:%.*]] = or i1 [[TMP20]], [[TMP21]]
-; CHECK-NEXT: [[CALL:%.*]] = select afn i1 [[TMP22]], float 0x7FF8000000000000, float [[TMP18]]
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_rootn_afn_f32(
+; PRELINK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[CALL:%.*]] = tail call afn float @_Z12__rootn_fastfi(float [[X]], i32 [[Y]])
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_rootn_afn_f32(
+; NOPRELINK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[TMP0:%.*]] = sitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call afn float @llvm.amdgcn.rcp.f32(float [[TMP0]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.log2.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = fmul afn float [[TMP1]], [[TMP3]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn float @llvm.exp2.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = and i32 [[Y]], 1
+; NOPRELINK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP6]], 0
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn float @llvm.copysign.f32(float [[TMP5]], float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP12:%.*]] = or i1 [[TMP10]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = icmp slt i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP14:%.*]] = xor i1 [[TMP11]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn float @llvm.copysign.f32(float [[TMP15]], float [[TMP16]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = select afn i1 [[TMP12]], float [[TMP17]], float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[DOTNOT]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = icmp eq i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP22:%.*]] = or i1 [[TMP20]], [[TMP21]]
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn i1 [[TMP22]], float 0x7FF8000000000000, float [[TMP18]]
+; NOPRELINK-NEXT: ret float [[TMP23]]
;
entry:
%call = tail call afn float @_Z5rootnfi(float %x, i32 %y)
@@ -1018,35 +1042,41 @@ entry:
}
define <2 x float> @test_rootn_afn_v2f32(<2 x float> %x, <2 x i32> %y) {
-; CHECK-LABEL: define <2 x float> @test_rootn_afn_v2f32(
-; CHECK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = sitofp <2 x i32> [[Y]] to <2 x float>
-; CHECK-NEXT: [[TMP1:%.*]] = call afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> [[TMP0]])
-; CHECK-NEXT: [[TMP2:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = fmul afn <2 x float> [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = and <2 x i32> [[Y]], splat (i32 1)
-; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq <2 x i32> [[TMP6]], zeroinitializer
-; CHECK-NEXT: [[TMP7:%.*]] = select afn <2 x i1> [[DOTNOT]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP8:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP5]], <2 x float> [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[TMP9]], splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP12:%.*]] = or <2 x i1> [[TMP10]], [[TMP11]]
-; CHECK-NEXT: [[TMP13:%.*]] = icmp slt <2 x i32> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP14:%.*]] = xor <2 x i1> [[TMP11]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP16:%.*]] = select afn <2 x i1> [[DOTNOT]], <2 x float> zeroinitializer, <2 x float> [[X]]
-; CHECK-NEXT: [[TMP17:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP15]], <2 x float> [[TMP16]])
-; CHECK-NEXT: [[TMP18:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[TMP17]], <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP19:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[DOTNOT]]
-; CHECK-NEXT: [[TMP21:%.*]] = icmp eq <2 x i32> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP22:%.*]] = or <2 x i1> [[TMP20]], [[TMP21]]
-; CHECK-NEXT: [[CALL:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP18]]
-; CHECK-NEXT: ret <2 x float> [[CALL]]
+; PRELINK-LABEL: define <2 x float> @test_rootn_afn_v2f32(
+; PRELINK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[CALL:%.*]] = tail call afn <2 x float> @_Z12__rootn_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[Y]])
+; PRELINK-NEXT: ret <2 x float> [[CALL]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_v2f32(
+; NOPRELINK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[TMP0:%.*]] = sitofp <2 x i32> [[Y]] to <2 x float>
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> [[TMP0]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = fmul afn <2 x float> [[TMP1]], [[TMP3]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = and <2 x i32> [[Y]], splat (i32 1)
+; NOPRELINK-NEXT: [[DOTNOT:%.*]] = icmp eq <2 x i32> [[TMP6]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn <2 x i1> [[DOTNOT]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP5]], <2 x float> [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq <2 x float> [[TMP9]], splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP12:%.*]] = or <2 x i1> [[TMP10]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = icmp slt <2 x i32> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP14:%.*]] = xor <2 x i1> [[TMP11]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn <2 x i1> [[TMP14]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn <2 x i1> [[DOTNOT]], <2 x float> zeroinitializer, <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP15]], <2 x float> [[TMP16]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = select afn <2 x i1> [[TMP12]], <2 x float> [[TMP17]], <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = fcmp afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and <2 x i1> [[TMP19]], [[DOTNOT]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = icmp eq <2 x i32> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP22:%.*]] = or <2 x i1> [[TMP20]], [[TMP21]]
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select afn <2 x i1> [[TMP22]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP18]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP23]]
;
entry:
%call = tail call afn <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> %y)
@@ -1102,32 +1132,38 @@ entry:
}
define float @test_rootn_afn_nnan_ninf_f32(float %x, i32 %y) {
-; CHECK-LABEL: define float @test_rootn_afn_nnan_ninf_f32(
-; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = sitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.amdgcn.rcp.f32(float [[TMP0]])
-; CHECK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP3:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = fmul nnan ninf afn float [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[Y]], 1
-; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP6]], 0
-; CHECK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP5]], float [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP10:%.*]] = icmp slt i32 [[Y]], 0
-; CHECK-NEXT: [[TMP11:%.*]] = xor i1 [[TMP9]], [[TMP10]]
-; CHECK-NEXT: [[TMP12:%.*]] = select nnan ninf afn i1 [[TMP11]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP13:%.*]] = select nnan ninf afn i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP14:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP12]], float [[TMP13]])
-; CHECK-NEXT: [[TMP15:%.*]] = select nnan ninf afn i1 [[TMP9]], float [[TMP14]], float [[TMP8]]
-; CHECK-NEXT: [[TMP16:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP17:%.*]] = and i1 [[TMP16]], [[DOTNOT]]
-; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[Y]], 0
-; CHECK-NEXT: [[TMP19:%.*]] = or i1 [[TMP17]], [[TMP18]]
-; CHECK-NEXT: [[CALL:%.*]] = select nnan ninf afn i1 [[TMP19]], float 0x7FF8000000000000, float [[TMP15]]
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32(
+; PRELINK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 [[Y]])
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32(
+; NOPRELINK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[TMP0:%.*]] = sitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.amdgcn.rcp.f32(float [[TMP0]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = fmul nnan ninf afn float [[TMP1]], [[TMP3]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = and i32 [[Y]], 1
+; NOPRELINK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP6]], 0
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP5]], float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP10:%.*]] = icmp slt i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP11:%.*]] = xor i1 [[TMP9]], [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select nnan ninf afn i1 [[TMP11]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select nnan ninf afn i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP12]], float [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan ninf afn i1 [[TMP9]], float [[TMP14]], float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP17:%.*]] = and i1 [[TMP16]], [[DOTNOT]]
+; NOPRELINK-NEXT: [[TMP18:%.*]] = icmp eq i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP19:%.*]] = or i1 [[TMP17]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = select nnan ninf afn i1 [[TMP19]], float 0x7FF8000000000000, float [[TMP15]]
+; NOPRELINK-NEXT: ret float [[TMP20]]
;
entry:
%call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 %y)
@@ -1135,32 +1171,38 @@ entry:
}
define <2 x float> @test_rootn_afn_nnan_ninf_v2f32(<2 x float> %x, <2 x i32> %y) {
-; CHECK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32(
-; CHECK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = sitofp <2 x i32> [[Y]] to <2 x float>
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> [[TMP0]])
-; CHECK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP3:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = fmul nnan ninf afn <2 x float> [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = and <2 x i32> [[Y]], splat (i32 1)
-; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq <2 x i32> [[TMP6]], zeroinitializer
-; CHECK-NEXT: [[TMP7:%.*]] = select nnan ninf afn <2 x i1> [[DOTNOT]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP5]], <2 x float> [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP10:%.*]] = icmp slt <2 x i32> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP11:%.*]] = xor <2 x i1> [[TMP9]], [[TMP10]]
-; CHECK-NEXT: [[TMP12:%.*]] = select nnan ninf afn <2 x i1> [[TMP11]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP13:%.*]] = select nnan ninf afn <2 x i1> [[DOTNOT]], <2 x float> zeroinitializer, <2 x float> [[X]]
-; CHECK-NEXT: [[TMP14:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP12]], <2 x float> [[TMP13]])
-; CHECK-NEXT: [[TMP15:%.*]] = select nnan ninf afn <2 x i1> [[TMP9]], <2 x float> [[TMP14]], <2 x float> [[TMP8]]
-; CHECK-NEXT: [[TMP16:%.*]] = fcmp nnan ninf afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP17:%.*]] = and <2 x i1> [[TMP16]], [[DOTNOT]]
-; CHECK-NEXT: [[TMP18:%.*]] = icmp eq <2 x i32> [[Y]], zeroinitializer
-; CHECK-NEXT: [[TMP19:%.*]] = or <2 x i1> [[TMP17]], [[TMP18]]
-; CHECK-NEXT: [[CALL:%.*]] = select nnan ninf afn <2 x i1> [[TMP19]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP15]]
-; CHECK-NEXT: ret <2 x float> [[CALL]]
+; PRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32(
+; PRELINK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn <2 x float> @_Z12__rootn_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> [[Y]])
+; PRELINK-NEXT: ret <2 x float> [[CALL]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32(
+; NOPRELINK-SAME: <2 x float> [[X:%.*]], <2 x i32> [[Y:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[TMP0:%.*]] = sitofp <2 x i32> [[Y]] to <2 x float>
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> [[TMP0]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = fmul nnan ninf afn <2 x float> [[TMP1]], [[TMP3]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = and <2 x i32> [[Y]], splat (i32 1)
+; NOPRELINK-NEXT: [[DOTNOT:%.*]] = icmp eq <2 x i32> [[TMP6]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn <2 x i1> [[DOTNOT]], <2 x float> splat (float 1.000000e+00), <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP5]], <2 x float> [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP10:%.*]] = icmp slt <2 x i32> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP11:%.*]] = xor <2 x i1> [[TMP9]], [[TMP10]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select nnan ninf afn <2 x i1> [[TMP11]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP13:%.*]] = select nnan ninf afn <2 x i1> [[DOTNOT]], <2 x float> zeroinitializer, <2 x float> [[X]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP12]], <2 x float> [[TMP13]])
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select nnan ninf afn <2 x i1> [[TMP9]], <2 x float> [[TMP14]], <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: [[TMP16:%.*]] = fcmp nnan ninf afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP17:%.*]] = and <2 x i1> [[TMP16]], [[DOTNOT]]
+; NOPRELINK-NEXT: [[TMP18:%.*]] = icmp eq <2 x i32> [[Y]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP19:%.*]] = or <2 x i1> [[TMP17]], [[TMP18]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = select nnan ninf afn <2 x i1> [[TMP19]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP15]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP20]]
;
entry:
%call = tail call nnan ninf afn <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> %y)
@@ -1219,7 +1261,7 @@ define float @test_rootn_fast_f32_nobuiltin(float %x, i32 %y) {
; CHECK-LABEL: define float @test_rootn_fast_f32_nobuiltin(
; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CALL:%.*]] = tail call fast float @_Z5rootnfi(float [[X]], i32 [[Y]]) #[[ATTR5]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call fast float @_Z5rootnfi(float [[X]], i32 [[Y]]) #[[ATTR4]]
; CHECK-NEXT: ret float [[CALL]]
;
entry:
@@ -1228,35 +1270,41 @@ entry:
}
define float @test_rootn_fast_f32_strictfp(float %x, i32 %y) #1 {
-; CHECK-LABEL: define float @test_rootn_fast_f32_strictfp(
-; CHECK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = call fast float @llvm.experimental.constrained.sitofp.f32.i32(i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
-; CHECK-NEXT: [[TMP1:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP0]]) #[[ATTR0]]
-; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.fabs.f32(float [[X]]) #[[ATTR0]]
-; CHECK-NEXT: [[TMP3:%.*]] = call fast float @llvm.log2.f32(float [[TMP2]]) #[[ATTR0]]
-; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.experimental.constrained.fmul.f32(float [[TMP1]], float [[TMP3]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
-; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.exp2.f32(float [[TMP4]]) #[[ATTR0]]
-; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[Y]], 1
-; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP6]], 0
-; CHECK-NEXT: [[TMP7:%.*]] = select fast i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.copysign.f32(float [[TMP5]], float [[TMP7]]) #[[ATTR0]]
-; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.fabs.f32(float [[X]]) #[[ATTR0]]
-; CHECK-NEXT: [[TMP10:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP9]], float 0x7FF0000000000000, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR0]]
-; CHECK-NEXT: [[TMP11:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[X]], float 0.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR0]]
-; CHECK-NEXT: [[TMP12:%.*]] = or i1 [[TMP10]], [[TMP11]]
-; CHECK-NEXT: [[TMP13:%.*]] = icmp slt i32 [[Y]], 0
-; CHECK-NEXT: [[TMP14:%.*]] = xor i1 [[TMP11]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select fast i1 [[TMP14]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP16:%.*]] = select fast i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP17:%.*]] = call fast float @llvm.copysign.f32(float [[TMP15]], float [[TMP16]]) #[[ATTR0]]
-; CHECK-NEXT: [[TMP18:%.*]] = select fast i1 [[TMP12]], float [[TMP17]], float [[TMP8]]
-; CHECK-NEXT: [[TMP19:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[X]], float 0.000000e+00, metadata !"olt", metadata !"fpexcept.strict") #[[ATTR0]]
-; CHECK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[DOTNOT]]
-; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i32 [[Y]], 0
-; CHECK-NEXT: [[TMP22:%.*]] = or i1 [[TMP20]], [[TMP21]]
-; CHECK-NEXT: [[CALL:%.*]] = select fast i1 [[TMP22]], float 0x7FF8000000000000, float [[TMP18]]
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_rootn_fast_f32_strictfp(
+; PRELINK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[CALL:%.*]] = tail call fast float @_Z12__rootn_fastfi(float [[X]], i32 [[Y]]) #[[ATTR0]]
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_rootn_fast_f32_strictfp(
+; NOPRELINK-SAME: float [[X:%.*]], i32 [[Y:%.*]]) #[[ATTR0]] {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[TMP0:%.*]] = call fast float @llvm.experimental.constrained.sitofp.f32.i32(i32 [[Y]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP0]]) #[[ATTR0]]
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call fast float @llvm.fabs.f32(float [[X]]) #[[ATTR0]]
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call fast float @llvm.log2.f32(float [[TMP2]]) #[[ATTR0]]
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call fast float @llvm.experimental.constrained.fmul.f32(float [[TMP1]], float [[TMP3]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR0]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call fast float @llvm.exp2.f32(float [[TMP4]]) #[[ATTR0]]
+; NOPRELINK-NEXT: [[TMP6:%.*]] = and i32 [[Y]], 1
+; NOPRELINK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP6]], 0
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select fast i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call fast float @llvm.copysign.f32(float [[TMP5]], float [[TMP7]]) #[[ATTR0]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call fast float @llvm.fabs.f32(float [[X]]) #[[ATTR0]]
+; NOPRELINK-NEXT: [[TMP10:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[TMP9]], float 0x7FF0000000000000, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR0]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[X]], float 0.000000e+00, metadata !"oeq", metadata !"fpexcept.strict") #[[ATTR0]]
+; NOPRELINK-NEXT: [[TMP12:%.*]] = or i1 [[TMP10]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = icmp slt i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP14:%.*]] = xor i1 [[TMP11]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select fast i1 [[TMP14]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select fast i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call fast float @llvm.copysign.f32(float [[TMP15]], float [[TMP16]]) #[[ATTR0]]
+; NOPRELINK-NEXT: [[TMP18:%.*]] = select fast i1 [[TMP12]], float [[TMP17]], float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = call i1 @llvm.experimental.constrained.fcmp.f32(float [[X]], float 0.000000e+00, metadata !"olt", metadata !"fpexcept.strict") #[[ATTR0]]
+; NOPRELINK-NEXT: [[TMP20:%.*]] = and i1 [[TMP19]], [[DOTNOT]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = icmp eq i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP22:%.*]] = or i1 [[TMP20]], [[TMP21]]
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select fast i1 [[TMP22]], float 0x7FF8000000000000, float [[TMP18]]
+; NOPRELINK-NEXT: ret float [[TMP23]]
;
entry:
%call = tail call fast float @_Z5rootnfi(float %x, i32 %y) #1
@@ -1264,188 +1312,266 @@ entry:
}
define float @test_rootn_fast_f32__y_poison(float %x) {
-; CHECK-LABEL: define float @test_rootn_fast_f32__y_poison(
-; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: ret float poison
+; PRELINK-LABEL: define float @test_rootn_fast_f32__y_poison(
+; PRELINK-SAME: float [[X:%.*]]) {
+; PRELINK-NEXT: [[CALL:%.*]] = tail call fast float @_Z12__rootn_fastfi(float [[X]], i32 poison)
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_rootn_fast_f32__y_poison(
+; NOPRELINK-SAME: float [[X:%.*]]) {
+; NOPRELINK-NEXT: ret float poison
;
%call = tail call fast float @_Z5rootnfi(float %x, i32 poison)
ret float %call
}
define float @test_rootn_afn_nnan_ninf_f32__y_3(float %x) {
-; CHECK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_3(
-; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[__ROOTN2CBRT:%.*]] = call nnan ninf afn float @_Z4cbrtf(float [[X]])
-; CHECK-NEXT: ret float [[__ROOTN2CBRT]]
+; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_3(
+; PRELINK-SAME: float [[X:%.*]]) {
+; PRELINK-NEXT: [[__ROOTN2CBRT:%.*]] = call nnan ninf afn float @_Z4cbrtf(float [[X]])
+; PRELINK-NEXT: ret float [[__ROOTN2CBRT]]
+;
+; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_3(
+; NOPRELINK-SAME: float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 0x3FD5555560000000
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP8]], float [[TMP5]]
+; NOPRELINK-NEXT: ret float [[TMP9]]
;
%call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 3)
ret float %call
}
define float @test_rootn_afn_nnan_ninf_f32__y_neg3(float %x) {
-; CHECK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg3(
-; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 0xBFD5555560000000
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
-; CHECK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
-; CHECK-NEXT: [[CALL:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP5]], float [[TMP8]]
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg3(
+; PRELINK-SAME: float [[X:%.*]]) {
+; PRELINK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 -3)
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg3(
+; NOPRELINK-SAME: float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 0xBFD5555560000000
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP5]], float [[TMP8]]
+; NOPRELINK-NEXT: ret float [[TMP9]]
;
%call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 -3)
ret float %call
}
define float @test_rootn_afn_nnan_ninf_f32__y_4(float %x) {
-; CHECK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_4(
-; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 2.500000e-01
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float 0.000000e+00, float [[TMP4]]
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[CALL:%.*]] = select nnan ninf afn i1 [[TMP7]], float 0x7FF8000000000000, float [[TMP6]]
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_4(
+; PRELINK-SAME: float [[X:%.*]]) {
+; PRELINK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 4)
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_4(
+; NOPRELINK-SAME: float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 2.500000e-01
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float 0.000000e+00, float [[TMP4]]
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan ninf afn i1 [[TMP7]], float 0x7FF8000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: ret float [[TMP8]]
;
%call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 4)
ret float %call
}
define float @test_rootn_afn_nnan_ninf_f32__y_neg4(float %x) {
-; CHECK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg4(
-; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], -2.500000e-01
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float [[TMP4]], float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[CALL:%.*]] = select nnan ninf afn i1 [[TMP7]], float 0x7FF8000000000000, float [[TMP6]]
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg4(
+; PRELINK-SAME: float [[X:%.*]]) {
+; PRELINK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 -4)
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg4(
+; NOPRELINK-SAME: float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], -2.500000e-01
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float [[TMP4]], float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan ninf afn i1 [[TMP7]], float 0x7FF8000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: ret float [[TMP8]]
;
%call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 -4)
ret float %call
}
define float @test_rootn_afn_nnan_ninf_f32__y_5(float %x) {
-; CHECK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_5(
-; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 0x3FC99999A0000000
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
-; CHECK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
-; CHECK-NEXT: [[CALL:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP8]], float [[TMP5]]
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_5(
+; PRELINK-SAME: float [[X:%.*]]) {
+; PRELINK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 5)
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_5(
+; NOPRELINK-SAME: float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 0x3FC99999A0000000
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP8]], float [[TMP5]]
+; NOPRELINK-NEXT: ret float [[TMP9]]
;
%call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 5)
ret float %call
}
define float @test_rootn_afn_nnan_ninf_f32__y_neg5(float %x) {
-; CHECK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg5(
-; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 0xBFC99999A0000000
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
-; CHECK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
-; CHECK-NEXT: [[CALL:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP5]], float [[TMP8]]
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg5(
+; PRELINK-SAME: float [[X:%.*]]) {
+; PRELINK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 -5)
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg5(
+; NOPRELINK-SAME: float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 0xBFC99999A0000000
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP5]], float [[TMP8]]
+; NOPRELINK-NEXT: ret float [[TMP9]]
;
%call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 -5)
ret float %call
}
define float @test_rootn_afn_nnan_ninf_f32__y_7(float %x) {
-; CHECK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_7(
-; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 0x3FC24924A0000000
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
-; CHECK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
-; CHECK-NEXT: [[CALL:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP8]], float [[TMP5]]
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_7(
+; PRELINK-SAME: float [[X:%.*]]) {
+; PRELINK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 7)
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_7(
+; NOPRELINK-SAME: float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 0x3FC24924A0000000
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP8]], float [[TMP5]]
+; NOPRELINK-NEXT: ret float [[TMP9]]
;
%call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 7)
ret float %call
}
define float @test_rootn_afn_nnan_ninf_f32__y_neg7(float %x) {
-; CHECK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg7(
-; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 0xBFC24924A0000000
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
-; CHECK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
-; CHECK-NEXT: [[CALL:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP5]], float [[TMP8]]
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg7(
+; PRELINK-SAME: float [[X:%.*]]) {
+; PRELINK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 -7)
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg7(
+; NOPRELINK-SAME: float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 0xBFC24924A0000000
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP5]], float [[TMP8]]
+; NOPRELINK-NEXT: ret float [[TMP9]]
;
%call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 -7)
ret float %call
}
define float @test_rootn_afn_nnan_ninf_f32__y_8(float %x) {
-; CHECK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_8(
-; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 1.250000e-01
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float 0.000000e+00, float [[TMP4]]
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[CALL:%.*]] = select nnan ninf afn i1 [[TMP7]], float 0x7FF8000000000000, float [[TMP6]]
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_8(
+; PRELINK-SAME: float [[X:%.*]]) {
+; PRELINK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 8)
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_8(
+; NOPRELINK-SAME: float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], 1.250000e-01
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float 0.000000e+00, float [[TMP4]]
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan ninf afn i1 [[TMP7]], float 0x7FF8000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: ret float [[TMP8]]
;
%call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 8)
ret float %call
}
define float @test_rootn_afn_nnan_ninf_f32__y_neg8(float %x) {
-; CHECK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg8(
-; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], -1.250000e-01
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float [[TMP4]], float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[CALL:%.*]] = select nnan ninf afn i1 [[TMP7]], float 0x7FF8000000000000, float [[TMP6]]
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg8(
+; PRELINK-SAME: float [[X:%.*]]) {
+; PRELINK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 -8)
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_rootn_afn_nnan_ninf_f32__y_neg8(
+; NOPRELINK-SAME: float [[X:%.*]]) {
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP2]], -1.250000e-01
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn i1 [[TMP5]], float [[TMP4]], float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf afn olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan ninf afn i1 [[TMP7]], float 0x7FF8000000000000, float [[TMP6]]
+; NOPRELINK-NEXT: ret float [[TMP8]]
;
%call = tail call nnan ninf afn float @_Z5rootnfi(float %x, i32 -8)
ret float %call
}
define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_3(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_3(
-; CHECK-SAME: <2 x float> [[X:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[__ROOTN2CBRT:%.*]] = call nnan ninf afn <2 x float> @_Z4cbrtDv2_f(<2 x float> [[X]])
-; CHECK-NEXT: ret <2 x float> [[__ROOTN2CBRT]]
+; PRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_3(
+; PRELINK-SAME: <2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[__ROOTN2CBRT:%.*]] = call nnan ninf afn <2 x float> @_Z4cbrtDv2_f(<2 x float> [[X]])
+; PRELINK-NEXT: ret <2 x float> [[__ROOTN2CBRT]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_3(
+; NOPRELINK-SAME: <2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[TMP0:%.*]] = call nnan ninf afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> splat (float 3.000000e+00))
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP0]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP4]], <2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP7]], <2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> [[TMP8]], <2 x float> [[TMP5]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP9]]
;
entry:
%call = tail call afn nnan ninf <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 3, i32 3>)
@@ -1453,19 +1579,25 @@ entry:
}
define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_4(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_4(
-; CHECK-SAME: <2 x float> [[X:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = call nnan ninf afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> splat (float 4.000000e+00))
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP0]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP6:%.*]] = select nnan ninf afn <2 x i1> [[TMP5]], <2 x float> zeroinitializer, <2 x float> [[TMP4]]
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[CALL:%.*]] = select nnan ninf afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP6]]
-; CHECK-NEXT: ret <2 x float> [[CALL]]
+; PRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_4(
+; PRELINK-SAME: <2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn <2 x float> @_Z12__rootn_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 4))
+; PRELINK-NEXT: ret <2 x float> [[CALL]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_4(
+; NOPRELINK-SAME: <2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[TMP0:%.*]] = call nnan ninf afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> splat (float 4.000000e+00))
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP0]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn <2 x i1> [[TMP5]], <2 x float> zeroinitializer, <2 x float> [[TMP4]]
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan ninf afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP8]]
;
entry:
%call = tail call afn nnan ninf <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 4, i32 4>)
@@ -1473,20 +1605,26 @@ entry:
}
define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg3(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg3(
-; CHECK-SAME: <2 x float> [[X:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = call nnan ninf afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> splat (float -3.000000e+00))
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP0]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP4]], <2 x float> [[X]])
-; CHECK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn une <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP7:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP7]], <2 x float> [[X]])
-; CHECK-NEXT: [[CALL:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> [[TMP5]], <2 x float> [[TMP8]]
-; CHECK-NEXT: ret <2 x float> [[CALL]]
+; PRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg3(
+; PRELINK-SAME: <2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn <2 x float> @_Z12__rootn_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -3))
+; PRELINK-NEXT: ret <2 x float> [[CALL]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg3(
+; NOPRELINK-SAME: <2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[TMP0:%.*]] = call nnan ninf afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> splat (float -3.000000e+00))
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP0]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP4]], <2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn une <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP7]], <2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> [[TMP5]], <2 x float> [[TMP8]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP9]]
;
entry:
%call = tail call afn nnan ninf <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 -3, i32 -3>)
@@ -1494,19 +1632,25 @@ entry:
}
define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg4(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg4(
-; CHECK-SAME: <2 x float> [[X:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = call nnan ninf afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> splat (float -4.000000e+00))
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP0]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn une <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP6:%.*]] = select nnan ninf afn <2 x i1> [[TMP5]], <2 x float> [[TMP4]], <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf afn olt <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[CALL:%.*]] = select nnan ninf afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP6]]
-; CHECK-NEXT: ret <2 x float> [[CALL]]
+; PRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg4(
+; PRELINK-SAME: <2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn <2 x float> @_Z12__rootn_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 -4))
+; PRELINK-NEXT: ret <2 x float> [[CALL]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_neg4(
+; NOPRELINK-SAME: <2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[TMP0:%.*]] = call nnan ninf afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> splat (float -4.000000e+00))
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP0]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp nnan ninf afn une <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn <2 x i1> [[TMP5]], <2 x float> [[TMP4]], <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp nnan ninf afn olt <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select nnan ninf afn <2 x i1> [[TMP7]], <2 x float> splat (float 0x7FF8000000000000), <2 x float> [[TMP6]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP8]]
;
entry:
%call = tail call afn nnan ninf <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 -4, i32 -4>)
@@ -1514,20 +1658,26 @@ entry:
}
define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_5(<2 x float> %x) {
-; CHECK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_5(
-; CHECK-SAME: <2 x float> [[X:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = call nnan ninf afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> splat (float 5.000000e+00))
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
-; CHECK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
-; CHECK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP0]], [[TMP2]]
-; CHECK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP4]], <2 x float> [[X]])
-; CHECK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
-; CHECK-NEXT: [[TMP7:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP7]], <2 x float> [[X]])
-; CHECK-NEXT: [[CALL:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> [[TMP8]], <2 x float> [[TMP5]]
-; CHECK-NEXT: ret <2 x float> [[CALL]]
+; PRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_5(
+; PRELINK-SAME: <2 x float> [[X:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn <2 x float> @_Z12__rootn_fastDv2_fDv2_i(<2 x float> [[X]], <2 x i32> splat (i32 5))
+; PRELINK-NEXT: ret <2 x float> [[CALL]]
+;
+; NOPRELINK-LABEL: define <2 x float> @test_rootn_afn_nnan_ninf_v2f32__y_5(
+; NOPRELINK-SAME: <2 x float> [[X:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[TMP0:%.*]] = call nnan ninf afn <2 x float> @llvm.amdgcn.rcp.v2f32(<2 x float> splat (float 5.000000e+00))
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn <2 x float> @llvm.fabs.v2f32(<2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn <2 x float> @llvm.log2.v2f32(<2 x float> [[TMP1]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn <2 x float> [[TMP0]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn <2 x float> @llvm.exp2.v2f32(<2 x float> [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP4]], <2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> zeroinitializer, <2 x float> splat (float 0x7FF0000000000000)
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP7]], <2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn <2 x i1> [[TMP6]], <2 x float> [[TMP8]], <2 x float> [[TMP5]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP9]]
;
entry:
%call = tail call afn nnan ninf <2 x float> @_Z5rootnDv2_fDv2_i(<2 x float> %x, <2 x i32> <i32 5, i32 5>)
@@ -1547,32 +1697,38 @@ entry:
}
define float @test_rootn_afn_f32__x_known_positive(float nofpclass(ninf nsub nnorm) %x, i32 %y) {
-; CHECK-LABEL: define float @test_rootn_afn_f32__x_known_positive(
-; CHECK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = sitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = call afn float @llvm.amdgcn.rcp.f32(float [[TMP0]])
-; CHECK-NEXT: [[TMP2:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.log2.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = fmul afn float [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = call afn float @llvm.exp2.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[Y]], 1
-; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP6]], 0
-; CHECK-NEXT: [[TMP7:%.*]] = select afn i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP8:%.*]] = call afn float @llvm.copysign.f32(float [[TMP5]], float [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP12:%.*]] = or i1 [[TMP10]], [[TMP11]]
-; CHECK-NEXT: [[TMP13:%.*]] = icmp slt i32 [[Y]], 0
-; CHECK-NEXT: [[TMP14:%.*]] = xor i1 [[TMP11]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP16:%.*]] = select afn i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP17:%.*]] = call afn float @llvm.copysign.f32(float [[TMP15]], float [[TMP16]])
-; CHECK-NEXT: [[TMP18:%.*]] = select afn i1 [[TMP12]], float [[TMP17]], float [[TMP8]]
-; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[Y]], 0
-; CHECK-NEXT: [[CALL:%.*]] = select afn i1 [[TMP19]], float 0x7FF8000000000000, float [[TMP18]]
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_rootn_afn_f32__x_known_positive(
+; PRELINK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[CALL:%.*]] = tail call afn float @_Z12__rootn_fastfi(float [[X]], i32 [[Y]])
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_rootn_afn_f32__x_known_positive(
+; NOPRELINK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[TMP0:%.*]] = sitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call afn float @llvm.amdgcn.rcp.f32(float [[TMP0]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.log2.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = fmul afn float [[TMP1]], [[TMP3]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn float @llvm.exp2.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = and i32 [[Y]], 1
+; NOPRELINK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP6]], 0
+; NOPRELINK-NEXT: [[TMP7:%.*]] = select afn i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call afn float @llvm.copysign.f32(float [[TMP5]], float [[TMP7]])
+; NOPRELINK-NEXT: [[TMP9:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP10:%.*]] = fcmp afn oeq float [[TMP9]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP12:%.*]] = or i1 [[TMP10]], [[TMP11]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = icmp slt i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP14:%.*]] = xor i1 [[TMP11]], [[TMP13]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = select afn i1 [[TMP14]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select afn i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP17:%.*]] = call afn float @llvm.copysign.f32(float [[TMP15]], float [[TMP16]])
+; NOPRELINK-NEXT: [[TMP18:%.*]] = select afn i1 [[TMP12]], float [[TMP17]], float [[TMP8]]
+; NOPRELINK-NEXT: [[TMP19:%.*]] = icmp eq i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP20:%.*]] = select afn i1 [[TMP19]], float 0x7FF8000000000000, float [[TMP18]]
+; NOPRELINK-NEXT: ret float [[TMP20]]
;
entry:
%call = tail call afn float @_Z5rootnfi(float %x, i32 %y)
@@ -1580,29 +1736,34 @@ entry:
}
define float @test_rootn_afn_ninf_nnan_f32__x_known_positive(float nofpclass(ninf nsub nnorm) %x, i32 %y) {
-; CHECK-LABEL: define float @test_rootn_afn_ninf_nnan_f32__x_known_positive(
-; CHECK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = sitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.amdgcn.rcp.f32(float [[TMP0]])
-; CHECK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP3:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = fmul nnan ninf afn float [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[Y]], 1
-; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP6]], 0
-; CHECK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP5]], float [[TMP7]])
-; CHECK-NEXT: [[TMP9:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP10:%.*]] = icmp slt i32 [[Y]], 0
-; CHECK-NEXT: [[TMP11:%.*]] = xor i1 [[TMP9]], [[TMP10]]
-; CHECK-NEXT: [[TMP12:%.*]] = select nnan ninf afn i1 [[TMP11]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP13:%.*]] = select nnan ninf afn i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
-; CHECK-NEXT: [[TMP14:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP12]], float [[TMP13]])
-; CHECK-NEXT: [[TMP15:%.*]] = select nnan ninf afn i1 [[TMP9]], float [[TMP14]], float [[TMP8]]
-; CHECK-NEXT: [[TMP16:%.*]] = icmp eq i32 [[Y]], 0
-; CHECK-NEXT: [[CALL:%.*]] = select nnan ninf afn i1 [[TMP16]], float 0x7FF8000000000000, float [[TMP15]]
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_rootn_afn_ninf_nnan_f32__x_known_positive(
+; PRELINK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[CALL:%.*]] = tail call nnan ninf afn float @_Z12__rootn_fastfi(float [[X]], i32 [[Y]])
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_rootn_afn_ninf_nnan_f32__x_known_positive(
+; NOPRELINK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[TMP0:%.*]] = sitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call nnan ninf afn float @llvm.amdgcn.rcp.f32(float [[TMP0]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call nnan ninf afn float @llvm.log2.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul nnan ninf afn float [[TMP1]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = and i32 [[Y]], 1
+; NOPRELINK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP5]], 0
+; NOPRELINK-NEXT: [[TMP6:%.*]] = select nnan ninf afn i1 [[DOTNOT]], float 1.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP7:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[TMP6]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP9:%.*]] = icmp slt i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP10:%.*]] = xor i1 [[TMP8]], [[TMP9]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select nnan ninf afn i1 [[TMP10]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP12:%.*]] = select nnan ninf afn i1 [[DOTNOT]], float 0.000000e+00, float [[X]]
+; NOPRELINK-NEXT: [[TMP13:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP11]], float [[TMP12]])
+; NOPRELINK-NEXT: [[TMP14:%.*]] = select nnan ninf afn i1 [[TMP8]], float [[TMP13]], float [[TMP7]]
+; NOPRELINK-NEXT: [[TMP15:%.*]] = icmp eq i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP16:%.*]] = select nnan ninf afn i1 [[TMP15]], float 0x7FF8000000000000, float [[TMP14]]
+; NOPRELINK-NEXT: ret float [[TMP16]]
;
entry:
%call = tail call afn ninf nnan float @_Z5rootnfi(float %x, i32 %y)
@@ -1610,20 +1771,26 @@ entry:
}
define float @test_rootn_afn_f32__x_known_positive__y_4(float nofpclass(ninf nsub nnorm) %x) {
-; CHECK-LABEL: define float @test_rootn_afn_f32__x_known_positive__y_4(
-; CHECK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP0:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP1:%.*]] = call afn float @llvm.log2.f32(float [[TMP0]])
-; CHECK-NEXT: [[TMP2:%.*]] = fmul afn float [[TMP1]], 2.500000e-01
-; CHECK-NEXT: [[TMP3:%.*]] = call afn float @llvm.exp2.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = call afn float @llvm.fabs.f32(float [[TMP3]])
-; CHECK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP6:%.*]] = fcmp afn oeq float [[TMP5]], 0x7FF0000000000000
-; CHECK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP8:%.*]] = select i1 [[TMP6]], float 0x7FF0000000000000, float [[TMP4]]
-; CHECK-NEXT: [[CALL:%.*]] = select i1 [[TMP7]], float 0.000000e+00, float [[TMP8]]
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_rootn_afn_f32__x_known_positive__y_4(
+; PRELINK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[CALL:%.*]] = tail call afn float @_Z12__rootn_fastfi(float [[X]], i32 4)
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_rootn_afn_f32__x_known_positive__y_4(
+; NOPRELINK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[TMP0:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call afn float @llvm.log2.f32(float [[TMP0]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = fmul afn float [[TMP1]], 2.500000e-01
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call afn float @llvm.exp2.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call afn float @llvm.fabs.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call afn float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp afn oeq float [[TMP5]], 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP7:%.*]] = fcmp afn oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select i1 [[TMP6]], float 0x7FF0000000000000, float [[TMP4]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select i1 [[TMP7]], float 0.000000e+00, float [[TMP8]]
+; NOPRELINK-NEXT: ret float [[TMP9]]
;
entry:
%call = tail call afn float @_Z5rootnfi(float %x, i32 4)
@@ -1657,26 +1824,33 @@ entry:
}
define float @test_fast_rootn_f32_y_known_even(float %x, i32 %y.arg) {
-; CHECK-LABEL: define float @test_fast_rootn_f32_y_known_even(
-; CHECK-SAME: float [[X:%.*]], i32 [[Y_ARG:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[Y:%.*]] = shl i32 [[Y_ARG]], 1
-; CHECK-NEXT: [[TMP0:%.*]] = sitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP0]])
-; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP3:%.*]] = call fast float @llvm.log2.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = fmul fast float [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.exp2.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = fcmp fast oeq float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP7:%.*]] = icmp slt i32 [[Y]], 0
-; CHECK-NEXT: [[TMP8:%.*]] = xor i1 [[TMP6]], [[TMP7]]
-; CHECK-NEXT: [[TMP9:%.*]] = select fast i1 [[TMP8]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP10:%.*]] = select fast i1 [[TMP6]], float [[TMP9]], float [[TMP5]]
-; CHECK-NEXT: [[TMP11:%.*]] = fcmp fast olt float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[Y]], 0
-; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP11]], [[TMP12]]
-; CHECK-NEXT: [[CALL:%.*]] = select fast i1 [[TMP13]], float 0x7FF8000000000000, float [[TMP10]]
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_fast_rootn_f32_y_known_even(
+; PRELINK-SAME: float [[X:%.*]], i32 [[Y_ARG:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[Y:%.*]] = shl i32 [[Y_ARG]], 1
+; PRELINK-NEXT: [[CALL:%.*]] = tail call fast float @_Z12__rootn_fastfi(float [[X]], i32 [[Y]])
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_fast_rootn_f32_y_known_even(
+; NOPRELINK-SAME: float [[X:%.*]], i32 [[Y_ARG:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[Y:%.*]] = shl i32 [[Y_ARG]], 1
+; NOPRELINK-NEXT: [[TMP0:%.*]] = sitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP0]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call fast float @llvm.fabs.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = call fast float @llvm.log2.f32(float [[TMP2]])
+; NOPRELINK-NEXT: [[TMP4:%.*]] = fmul fast float [[TMP1]], [[TMP3]]
+; NOPRELINK-NEXT: [[TMP5:%.*]] = call fast float @llvm.exp2.f32(float [[TMP4]])
+; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp fast oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP7:%.*]] = icmp slt i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP8:%.*]] = xor i1 [[TMP6]], [[TMP7]]
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select fast i1 [[TMP8]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP10:%.*]] = select fast i1 [[TMP6]], float [[TMP9]], float [[TMP5]]
+; NOPRELINK-NEXT: [[TMP11:%.*]] = fcmp fast olt float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP13:%.*]] = or i1 [[TMP11]], [[TMP12]]
+; NOPRELINK-NEXT: [[TMP14:%.*]] = select fast i1 [[TMP13]], float 0x7FF8000000000000, float [[TMP10]]
+; NOPRELINK-NEXT: ret float [[TMP14]]
;
entry:
%y = shl i32 %y.arg, 1
@@ -1685,24 +1859,30 @@ entry:
}
define float @test_fast_rootn_f32_known_positive_y_known_even(float nofpclass(ninf nsub nnorm) %x, i32 %y.arg) {
-; CHECK-LABEL: define float @test_fast_rootn_f32_known_positive_y_known_even(
-; CHECK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y_ARG:%.*]]) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[Y:%.*]] = shl i32 [[Y_ARG]], 1
-; CHECK-NEXT: [[TMP0:%.*]] = sitofp i32 [[Y]] to float
-; CHECK-NEXT: [[TMP1:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP0]])
-; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.fabs.f32(float [[X]])
-; CHECK-NEXT: [[TMP3:%.*]] = call fast float @llvm.log2.f32(float [[TMP2]])
-; CHECK-NEXT: [[TMP4:%.*]] = fmul fast float [[TMP1]], [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = call fast float @llvm.exp2.f32(float [[TMP4]])
-; CHECK-NEXT: [[TMP6:%.*]] = fcmp fast oeq float [[X]], 0.000000e+00
-; CHECK-NEXT: [[TMP7:%.*]] = icmp slt i32 [[Y]], 0
-; CHECK-NEXT: [[TMP8:%.*]] = xor i1 [[TMP6]], [[TMP7]]
-; CHECK-NEXT: [[TMP9:%.*]] = select fast i1 [[TMP8]], float 0.000000e+00, float 0x7FF0000000000000
-; CHECK-NEXT: [[TMP10:%.*]] = select fast i1 [[TMP6]], float [[TMP9]], float [[TMP5]]
-; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i32 [[Y]], 0
-; CHECK-NEXT: [[CALL:%.*]] = select fast i1 [[TMP11]], float 0x7FF8000000000000, float [[TMP10]]
-; CHECK-NEXT: ret float [[CALL]]
+; PRELINK-LABEL: define float @test_fast_rootn_f32_known_positive_y_known_even(
+; PRELINK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y_ARG:%.*]]) {
+; PRELINK-NEXT: entry:
+; PRELINK-NEXT: [[Y:%.*]] = shl i32 [[Y_ARG]], 1
+; PRELINK-NEXT: [[CALL:%.*]] = tail call fast float @_Z12__rootn_fastfi(float [[X]], i32 [[Y]])
+; PRELINK-NEXT: ret float [[CALL]]
+;
+; NOPRELINK-LABEL: define float @test_fast_rootn_f32_known_positive_y_known_even(
+; NOPRELINK-SAME: float nofpclass(ninf nsub nnorm) [[X:%.*]], i32 [[Y_ARG:%.*]]) {
+; NOPRELINK-NEXT: entry:
+; NOPRELINK-NEXT: [[Y:%.*]] = shl i32 [[Y_ARG]], 1
+; NOPRELINK-NEXT: [[TMP0:%.*]] = sitofp i32 [[Y]] to float
+; NOPRELINK-NEXT: [[TMP1:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP0]])
+; NOPRELINK-NEXT: [[TMP2:%.*]] = call fast float @llvm.log2.f32(float [[X]])
+; NOPRELINK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP1]], [[TMP2]]
+; NOPRELINK-NEXT: [[TMP4:%.*]] = call fast float @llvm.exp2.f32(float [[TMP3]])
+; NOPRELINK-NEXT: [[TMP5:%.*]] = fcmp fast oeq float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP6:%.*]] = icmp slt i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP7:%.*]] = xor i1 [[TMP5]], [[TMP6]]
+; NOPRELINK-NEXT: [[TMP8:%.*]] = select fast i1 [[TMP7]], float 0.000000e+00, float 0x7FF0000000000000
+; NOPRELINK-NEXT: [[TMP9:%.*]] = select fast i1 [[TMP5]], float [[TMP8]], float [[TMP4]]
+; NOPRELINK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[Y]], 0
+; NOPRELINK-NEXT: [[TMP11:%.*]] = select fast i1 [[TMP10]], float 0x7FF8000000000000, float [[TMP9]]
+; NOPRELINK-NEXT: ret float [[TMP11]]
;
entry:
%y = shl i32 %y.arg, 1
@@ -1713,7 +1893,7 @@ entry:
define float @test_rootn_f32__y_0_nobuiltin(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_0_nobuiltin(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 0) #[[ATTR5]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 0) #[[ATTR4]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = tail call float @_Z5rootnfi(float %x, i32 0) #0
@@ -1723,7 +1903,7 @@ define float @test_rootn_f32__y_0_nobuiltin(float %x) {
define float @test_rootn_f32__y_1_nobuiltin(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_1_nobuiltin(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 1) #[[ATTR5]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 1) #[[ATTR4]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = tail call float @_Z5rootnfi(float %x, i32 1) #0
@@ -1733,7 +1913,7 @@ define float @test_rootn_f32__y_1_nobuiltin(float %x) {
define float @test_rootn_f32__y_2_nobuiltin(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_2_nobuiltin(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 2) #[[ATTR5]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 2) #[[ATTR4]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = tail call float @_Z5rootnfi(float %x, i32 2) #0
@@ -1743,7 +1923,7 @@ define float @test_rootn_f32__y_2_nobuiltin(float %x) {
define float @test_rootn_f32__y_3_nobuiltin(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_3_nobuiltin(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 3) #[[ATTR5]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 3) #[[ATTR4]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = tail call float @_Z5rootnfi(float %x, i32 3) #0
@@ -1753,7 +1933,7 @@ define float @test_rootn_f32__y_3_nobuiltin(float %x) {
define float @test_rootn_f32__y_neg1_nobuiltin(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_neg1_nobuiltin(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 -1) #[[ATTR5]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 -1) #[[ATTR4]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = tail call float @_Z5rootnfi(float %x, i32 -1) #0
@@ -1763,7 +1943,7 @@ define float @test_rootn_f32__y_neg1_nobuiltin(float %x) {
define float @test_rootn_f32__y_neg2_nobuiltin(float %x) {
; CHECK-LABEL: define float @test_rootn_f32__y_neg2_nobuiltin(
; CHECK-SAME: float [[X:%.*]]) {
-; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 -2) #[[ATTR5]]
+; CHECK-NEXT: [[CALL:%.*]] = tail call float @_Z5rootnfi(float [[X]], i32 -2) #[[ATTR4]]
; CHECK-NEXT: ret float [[CALL]]
;
%call = tail call float @_Z5rootnfi(float %x, i32 -2) #0
@@ -1774,16 +1954,27 @@ attributes #0 = { nobuiltin }
attributes #1 = { strictfp }
attributes #2 = { noinline }
+!llvm.module.flags = !{!1}
!0 = !{float 3.0}
+!1 = !{i32 1, !"amdgpu-libcall-have-fast-pow", i32 1}
+
+;.
+; PRELINK: attributes #[[ATTR0]] = { strictfp }
+; PRELINK: attributes #[[ATTR1:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
+; PRELINK: attributes #[[ATTR2:[0-9]+]] = { nounwind memory(read) }
+; PRELINK: attributes #[[ATTR3]] = { noinline }
+; PRELINK: attributes #[[ATTR4]] = { nobuiltin }
+;.
+; NOPRELINK: attributes #[[ATTR0]] = { strictfp }
+; NOPRELINK: attributes #[[ATTR1:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
+; NOPRELINK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
+; NOPRELINK: attributes #[[ATTR3]] = { noinline }
+; NOPRELINK: attributes #[[ATTR4]] = { nobuiltin }
;.
-; CHECK: attributes #[[ATTR0]] = { strictfp }
-; CHECK: attributes #[[ATTR1:[0-9]+]] = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) }
-; CHECK: attributes #[[ATTR2:[0-9]+]] = { nounwind memory(read) }
-; CHECK: attributes #[[ATTR3:[0-9]+]] = { nocallback nofree nosync nounwind strictfp willreturn memory(inaccessiblemem: readwrite) }
-; CHECK: attributes #[[ATTR4]] = { noinline }
-; CHECK: attributes #[[ATTR5]] = { nobuiltin }
+; PRELINK: [[META0]] = !{float 2.000000e+00}
+; PRELINK: [[META1]] = !{float 3.000000e+00}
;.
-; CHECK: [[META0]] = !{float 2.000000e+00}
-; CHECK: [[META1]] = !{float 3.000000e+00}
+; NOPRELINK: [[META0]] = !{float 2.000000e+00}
+; NOPRELINK: [[META1]] = !{float 3.000000e+00}
;.
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