[llvm] [AMDGPU] fix eliminateFrameIndex to use SGPR frame index (PR #178991)

[via llvm-commits]

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@@ -3082,7 +3082,12 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
     if (!IsMUBUF && !MFI->isBottomOfStack()) {
       // Convert to a swizzled stack address by scaling by the wave size.
       // In an entry function/kernel the offset is already swizzled.
-      bool IsSALU = isSGPRClass(TII->getRegClass(MI->getDesc(), FIOperandNum));
+      const TargetRegisterClass *FiRC =
+          TII->getRegClass(MI->getDesc(), FIOperandNum);
+      // If FiRC is null, fall back to non-SALU handling to avoid crashing.
+      // Some instructions may not have regclass information for FI operands
+      // yet.
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hjagasiaAMD wrote:

I see this on "test_v_cndmask_e64" test in the mir if we dont have the null RegClass check.
Is it not a valid test?

llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1030 -run-pass prologepilog -o - llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir

PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace and instructions to reproduce the bug.
Stack dump:
0.      Program arguments: / build/bin/llc -mtriple=amdgcn -verify-machineinstrs -mcpu=gfx1030 -run-pass prologepilog -o - / llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir
1.      Running pass 'Function Pass Manager' on module '/ llvm/test/CodeGen/AMDGPU/eliminate-frame-index-select.mir'.
2.      Running pass 'Prologue/Epilogue Insertion & Frame Finalization' on function '@test_v_cndmask_e64'
 #0 0x00005602dadd7a0e llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) / llvm/lib/Support/Unix/Signals.inc:842:22
 #1 0x00005602dadd7e8b PrintStackTraceSignalHandler(void*) / llvm/lib/Support/Unix/Signals.inc:924:1
 #2 0x00005602dadd5070 llvm::sys::RunSignalHandlers() / llvm/lib/Support/Signals.cpp:108:20
 #3 0x00005602dadd722d SignalHandler(int, siginfo_t*, void*) / llvm/lib/Support/Unix/Signals.inc:429:14
 #4 0x00007f8950602520 (/lib/x86_64-linux-gnu/libc.so.6+0x42520)
 #5 0x00005602d8187f97 llvm::SIRegisterInfo::hasSGPRs(llvm::TargetRegisterClass const*) / llvm/lib/Target/AMDGPU/SIRegisterInfo.h:276:16
 #6 0x00005602d8187e65 llvm::SIRegisterInfo::isSGPRClass(llvm::TargetRegisterClass const*) / llvm/lib/Target/AMDGPU/SIRegisterInfo.h:227:42
 #7 0x00005602d8540ca9 llvm::SIRegisterInfo::eliminateFrameIndex(llvm::MachineInstrBundleIterator<llvm::MachineInstr, false>, int, unsigned int, llvm::RegScavenger*) const / llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:3086:0



https://github.com/llvm/llvm-project/pull/178991